CN109979880B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN109979880B
CN109979880B CN201711458578.1A CN201711458578A CN109979880B CN 109979880 B CN109979880 B CN 109979880B CN 201711458578 A CN201711458578 A CN 201711458578A CN 109979880 B CN109979880 B CN 109979880B
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layer
forming
gate oxide
oxide layer
gate
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CN109979880A (en
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张焕云
吴健
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part column, and the fin part column comprises a bottom region, a channel region positioned on the bottom region and a top region positioned on the channel region; forming a first isolation layer on the substrate, wherein the first isolation layer covers the bottom area of the fin portion column; forming a first gate oxide layer and a second gate oxide layer on the surface of the side wall of the fin part column channel region, wherein the second gate oxide layer is positioned on the surface of the top of the first gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different; forming a grid structure on the top surface of the first isolation layer, wherein the grid structure covers the first grid oxide layer and the second grid oxide layer; and forming a second isolation layer on the top surface of the gate structure, wherein the second isolation layer covers the side wall of the top region of the fin column. The forming method can improve the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the element density and integration of semiconductor devices increase, the size of transistors also becomes smaller, and the reduction in the size of transistors makes short-channel effects more and more significant.
To reduce short channel effects, finfets operate. The grid electrode of the fin field effect transistor is in a fork-shaped 3D structure similar to a fish fin. The grid electrode of the fin field effect transistor can be switched on and off at the multi-side control circuit of the fin column, so that the short channel effect of the transistor can be well inhibited.
The integration of either planar or finfet devices is still low. In order to improve the integration of a semiconductor structure, a vertical nanowire transistor is proposed.
However, the performance of the existing vertical nanowire transistor is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part column, and the fin part column comprises a bottom region, a channel region positioned on the bottom region and a top region positioned on the channel region; forming a first gate oxide layer and a second gate oxide layer on the surface of the side wall of the fin part column channel region, wherein the second gate oxide layer is positioned on the surface of the top of the first gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different; and forming a grid structure covering the side walls of the first grid oxide layer and the second grid oxide layer.
Optionally, the substrate bottom region is used for connecting a first potential, and the fin pillar top region is used for connecting a second potential; the first electric potential is greater than the second electric potential, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer; or the second potential is greater than the first potential, and the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer.
Optionally, the thickness of the first gate oxide layer is greater than that of the second gate oxide layer, and after the first gate oxide layer is formed, the second gate oxide layer is formed; the method for forming the first gate oxide layer comprises the following steps: performing first oxidation treatment on the fin part column channel region and the top region, and forming a first initial gate oxide layer on the surfaces of the fin part column channel region and the top region; removing the first initial gate oxide layer of the top region and part of the channel region in contact with the top region to form a first gate oxide layer; the method for forming the second gate oxide layer comprises the following steps: and carrying out second oxidation treatment on the fin portion column, and forming a second gate oxide layer on the surface of the exposed fin portion column.
Optionally, the method further includes: forming a first isolation layer on the substrate, wherein the first isolation layer covers the bottom region of the fin column, and the grid structure is positioned on the top surface of the first isolation layer; forming a second isolation layer on the top surface of the grid structure, wherein the second isolation layer covers the side wall of the top area of the fin column; the method for removing the top region and the part of the channel region first initial gate oxide layer contacted with the top region comprises the following steps: forming a sacrificial layer on the top surface of the first isolation layer, wherein the sacrificial layer completely covers the top surface of the first isolation layer and covers a part of the first initial gate oxide layer of the channel region, the top surface of the sacrificial layer is lower than the top surface of the channel region, and the material of the sacrificial layer is different from that of the first isolation layer; and etching the first initial gate oxide layer by taking the sacrificial layer as a mask, and removing the exposed first initial gate oxide layer to form a first gate oxide layer.
Optionally, the sacrificial layer is made of polysilicon, amorphous silicon, amorphous carbon or an organic dielectric material; the first isolation layer is made of silicon oxide, silicon nitride or low-k dielectric materials.
Optionally, the first oxidation treatment process includes an in-situ water vapor generation process; the technological parameters of the first oxidation treatment comprise that the reaction temperature is 850-1050 ℃; the second oxidation treatment process comprises an in-situ water vapor generation process; the technological parameters of the second oxidation treatment include that the reaction temperature is 850-1050 ℃.
Optionally, the thickness of the first gate oxide layer is 35 angstroms to 45 angstroms; the thickness of the second gate oxide layer is 13-17 angstroms.
Optionally, the method for removing the first initial gate oxide layer of the top region and a part of the channel region in contact with the top region includes: forming a protective side wall covering a part of the side wall of the first initial gate oxide layer, wherein the top of the protective side wall is lower than the surface of the top of the channel region; and etching the first initial gate oxide layer by taking the protective side wall as a mask, and removing the first initial gate oxide layer exposed by the protective side wall to form a first gate oxide layer.
Optionally, the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer; the method for forming the first gate oxide layer and the second gate oxide layer comprises the following steps: performing third oxidation treatment on the fin part column channel region and the top region, and forming first gate oxide layers on the surfaces of the side walls of the fin part column channel region and the top region; forming a pattern layer covering the first gate oxide layer, wherein the top surface of the pattern layer is lower than that of the channel region; and performing fourth oxidation treatment on the fin part column by taking the pattern layer as a mask, increasing the thickness of the exposed first gate oxide layer, and forming a second gate oxide layer.
Optionally, after the forming the gate structure, the method further includes: and removing the second gate oxide layer in the top area.
Optionally, before forming the gate structure, the method further includes: forming a first source drain doping layer on the surface of the substrate, wherein the first source drain doping layer covers the side wall of the bottom area of the fin portion column; the grid structure is positioned at the top of the first source-drain doped layer.
Optionally, before forming the gate structure, the method further includes: forming a first conductive structure on the surface of the substrate, wherein the first conductive structure is electrically connected with the bottom region of the fin column; the gate structure is located on top of the first conductive structure.
Optionally, after forming the first gate oxide layer and the second gate oxide layer, the method further includes: forming a dielectric layer on the substrate; the dielectric layer covers the side wall of the grid structure; the method for forming the grid structure and the dielectric layer comprises the following steps: forming a pseudo gate structure covering the first gate oxide layer, the second gate oxide layer and the side wall of the top area of the fin portion column; forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure and exposes the top surface of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the dielectric layer; forming a first gate structure layer in the gate opening; and removing the first grid structure layer in the top area to form a grid structure.
Optionally, the number of the fin portion columns is multiple, and the gate structures on the surfaces of the fin portion columns are mutually separated; the method for forming the dummy gate structure comprises the following steps: forming a dummy gate layer on the substrate, wherein the dummy gate layer covers the side wall of the channel region of the fin portion column, the side wall of the top region and the surface of the top portion; and etching the pseudo gate layer, removing part of the pseudo gate layer to form a pseudo gate structure, wherein the pseudo gate structures covering the adjacent fin portion columns are mutually separated.
Optionally, the method further includes: forming a first source drain doping layer on the surface of the substrate, wherein the first source drain doping layer covers the side wall of the bottom area of the fin portion column; the grid structure is positioned at the top of the first source-drain doping layer; after the gate structure is formed, the method further comprises the following steps: forming a first contact hole in the dielectric layer, wherein the bottom of the first contact hole is exposed out of the first source drain doping layer; after the first contact hole is formed, performing first supplementary ion implantation on the first source drain doping layer exposed at the bottom of the first contact hole, and forming a first high doping region in the first source drain doping layer; and forming a first interconnection structure in the first contact hole after the first supplementary ion implantation.
Optionally, the method for forming the gate structure includes: forming a second grid structure layer on the top of the substrate, wherein the second grid structure layer covers the first grid oxide layer, the second grid oxide layer and the side wall of the top area of the fin part column; and etching the second gate structure layer, and removing the second gate structure layer in the top region to form a gate structure.
Optionally, before forming the gate structure, the method further includes: forming a first source drain doped region in the bottom region of the fin column or the substrate; after the gate structure is formed, the method further comprises the following steps: performing ion implantation on the fin portion column top region, and forming a second source drain doped region in the fin portion column top region; or, before forming the gate structure, further comprising: forming a barrier layer on the surface of the side wall of the fin part column channel region; performing ion implantation on the fin portion column by taking the barrier layer as a mask, forming a first source drain doped region in the bottom region of the fin portion column, and forming a second source drain doped region in the top region of the fin portion column; or, further comprising: forming a second isolation layer on the top surface of the gate structure, wherein the second isolation layer covers the side wall of the top region of the fin column, the top region of the fin column is removed, and a source drain groove is formed in the second isolation layer; and forming a second source-drain doping layer in the source-drain groove.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises: the device comprises a substrate, a first electrode, a second electrode, a third electrode, a fourth electrode, a fifth electrode, a sixth electrode, a fifth; the first gate oxide layer and the second gate oxide layer are positioned on the surface of the side wall of the fin part column channel region, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different; and the grid structure covers the first grid oxide layer and the second grid oxide layer.
Optionally, the method further includes: a first isolation layer on the substrate, the first isolation layer covering the fin column bottom region; the dielectric layer is positioned on the first isolation layer and covers the side wall of the grid structure; the top surface of the dielectric layer is higher than or flush with the top surface of the fin portion column; the dielectric layer is provided with an isolation opening, and the bottom of the isolation opening is exposed out of the top of the grid structure; and the second isolation layer is positioned in the isolation opening, is positioned on the top surface of the grid structure and covers the side wall of the top area of the fin column.
Optionally, the method further includes: the first source-drain doping layer is positioned on the surface of the substrate, covers the bottom area of the fin column, and covers the top surface of the first source-drain doping layer; the first contact hole is positioned in the dielectric layer, and the bottom of the first contact hole is exposed out of the first source drain doping layer; the first high-doping region is positioned in the first source drain doping layer at the bottom of the first contact hole; a first interconnect structure in the first contact hole.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the arrangement directions of the bottom region, the channel region and the top region are vertical to the surface of the substrate, and the bottom region and the top region are respectively used for forming the source region and the drain region of the semiconductor structure, so that the arrangement directions of the source region, the drain region and the grid electrode of the formed semiconductor structure are vertical to the surface of the substrate, the area of the surface of the substrate occupied by the formed semiconductor structure is small, and the integration level of the formed semiconductor structure is high. In addition, before the grid structure is formed, a first grid oxide layer and a second grid oxide layer are formed on the surface of the side wall of the fin portion column channel region, and the thicknesses of the first grid oxide layer and the second grid oxide layer are different. Because the electric potentials applied to the bottom area and the top area of the fin column are different, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different, the gate oxide layer on the side with the higher electric potential of the fin column can be thicker, and therefore the first gate oxide layer and the second gate oxide layer are not easy to break down; in addition, the gate oxide layer on the lower side of the potential is made thinner, so that the threshold voltage of the formed semiconductor structure is not easy to increase, and the energy consumption can be further reduced.
Further, the sacrificial layer completely covers the top surface of the first isolation layer, so that in the process of etching the first initial gate oxide layer, the sacrificial layer can protect the first isolation layer and reduce the loss of the first isolation layer. The material of the sacrificial layer is different from that of the first isolation layer, and in the process of removing the sacrificial layer, the etching selection ratio of the sacrificial layer to the first isolation layer is large, so that the loss of the first isolation layer can be reduced, and the performance of the formed semiconductor structure is improved.
Furthermore, the first initial gate oxide layer on the surface of the side wall of the fin part column channel region is covered by the protective side wall, the thickness of the protective side wall is smaller, and in the subsequent etching process of the first initial gate oxide layer, the protective side wall can also generate loss, so that the distance between the top of the formed first gate oxide layer and the top of the protective side wall can be reduced, the removal amount of the first initial gate oxide layer covered by the protective side wall is larger, and the uniformity of the thickness of the first gate oxide layer can be increased.
Further, before the second conductive structure is formed, a first high-doping region is formed in the first source-drain doping layer at the bottom of the first contact hole, and due to the fact that the concentration of doping ions in the first high-doping region is high, ohmic contact is easily formed between the first high-doping region and the first interconnection structure, so that contact resistance between the first interconnection structure and the first source-drain doping layer can be reduced, and performance of the formed semiconductor structure is improved.
Furthermore, the grid electrode structures on the side walls of the adjacent fin portion columns are separated, so that different grid electrode structures can have different electric potentials, and different functions are achieved.
Furthermore, before the dielectric layer is formed, a pseudo gate structure is formed, and the subsequent gate structures can be separated through etching of the pseudo gate structure, so that the etching of the gate structure can be reduced. The material of the pseudo gate structure can be a semiconductor material, so that the etching process of the semiconductor material is simple, and the process can be simplified.
In the semiconductor structure provided by the technical scheme of the invention, the surface of the side wall of the channel region of the fin part column is provided with the first gate oxide layer and the second gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different, so that the threshold voltage of the semiconductor structure is not lower, and the first gate oxide layer and the second gate oxide layer of the semiconductor structure are not easy to be punctured.
Drawings
FIGS. 1 and 2 are schematic structural diagrams of steps of a method of forming a vertical nanowire transistor;
FIGS. 3-24 are schematic structural views of steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 25 to 30 are schematic structural views of steps of another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The prior art semiconductor structures have a number of problems, such as: the performance of the semiconductor structure is poor.
The reason for the poor performance of a semiconductor structure is now analyzed in connection with the semiconductor structure:
the conventional planar transistor occupies a large substrate surface, so that the integration degree of the semiconductor structure is low. In order to improve the integration of the formed semiconductor structure, a vertical nanowire transistor is proposed.
Fig. 1 and 2 are schematic structural diagrams of steps of a method of forming a vertical nanowire transistor.
Referring to fig. 1, a substrate 130 is provided, the surface of the substrate 130 has a fin pillar 131, and the fin pillar 131 includes a bottom region I, a channel region II on the bottom region I, and a top region III on the channel region II.
Continuing to refer to fig. 1, performing oxidation treatment on the sidewall of the fin pillar 131, and forming a gate oxide layer 110 on the surface of the sidewall of the fin pillar 131; after the gate oxide layer 110 is formed, forming a first metal silicide 141 connected with the bottom region I of the fin portion column 131; a second metal silicide 142 is formed on the top surface of the fin pillar 131.
Referring to fig. 2, a first isolation layer 150 is formed on the substrate 130, wherein the first isolation layer 150 covers sidewalls of the bottom region I of the fin pillar 131 and the surface of the first metallization 141; forming a gate structure 151 on top of the first isolation layer 150, wherein the gate structure 151 is located on the surface of the sidewall of the channel region II; a second isolation layer 152 is formed on top of the gate structure 151, and the second isolation layer 152 covers the sidewall of the top region III and exposes the second metal silicide 142.
Subsequently forming a first plug connecting the first metal silicide 141; a second plug is formed connecting the second metal silicide 142.
Wherein the gate oxide layer 110 is formed through an oxidation process. The gate oxide layer 110 of the channel region II of the fin column 231 is formed by the same oxidation process, so that the gate oxide layer 110 on the surface of the channel region II of the fin column 231 has the same thickness. The drain region is at a higher potential due to the difference in potential applied to the source and drain regions of the transistor. If the thickness of the gate oxide layer 110 is smaller, when the voltage received by the drain region is higher, the gate oxide layer 110 adjacent to the drain region is easily broken down due to the stronger electric field of the drain region; if the thickness of the gate oxide layer 110 is too large, the threshold voltage is easily increased, and the power consumption is increased.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a fin part column, and the fin part column comprises a bottom region, a channel region positioned on the bottom region and a top region positioned on the channel region; and forming a first gate oxide layer and a second gate oxide layer on the surface of the side wall of the fin part column channel region, wherein the second gate oxide layer is positioned on the top surface of the first gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different. Because the thickness of first gate oxide is inequality with the thickness of second gate oxide, through adjusting the thickness of first gate oxide and second gate oxide can make the threshold voltage of semiconductor structure is lower, and first gate oxide and second gate oxide are difficult to be punctured.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 24 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, the substrate 200 having a fin pillar 201 thereon, the fin pillar 201 comprising: a bottom region a, a channel region B located on the bottom region a, and a top region C located on the channel region B.
In this embodiment, the substrate 200 and the fin pillar 201 are made of silicon, germanium, silicon germanium, or silicon carbide. In other embodiments, the substrate and fin pillar material may also be a single crystal of a III-V material.
The fin pillar 201 is shaped as a cylinder. Specifically, in this embodiment, the fin pillar 201 is a cylinder. In other embodiments, the fin pillar may be a square pillar.
In this embodiment, the surface of the substrate 200 has a (100) crystal orientation.
The steps of forming the substrate 200 and the fin pillars 201 include: providing an initial substrate; forming a first patterned mask layer on the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form a substrate 200 and a fin column 201 positioned on the substrate 200.
Before forming the first mask layer, the method further includes: an adhesion layer is formed on the initial substrate.
The adhesion layer is used for improving the adhesion of the contact surface between the first mask layer and the initial substrate.
In this embodiment, the starting substrate is a single crystal of silicon, germanium, silicon germanium or a group III-V material. The first mask layer is made of silicon nitride or silicon oxynitride. The material of the adhesion layer is silicon oxide.
The process of etching the initial substrate comprises a dry etching process. The dry etching process has a good line width control effect, the size of the fin portion pillar 201 is easy to control, and the formed fin portion pillar 201 has good verticality with the surface of the substrate 200. In other embodiments, the process of etching the initial substrate comprises wet etching.
In this embodiment, the bottom region a of the fin pillar 201 is used to form a drain region or a source region of an MOS transistor; the channel region B is used for forming a channel of a MOS transistor; the top region C is used for forming a source region or a drain region of the MOS transistor.
In other embodiments, the formed semiconductor structure is a tunneling field effect transistor. The bottom area is used for forming a source area or a drain area of the tunneling field effect transistor; the channel region is used for forming a channel of the tunneling field effect transistor. The top area is used for forming a source region or a drain region of the tunneling field effect transistor.
In this embodiment, the number of the fin pillars 201 is plural. In other embodiments, the number of the fin pillars may be one.
If the height of the fin column 201 is too small, the dimension of the subsequently formed first doped region, second doped region or gate structure along the height direction of the fin column 201 is easily too small, thereby affecting the performance of the formed semiconductor structure; if the height of the fin pillar 201 is too large, the process difficulty is increased. Specifically, in the present embodiment, the height of the fin pillar 201 is 90nm to 110nm, for example, 100 nm.
If the height of the fin portion pillar 201 is too small, the process difficulty is easily increased; if the diameter of the fin pillar 201 is too large, the integration of the formed semiconductor structure is easily reduced. Specifically, in this embodiment, the diameter of the fin pillar 201 is 7nm to 9 nm.
In other embodiments, the forming method further comprises: and reducing the diameter of the fin part column. The diameter reducing step comprises the following steps: performing reducing oxidation treatment on the side wall of the fin part column, and forming a reduced oxide layer on the surface of the side wall of the fin part column; and removing the shrinking oxide layer. And repeating the diameter reducing treatment step to reduce the diameter of the fin part column. The fin pillar may have a diameter of 4.8nm to 5.2nm, for example 5 nm. Alternatively, the fin column may be formed by an induction growth method, for example, gold nanoparticles are formed on the surface of the substrate, the gold nanoparticles are used as a catalyst to induce nucleation of the fin column material, and the fin column is formed by growing from the nucleation point along the axial direction.
And forming a first source-drain doping layer 211 on the surface of the substrate 200, wherein the first source-drain doping layer 211 covers the bottom region a of the fin column 201.
In this embodiment, the first source-drain doping layer 211 is used as a drain region of the formed semiconductor structure. The first source-drain doped layer 211 is used for receiving a first potential. Specifically, the steps of forming the first source-drain doping layer 211 are shown in fig. 4 and 5.
Referring to fig. 4, an initial source-drain doping layer 210 is formed on the top and sidewall surfaces of the fin pillar 201 and the surface of the substrate 200.
The material of the initial source-drain doping layer 210 is silicon, germanium or silicon-germanium.
The step of forming the initial source drain doping layer 210 includes: epitaxial layers are formed on the top and the side wall surfaces of the fin portion column 201 and the surface of the substrate 200 through epitaxial growth, the epitaxial layers are doped, and first doping ions are doped into the epitaxial layers to form an initial source drain doping layer 210.
In this embodiment, the process of doping the epitaxial layer includes an in-situ doping process. In other embodiments, the process of doping the epitaxial layer comprises an ion implantation process.
It should be noted that, since the growth rate of the epitaxial layer along the <100> crystal orientation of the substrate 200 is the fastest during the epitaxial growth process, the growth rate along other crystal orientations is less than the <100> crystal orientation. Since the surface of the substrate 200 is a (100) crystal plane. The sidewall surface of the fin column 201 includes a plurality of crystal plane directions, so that the growth rate of the epitaxial layer on the sidewall of the fin column 201 is low in the epitaxial growth process, and the growth rate of the epitaxial layer on the surface of the substrate 200 is high.
In the process of etching the initial substrate to form the substrate 200 and the fin portion pillar 201, a corner where the top of the fin portion pillar 201 is in contact with the side wall is easily etched, and the diameter of the fin portion pillar 201 is small, so that the top of the fin portion pillar 201 is not parallel to the surface of the substrate 200, and the crystal plane directions of the top surface of the fin portion pillar 201 are diversified. In the process of forming the epitaxial layer, the growth rate of the epitaxial layer of the fin pillar 201 is less than that of the epitaxial layer on the surface of the substrate 200.
In summary, the thickness of the epitaxial layer on the sidewall and the top surface of the fin pillar 201 is smaller than the thickness of the epitaxial layer on the surface of the substrate 200.
When the semiconductor structure is a PMOS transistor, the first dopant ions are P-type ions, such as boron ions or HB2 +Ions; when the formed semiconductor structure is an NMOS transistor, the first doping ions are N-type ions, such as phosphorous ions or arsenic ions.
Referring to fig. 5, the initial source-drain doping layer 210 is etched, and the initial source-drain doping layer 210 on the sidewall of the fin pillar 201 is removed to form a first source-drain doping layer 211.
In this embodiment, the first source-drain doping layer 211 is used as a drain region of the formed semiconductor structure. The first source-drain doped layer 211 is used for receiving a first potential.
In this embodiment, the process of removing the initial source-drain doping layer 210 on the sidewall of the fin pillar 201 includes a combination of a dry etching process and a wet etching process.
Because the thickness of the initial source-drain doping layer 210 on the top and the sidewall of the fin pillar 201 is small, in the process of etching the initial source-drain doping layer 210, the initial source-drain doping layer 210 on the top and the sidewall of the fin pillar 201 is easily and completely removed, and a part of the initial source-drain doping layer 210 on the surface of the substrate 200 is easily retained to form the first source-drain doping layer 211.
In this embodiment, in the process of removing the initial source-drain doping layer 210 on the sidewall of the fin pillar 201, the initial source-drain doping layer 210 on the top surface of the fin pillar 201 is also removed. In other embodiments, the initial source drain doped layer on the top surface of the fin pillar may not be removed.
Under the condition that the height of the fin portion column 201 is fixed, if the thickness of the first source-drain doping layer 211 on the surface of the substrate 200 is too large, the process difficulty is easily increased; if the thickness of the first source-drain doping layer 211 on the surface of the substrate 200 is too small, the resistance of the first source-drain doping layer 211 is easily increased, thereby affecting the performance of the semiconductor structure. Specifically, in this embodiment, the thickness of the first source-drain doping layer 211 on the surface of the substrate 200 is 60 angstroms to 100 angstroms.
Referring to fig. 6, a first isolation layer 220 is formed on the substrate 200, and the first isolation layer 220 covers the bottom region a of the fin pillar 201.
In this embodiment, the first isolation layer 220 covers the top surface of the first source-drain doping layer 211.
The first isolation layer 220 is used for realizing electrical isolation between the first source-drain doping layer 211 and a subsequently formed gate structure.
The first isolation layer 220 is made of silicon oxide. In other embodiments, the material of the first isolation layer 220 may also be silicon oxynitride or a low-k (k less than 3.9) dielectric material.
The step of forming the first isolation layer 220 includes: forming a first initial isolation layer on the substrate 200, wherein the surface of the first initial isolation layer is higher than or flush with the top surface of the fin pillar 201; and etching the first initial isolation layer to form a first isolation layer 220, wherein the surface of the first isolation layer 220 is lower than or flush with the top surface of the bottom area A.
The process of forming the first initial isolation layer comprises a fluid chemical vapor deposition process. Particularly good gap filling capability of fluid chemical vapor deposition processes.
And the process for etching the first initial isolation layer comprises one or two of dry etching and wet etching.
If the thickness of the first isolation layer 220 is too small, it is not favorable for electrical isolation between the first source-drain doping layer 211 and the subsequently formed gate structure; if the thickness of the first isolation layer 220 is too large, the size of the gate structure or the first source-drain doping layer 211 is easily reduced under the condition that the height of the fin pillar 201 is fixed, and the performance of the formed semiconductor structure is affected. Specifically, the thickness of the first isolation layer 220 is 180 to 220 angstroms.
A first gate oxide layer 231 and a second gate oxide layer 232 are formed on the surface of the side wall of the channel region B of the fin portion pillar 201 subsequently, the second gate oxide layer 232 is located on the top surface of the first gate oxide layer 231, and the thicknesses of the first gate oxide layer 231 and the second gate oxide layer 232 are different.
In this embodiment, the steps of forming the first gate oxide layer 231 and the second gate oxide layer 232 are as shown in fig. 7 to 14.
In this embodiment, after the first gate oxide layer 231 is formed, the second gate oxide layer 232 is formed.
In this embodiment, the steps of forming the first gate oxide layer 231 are as shown in fig. 7 to 14.
Referring to fig. 7, a first oxidation process is performed on the channel region B and the top region C of the fin pillar 201, and a first initial gate oxide layer 230 is formed on the surfaces of the channel region B and the top region C of the fin pillar 201.
The first initial gate oxide layer 230 is used for the subsequent formation of a first gate oxide layer.
In this embodiment, the fin pillar 201 is made of silicon, and correspondingly, the first initial gate oxide layer 230 is made of silicon oxide.
In other embodiments, if the material of the fin pillar is germanium, the material of the first initial oxide layer is germanium oxide; the fin column is made of silicon germanium, and the first initial oxide layer is made of silicon germanium oxide.
If the thickness of the first initial gate oxide layer 230 is too small, when the potential applied to the first source-drain doping layer 211 is high, the electric field intensity of the first initial gate oxide layer 230 is high, so that the first gate oxide layer 231 is easily broken down; if the thickness of the first initial gate oxide layer 230 is too large, it is easy to increase the threshold voltage of the formed semiconductor structure. Specifically, the thickness of the first initial gate oxide layer 230 is 35 to 45 angstroms.
In this embodiment, the first oxidation process includes an in-situ steam generation process. In other embodiments, the first oxidation process comprises a thermal oxidation process.
The reaction gas of the first oxidation treatment includes water vapor.
If the reaction temperature of the first oxidation treatment is too high, the reaction rate is easily caused to be too fast, so that the thickness of the first initial gate oxide layer 230 is not controlled favorably; if the reaction temperature of the first oxidation treatment is too low, the production efficiency is liable to be lowered. Specifically, the reaction temperature of the first oxidation treatment is 850 to 1050 ℃, for example, 950 ℃.
And subsequently removing the first initial gate oxide layer 230 of the top region C and part of the channel region B contacted with the top region C to form a first gate oxide layer 231, wherein the top surface of the first gate oxide layer 231 is lower than the top surface of the channel region B.
In this embodiment, the step of removing the first initial gate oxide layer 230 of the top region C and the part of the channel region B in contact with the top region C is as shown in fig. 8 to 14.
And subsequently forming a sacrificial layer 241 on the top surface of the first isolation layer 220, wherein the sacrificial layer 241 covers a part of the first initial gate oxide layer 230 of the channel region B, the top surface of the sacrificial layer 241 is lower than that of the channel region B, and the material of the sacrificial layer 241 is different from that of the first isolation layer 220.
In this embodiment, the step of forming the sacrificial layer 241 is as shown in fig. 8 and 9.
Referring to fig. 8, an initial sacrificial layer 240 is formed on the top surface of the first isolation layer 220, the material of the initial sacrificial layer 240 is different from that of the first isolation layer 220, and the initial sacrificial layer 240 covers the channel region B and the top region C of the fin pillar 201, and the first initial gate oxide layer 230.
The initial sacrificial layer 240 is located on the top surface of the first isolation layer 220. The initial sacrificial layer 240 completely covers the top surface of the first isolation layer 220.
In this embodiment, the material of the initial sacrificial layer 240 is polysilicon. In other embodiments, the material of the initial sacrificial layer may be amorphous silicon, amorphous carbon, or an organic dielectric material.
In this embodiment, the process of forming the initial sacrificial layer 240 includes a chemical vapor deposition process. In other embodiments, when the material of the initial sacrificial layer is an organic dielectric material, the process of forming the initial sacrificial layer includes a spin-on process.
Referring to fig. 9, the initial sacrificial layer 240 of the top region C and a portion of the channel region B is removed to form a sacrificial layer 241, wherein a top surface of the sacrificial layer 241 is lower than a top surface of the channel region B.
The sacrificial layer 241 completely covers the top surface of the first isolation layer 220, and in the subsequent etching process of the first gate oxide layer 231, the first isolation layer 220 and a part of the channel region B of the first gate oxide layer 231 can be protected, and the loss of the first isolation layer 220 is reduced. The material of the sacrificial layer 241 is different from the material of the first isolation layer 220, so that the etching selectivity of the sacrificial layer 241 and the first isolation layer 220 is relatively high in the process of removing the sacrificial layer 241, thereby reducing the loss of the first isolation layer 220 and improving the performance of the formed semiconductor structure.
If the thickness of the sacrificial layer 241 is too large, the dimension of the first gate oxide layer 231 formed subsequently along the direction vertical to the surface of the substrate 200 is easily too large, the threshold voltage of the formed semiconductor structure is too high, and the energy consumption is increased; if the thickness of the sacrificial layer 241 is too small, it is not favorable for protecting the first isolation layer 220. Specifically, the thickness of the sacrificial layer 241 is 270 to 330 angstroms, for example, 300 angstroms.
In this embodiment, the process of removing the initial sacrificial layer 240 of the top region C and the partial channel region B includes dry etching. In other embodiments, the process of removing the initial sacrificial layer of the top region and the portion of the channel region includes wet etching.
Specifically, in this embodiment, the process parameters for removing the initial sacrificial layer 240 in the top region C and the partial channel region B include: sulfur hexafluoride (SF)6) And tetrachlorosilane (SiCl)4) And trichloromethane (CHCl)3) One or more combinations thereof.
In this embodiment, the forming method further includes: and forming a protective side wall 251 on the surface of the side wall of the channel region B.
In this embodiment, the protective sidewall 251 covers a portion of the sidewall of the channel region B, and the protective sidewall 251 is located on the top surface of the sacrificial layer 241.
In other embodiments, the protective sidewall may not be formed.
In this embodiment, the steps of forming the protective sidewall 251 are shown in fig. 10 and fig. 11.
Referring to fig. 10, a protective sidewall layer 250 is formed to cover the sidewalls and top of the first initial gate oxide layer 230 and the top surface of the sacrificial layer 241.
The protective sidewall layer 250 is used for forming a protective sidewall subsequently.
In this embodiment, the material of the protective sidewall layer 250 is different from that of the first initial gate oxide layer 230. In the subsequent process of removing the protective side wall layer 250, the loss of the subsequent first gate oxide layer can be reduced, and the thickness uniformity of the subsequently formed first gate oxide layer is ensured.
In this embodiment, the material of the protective sidewall layer 250 is silicon nitride. In other embodiments, the material of the protective sidewall layer is silicon oxynitride.
If the thickness of the protective side wall layer 250 is too large, the process difficulty of subsequent removal of the protective side wall is easily increased; if the thickness of the protective sidewall layer 250 is too small, it is not favorable for the subsequently formed protective sidewall to protect the first initial gate oxide sidewall 230. Specifically, in this embodiment, the thickness of the protective sidewall layer 250 is 70 to 90 angstroms, for example, 80 angstroms.
The process of forming the protective sidewall layer 250 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 11, the protective sidewall layer 250 (shown in fig. 10) covering the sidewalls and the top of the top region C of the fin pillar 201 and the top surface of the sacrificial layer 241 is removed to form a protective sidewall 251.
The protective sidewall 251 is used for protecting partial side walls of the first initial gate oxide layer 230, so that the loss of the side walls of the protective sidewall layer 250 can be reduced, and the thickness of the subsequently formed first gate oxide layer can be uniform. Because the thickness of the protective side wall 251 is smaller, in the subsequent etching process of the first initial gate oxide layer 230, the protective side wall 251 also generates loss, so that the distance between the top of the first gate oxide layer 231 and the top of the protective side wall 251 can be reduced, the removal amount of the first initial gate oxide layer 230 covered by the protective side wall 251 is larger, and the thickness uniformity of the first gate oxide layer 231 can be further increased.
In this embodiment, the process of removing the protective sidewall layer 250 covering the sidewalls and the top of the top region C of the fin pillar 201 and the top surface of the sacrificial layer 241 includes: and (3) an anisotropic dry etching process. The anisotropic dry etching process has a longitudinal etching rate greater than a transverse etching rate, so that the loss of the side wall of the protective sidewall layer 250 can be reduced, and the protective sidewall 251 is formed.
Specifically, the etching gas for removing the protective sidewall layer 250 covering the sidewall and the top of the top region C of the fin pillar 201 and the top surface of the sacrificial layer 241 includes CF4。
If the height of the protective sidewall 251 is too large, the height of the formed first gate oxide layer 231 is easily made to be too large, so that the threshold voltage of the formed semiconductor structure is easily increased; if the height of the protective side wall 251 is too small, the thickness uniformity of the first gate oxide layer 231 is not favorably increased, and the height of the first gate oxide layer 231 formed subsequently is easily too small, so that the second gate oxide layer 232 formed subsequently is close to the first source drain doping layer 211, and the second gate oxide layer 232 is easily broken down when the potential on the first source drain doping layer 211 is high. Specifically, in this embodiment, the height of the protective sidewall 251 is 9nm to 11 nm.
In other embodiments, the sacrificial layer may be formed without forming the protective sidewall; or forming the protective side wall without forming the sacrificial layer; the protective side wall is located on the top surface of the first isolation layer.
Referring to fig. 12, the first initial gate oxide layer 230 is etched by using the sacrificial layer 241 and the protective sidewall 251 as masks, so as to form a first gate oxide layer 231.
In this embodiment, the protective sidewall 251 is further used as a mask in the process of etching the first initial gate oxide layer 230. In other embodiments, the forming method does not include the step of forming the protective side wall, and the sacrificial layer is used as a mask in the process of etching the first initial gate oxide layer; or, when the forming method does not include the step of forming the sacrificial layer, the protective side wall is used as a mask in the process of etching the first initial gate oxide layer.
In this embodiment, the process of etching the first initial gate oxide layer 230 includes a dry etching process. The dry etching process has good line width control and can effectively control the height of the first gate oxide layer.
In other embodiments, the process of etching the first initial gate oxide layer comprises a wet etching process.
In this embodiment, the etching gas for etching the first initial gate oxide layer 230 includes: carbon tetrafluoride (CF)4) Octafluoropropane (C)3F8) And trifluoromethane (CHF)3) One or more combinations thereof.
The dimension of the first gate oxide layer 231 in a direction perpendicular to the surface of the substrate 200 is the height of the first gate oxide layer 231.
If the height of the first gate oxide layer 231 is too large, the threshold voltage of the formed semiconductor structure is easily increased; if the height of the first gate oxide layer 231 is too small, the second gate oxide layer formed later is easily too close to the first source-drain doped layer 211, and when the potential of the first source-drain doped layer 211 is higher, the second gate oxide layer 232 is easily broken down. Specifically, in this embodiment, the height of the first gate oxide layer 231 is 400 to 500 angstroms, for example, 450 angstroms.
Referring to fig. 13, after the first gate oxide layer 231 is formed, the protective sidewall spacers 251 are removed (as shown in fig. 12).
In this embodiment, the process of removing the protective sidewall 251 includes a wet etching process. In other embodiments, the process for removing the protective sidewall spacer may further include an isotropic dry etching process.
Specifically, in this embodiment, the etching solution for removing the protective sidewall 251 includes phosphoric acid.
In this embodiment, the removing the process parameters of the protective sidewall 251 includes: the reaction temperature is 720 ℃ to 880 ℃, for example 800 ℃.
Referring to fig. 14, after the first gate oxide layer 231 is formed, the sacrificial layer 241 is removed (as shown in fig. 13).
In this embodiment, after removing the protective sidewall 251 (as shown in fig. 13), the sacrificial layer 241 is removed.
In this embodiment, the process of removing the sacrificial layer 241 includes a wet etching process. The selectivity of the wet etching is good, and the loss of the fin portion pillar 201 can be reduced. In other embodiments, the process of removing the sacrificial layer comprises a dry etch process.
Specifically, in this embodiment, the etching solution for removing the sacrificial layer 241 includes a mixed solution of hydrofluoric acid and nitric acid.
In the process of etching the first initial gate oxide layer 230 (as shown in fig. 11), the surface of the sacrificial layer 241 is easily damaged, so that the sacrificial layer 241 is amorphized, and thus, in the process of removing the subsequent dummy gate structure, the material of the sacrificial layer 241 remains in the gate opening, thereby affecting the performance of the formed semiconductor structure.
In other embodiments, the sacrificial layer is not removed, and is used for forming a dummy gate structure subsequently.
Referring to fig. 15, a second gate oxide layer 232 is formed on the surface of the exposed sidewall of the channel region B of the first gate oxide layer 231.
In this embodiment, the method for forming the second gate oxide layer 232 includes: and performing second oxidation treatment on the fin portion pillar 201, and forming a second gate oxide layer 232 on the surface of the fin portion pillar 201 exposed by the first gate oxide layer 231.
In this embodiment, the second gate oxide layer 232 is located on the sidewall of the channel region B of the fin pillar 201 exposed by the first gate oxide layer 231, and on the sidewall and the top surface of the top region C of the fin pillar 201.
The second oxidation process is used to form a second gate oxide layer 232.
In this embodiment, the second oxidation process uses the first isolation layer 220 as a mask. The second gate oxide layer 232 is also located on the top and sidewall surfaces of the top region C of the fin pillar 201. In the second oxidation process, the first isolation layer 220 may protect the first source-drain doping layer 211, and prevent the first source-drain doping layer 211 from being oxidized.
In this embodiment, the second oxidation process includes an in-situ water vapor generation process. In other embodiments, the second oxidation process comprises a thermal oxidation process.
In this embodiment, the reaction gas of the second oxidation treatment includes water vapor.
In this embodiment, the process parameters of the second oxidation treatment include: the reaction temperature is 850 ℃ to 1050 ℃, for example 950 ℃.
The thickness of the second gate oxide layer 232 is the dimension of the second gate oxide layer 232 in the direction perpendicular to the sidewall of the fin pillar 201.
If the thickness of the second gate oxide layer 232 is too large, the threshold voltage of the formed semiconductor structure is easily increased; if the thickness of the second gate oxide layer 232 is too small, it is easily broken down. Specifically, the thickness of the second gate oxide layer 232 is 12 to 14 angstroms, for example, 15 angstroms.
The height of the second gate oxide layer 232 is the dimension of the second gate oxide layer 232 along the height direction of the fin portion pillar 201.
The height of the second gate oxide layer 232 is equal to the height of the channel region B minus the height of the first gate oxide layer 231. Specifically, in this embodiment, the height of the second gate oxide layer 232 is equal to 130 angstroms to 160 angstroms.
In this embodiment, after removing the protective sidewall 251 and the sacrificial layer 241, the second oxidation process is performed. In other embodiments, the second oxidation process may be performed after the first gate oxide layer is formed before the protective sidewall and the sacrificial layer are removed.
In this embodiment, the thickness of the first gate oxide layer 231 is greater than that of the second gate oxide layer 232.
In other embodiments, the first source-drain doped layer is used for connecting a first potential, and the top region of the fin column is used for connecting a second potential; the second electric potential is larger than the first electric potential, and the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer.
The step of forming the first gate oxide layer and the second gate oxide layer comprises the following steps: performing third oxidation treatment on the fin part column channel region and the top region, and forming first gate oxide layers on the surfaces of the side walls of the fin part column channel region and the top region; forming a pattern layer covering the first gate oxide layer, wherein the top surface of the pattern layer is lower than that of the channel region; and carrying out fourth oxidation treatment on the fin part column by taking the pattern layer as a mask, and increasing the thickness of the first gate oxide layer exposed by the pattern layer to form a second gate oxide layer.
A gate structure is formed on the top surface of the first isolation layer 220, and the gate structure covers the channel region B, namely a first gate oxide layer 231 and a second gate oxide layer 232; a dielectric layer is formed on the first isolation layer 220, and the dielectric layer covers the sidewalls of the gate structure.
In this embodiment, the steps of forming the gate structure and the dielectric layer are as shown in fig. 16 to 21.
And forming a dummy gate structure covering the first gate oxide layer 231, the second gate oxide layer 232 and the top region C of the fin portion pillar 201.
In this embodiment, if adjacent dummy gate structures are separated from each other, the steps of forming the dummy gate structures are as shown in fig. 16 and 17.
Referring to fig. 16, a dummy gate layer 242 is formed on the first isolation layer 220, wherein the dummy gate layer 242 covers the sidewalls of the first gate oxide layer 231 and the top and sidewall surfaces of the second gate oxide layer 232.
The dummy gate layer 242 is used for forming a dummy gate structure, thereby occupying space for the subsequently formed gate structure.
In this embodiment, the top surface of the dummy gate layer 242 is higher than the top surface of the fin pillar 201. The top surface of the dummy gate layer 242 is higher than the top surface of the fin portion pillar 201, so that a subsequently formed dielectric layer can be higher than the top surface of the fin portion pillar 201, and the dielectric layer can serve as a support for a subsequently formed isolation opening. In other embodiments, the dummy gate layer top surface is flush with the fin pillar top surface.
The material of the dummy gate layer 242 is polysilicon. In other embodiments, the material of the dummy gate layer may be poly-germanium or poly-silicon-germanium. The removal process of the semiconductor material through the etching process is simple, and the process difficulty can be reduced by forming the dummy gate structure before forming the gate structure.
The process for forming the dummy gate layer 242 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
After forming the dummy gate layer 242, the method further includes: and planarizing the top surface of the dummy gate layer 242 to increase the flatness of the top surface of the dummy gate structure.
Referring to fig. 17, the dummy gate layer 242 (shown in fig. 16) is etched to remove a portion of the dummy gate layer 242, so as to form dummy gate structures 243, wherein the dummy gate structures 243 covering adjacent fin pillars 201 are separated from each other.
Dummy gate structure 243 is used to occupy space for subsequently formed gate structures.
The step of etching the dummy gate layer 242 includes: forming a patterned second mask layer on the dummy gate layer 242, wherein the second mask layer covers the first gate oxide layer 231, the second gate oxide layer 232 and the dummy gate layer 242 on the top of the fin column 201; etching the dummy gate layer 242 by using the second mask layer as a mask, and removing part of the dummy gate layer 242 to form a dummy gate structure 243; after the dummy gate structure 243 is formed, the second mask layer is removed.
The second mask layer is made of silicon nitride.
Because the material of the dummy gate layer 242 is a semiconductor material, the etching process of the dummy gate layer 242 is simple, and thus the process flow can be simplified.
In this embodiment, the process of etching the dummy gate layer 242 includes a dry etching process. The dry etching process has good line width control, can accurately control the width of the dummy gate structure 243, and can ensure that the verticality of the side wall of the formed dummy gate structure 243 is good.
Specifically, in this embodiment, the etching gas for etching the dummy gate layer 242 includes: SF6、CF4Or CF4And O2Combinations of (a) and (b).
It should be noted that, in this embodiment, the dummy gate layer 242 is etched to form the dummy gate structure 243, so that the dummy gate structures 243 on the sidewalls and the tops of the adjacent fin pillars 201 can be separated from each other, and thus the subsequently formed gate structures are separated from each other, and different gate structures can have different potentials, thereby implementing different functions.
In addition, before the dielectric layer is formed, the dummy gate structure 243 is formed, and subsequent gate structures can be separated from each other by etching the dummy gate structure 243, so that the etching process for the subsequently formed gate structures can be reduced. Since the material of the dummy gate structure 243 may be a semiconductor material, the etching process for the semiconductor material is simple, so that the process can be simplified.
Referring to fig. 18, a dielectric layer 260 is formed on the first isolation layer 220, wherein the dielectric layer 260 covers sidewalls of the dummy gate structure 243 and exposes a top surface of the dummy gate structure 243.
The dielectric layer 260 is used to achieve electrical isolation between subsequently formed adjacent gate structures.
In this embodiment, the dielectric layer 260 is made of silicon oxide.
In other embodiments, the material of the dielectric layer may also be a low-k (k is less than 3.9) dielectric material.
In this embodiment, the step of forming the dielectric layer 260 includes: forming an initial dielectric layer on the first isolation layer 220, wherein the initial dielectric layer covers sidewalls and a top of the dummy gate structure 243; and performing first planarization treatment on the initial dielectric layer until the top surface of the dummy gate structure 243 is exposed, so as to form a dielectric layer 260.
In this embodiment, the process of forming the initial dielectric layer includes a chemical vapor deposition process. The first planarization treatment process for the initial dielectric layer comprises chemical mechanical polishing.
Referring to fig. 19, the dummy gate structure 243 is removed (as shown in fig. 18), and a gate opening 261 is formed in the dielectric layer 260.
The gate opening 261 is used for subsequently accommodating a gate structure 263.
In this embodiment, the process of removing the dummy gate structure 243 includes: and (5) wet etching process. The wet etching process has good selectivity, and has small damage to the first gate oxide layer 231 and the second gate oxide layer 232.
In other embodiments, the process of removing the dummy gate structure includes a dry etching process.
Specifically, in this embodiment, the removing the etching solution of the dummy gate structure 243 includes: a mixed solution of nitric acid and hydrofluoric acid.
Referring to fig. 20, a gate structure layer 262 is formed in the gate opening 261 (shown in fig. 19).
The gate structure layer 262 is used for the subsequent formation of a gate structure.
In this embodiment, the step of forming the gate structure layer 262 includes: forming an initial gate structure layer on the gate opening 261 and the dielectric layer 260; and performing second planarization treatment on the initial gate structure layer until the initial gate structure layer on the dielectric layer 260 is removed, so as to form a gate structure layer 262.
The second planarization process includes a chemical mechanical polishing process. The chemical mechanical grinding process has simple process for removing the metal material, thereby reducing the process difficulty.
The initial gate structure layer includes: an initial high-k dielectric layer on the sidewalls and bottom surface of the gate opening 261 and on the top surface of the dielectric layer 260; a gate layer covering a surface of the initial high-k dielectric layer.
The step of forming the initial gate structure layer comprises: forming an initial high-k dielectric film on the bottom and sidewall surfaces of the gate opening 261 and the top surface of the dielectric layer 260; after forming the initial high-k dielectric layer, an initial gate layer is formed in the gate opening 261 and on the dielectric layer 260.
The gate structure layer includes: a high-k dielectric film located at the bottom and sidewall surface of the gate opening 261; a gate layer overlying the high-k dielectric layer.
Removing the initial gate structure layer on the dielectric layer 260, and forming a gate structure layer, including: removing the initial high-k dielectric film on the gate structure 263 to form a high-k dielectric film; and removing the initial gate layer on the dielectric layer 260 to form a gate layer.
The material of the high-k dielectric film is HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
In this embodiment, the gate layer is made of W. In other embodiments, the material of the gate layer is Al, Cu, Ag, Au, Ni, Ti, WN, or WSi.
Referring to fig. 21, the gate structure layer 262 in the top region C (as shown in fig. 20) is removed to form a gate structure 263.
Because the dummy gate structures 243 on the sidewalls and tops of the adjacent fin pillars 201 are separated from each other, and the dielectric layer 260 is disposed between the adjacent gate openings 261, the gate structures 263 are separated from each other, so that different gate structures 263 can have different potentials, thereby implementing different functions.
In this embodiment, after the gate structure layer 262 in the top region C is removed, an isolation opening is formed in the dielectric layer 260.
In this embodiment, the gate structure includes: a high-k dielectric layer located at the bottom and the sidewall of the gate opening 261 of the channel region B; and the grid electrode covers the high-k dielectric layer.
The method for forming the gate structure comprises the following steps: removing the gate layer of the top region C to form a gate; and removing the high-k dielectric film of the top area C to form a high-k dielectric layer.
Since the thickness of the removed gate structure layer 262 is small, the process of removing the gate structure layer 262 is simple. Specifically, in this embodiment, a portion of the gate structure layer 262 is removed to make the surface of the gate structure 263 lower than the top surface of the fin 201, and the distance between the top surface of the gate structure 232 and the top surface of the fin 201 is 70 angstroms to 90 angstroms, for example, 80 angstroms. Specifically, the thickness of the removed gate structure layer 262 is 430 to 530 angstroms, for example, 480 angstroms.
The process of removing the top region C gate structure layer 262 includes a dry etching process. The etching gas for removing the top region C gate structure layer 262 includes fluorine-based or chlorine-based gas.
In this embodiment, after removing the gate structure 263 in the top region C, the method further includes: the first gate oxide layer 231 on the top and sidewall surfaces of the top region C is removed.
The second gate oxide layer 232 on the top and sidewall surfaces of the top region C is removed to expose the top and sidewall of the top region C, so that a second source/drain doped region can be formed in the top region C in the following step.
The process for removing the second gate oxide layer 232 on the top and sidewall surfaces of the top region C includes one or a combination of a wet etching process and a dry etching process.
Specifically, in this embodiment, the process of removing the second gate oxide layer 232 on the top and the sidewall surface of the top region C includes an isotropic dry etching process. The isotropic dry etching can reduce the corrosion to the grid.
Specifically, in this embodiment, the step of removing the etching gas of the second gate oxide layer 232 on the top and the sidewall surface of the top region C includes: CF (compact flash)4And oxygen, wherein the oxygen concentration is about 20% to 40%. The oxygen can consume fluorine during the reaction process, and the etching selectivity ratio of the second gate oxide layer 232 to the gate structure 263 is improved.
Referring to fig. 22, after the gate structure 263 is formed, a second source/drain doped region 280 is formed in the top region C fin pillar 201, and the second source/drain doped region 280 has second doped ions therein.
In this embodiment, the second source-drain doped region 280 is used for forming a source region of the semiconductor structure, and the second source-drain doped region 280 is used for receiving a second potential. The second potential is less than the first potential.
In this embodiment, the process of forming the second source/drain doped region 280 in the top region C fin pillar 201 includes an ion implantation process.
In other embodiments, the forming method does not include the step of forming the second source drain doped region. The forming method further includes: and forming a second source-drain doping layer in the top region or on the surface of the top region.
The method for forming the second source-drain doping layer comprises the following steps: forming a source drain groove in the top area of the fin column; forming a second source-drain doping layer in the source-drain groove; or, the method for forming the second source-drain doping layer includes: and forming a second source-drain doping layer on the top and the surface of the fin portion column top area. The process for forming the second source-drain doping layer comprises an epitaxial growth process.
When the formed semiconductor structure is an NMOS transistor, the second doping ions are N-type ions, such as phosphorus ions or arsenic ions; when the semiconductor structure is a PMOS transistor, the second dopant ions are P-type ions, such as boron ions or BF2 +Ions.
Referring to fig. 23, a second isolation layer 262 is formed on the top surface of the gate structure 263, and the second isolation layer 262 covers the sidewall of the top region C of the fin pillar 201.
The second isolation layer 262 is used to electrically isolate the gate structure 263 from external circuitry.
In this embodiment, the second isolation layer 262 is made of silicon oxide. In other embodiments, the material of the second isolation layer may also be a low-k dielectric material.
In this embodiment, the process of forming the second isolation layer 262 includes a chemical vapor deposition process.
In this embodiment, the second isolation layer 262 is located in the isolation opening in the dielectric layer 260, and the top surface of the second isolation layer 262 is flush with the top surface of the dielectric layer 260. In other embodiments, the second isolation layer may also be located on the top surface of the dielectric layer.
If the thickness of the second isolation layer 262 is too large, the process difficulty is easily increased; if the thickness of the second isolation layer 262 is too small, it is not conducive to electrically isolating the gate structure 263 from external circuitry. The height difference between the top surface of the second isolation layer 262 and the top surface of the fin 201 is 350 to 450 angstroms, for example 400 angstroms. Specifically, in this embodiment, the thickness of the second isolation layer 262 is 550 to 650 angstroms.
Referring to fig. 24, a first interconnection structure 270 is formed in the dielectric layer 260, and the first interconnection structure 270 is electrically connected to the first source-drain doping layer 211.
The first interconnection structure 270 is used to electrically connect the first source-drain doped layer 211 with an external circuit.
In this embodiment, the method for forming the first interconnect structure 270 includes: forming a first contact hole in the dielectric layer 260, wherein the bottom of the first contact hole exposes the first source-drain doping layer 211; a first interconnect structure 270 is formed in the first contact hole.
In this embodiment, before forming the first interconnect structure 270 in the first contact hole, the method further includes: and performing first supplementary ion implantation on the first source-drain doping layer 211 exposed at the bottom of the first contact hole, and forming a first high-doping region in the first source-drain doping layer 211.
The implanted ions of the first supplementary ion implantation have the same conductivity type as the first doped ions.
The first supplemental ion implantation enables the concentration of doped ions in the first highly doped region to be higher, so that ohmic contact can be formed between the first interconnection structure 270 and the first highly doped region, thereby reducing the contact resistance between the first interconnection structure 270 and the first source-drain doped layer 211, and improving the performance of the formed semiconductor structure.
The first interconnect structure 270 includes: the first metallization layer is positioned on the surface of the first high-doping area exposed from the bottom of the first contact hole; a first plug in the first contact hole, the first metallization layer being between the first plug and the first high-doped layer.
The method of forming the first interconnect structure 270 in the first contact hole includes: forming a first metallization layer on the surface of the first high-doping area exposed at the bottom of the first contact hole; after forming the first metallization layer, a first plug is formed in the first contact hole.
The method of forming the first metallization layer includes: forming metal layers at the bottom and on the surface of the side wall of the first contact hole; carrying out first annealing treatment on the metal layer to enable the metal layer to react with the first high-doping area to form a first metalized layer; and removing the residual metal layer after the first annealing treatment.
The metal layer is made of nickel or cobalt.
The forming method further includes: a second interconnect structure is formed in the second isolation layer 262, and the second interconnect structure is electrically connected to the second source-drain doped region 280.
The method of forming the second interconnect structure includes: forming a second contact hole in the second isolation layer 262, wherein the bottom of the second contact hole exposes the top surface of the second source/drain doped region 280; and forming a second interconnection structure in the second contact hole.
The second interconnect structure includes: the second metallization layer is positioned on the surface of the second source drain doped region 280 exposed at the bottom of the second contact hole; and the second plug is positioned in the second contact hole, and the second metallization layer is positioned between the second plug and the second source-drain doped region 280.
In this embodiment, before forming the second interconnect structure, the method further includes: and performing second supplementary ion implantation on the second source-drain doped region 280 exposed at the bottom of the second contact hole, and forming a second high-doped region in the second source-drain doped region 280 at the bottom of the second contact hole.
The conductivity type of the ions implanted by the second supplemental ion implantation is the same as the conductivity type of the second doped ions in the second source-drain doped region 280.
Fig. 25 to 30 are schematic structural views of steps of a method for forming a semiconductor structure according to still another embodiment of the present invention.
The present embodiment has the same points as the previous embodiment, and is not repeated herein, except that:
referring to fig. 25, a first source/drain doped region 361 is formed in the bottom region of the fin pillar 201.
The method for forming the first source-drain doped region 361 includes: forming a barrier layer 301 covering the top region and the bottom region of the fin pillar 201; and performing ion implantation on the bottom region of the fin column 201 by using the barrier layer 301 as a mask, and forming a first source-drain doped region 361 in the bottom region of the fin column 201.
The step of forming the barrier layer 301 includes: forming a first peeling layer on the substrate 200, wherein the first peeling layer covers sidewalls of a bottom region I of the fin pillar 201; forming initial barrier layers on the surface of the first stripping layer, the side wall of the channel region II of the fin portion column 201, the side wall of the top region III and the surface of the top; and removing the first stripping layer and the initial barrier layer on the surface of the first stripping layer to form a barrier layer 301.
The material of the barrier layer 301 is polysilicon, amorphous silicon, silicon nitride or poly-germanium.
In this embodiment, after the first source-drain doped region 361 is formed, a subsequent second source-drain doped region 362 is formed.
In other embodiments, a second source-drain doped region is formed in the process of forming the first source-drain doped region; the barrier layer also exposes the fin top region sidewalls and top surface.
The method of forming the barrier layer further comprises: and removing the initial barrier layer on the top area of the fin column to form a barrier layer after removing the first stripping layer and the initial barrier layer on the surface of the first stripping layer.
The method for removing the initial barrier layer at the top area of the fin column comprises the following steps: forming a second stripping layer covering the side wall of the bottom region of the fin part column and the initial barrier of the channel region; and etching the initial barrier by using the second stripping layer as a mask, and removing the initial barrier layer in the top area to form a barrier layer.
The method for forming the first source drain doping region and the second source drain doping region comprises the following steps: and performing ion implantation on the fin portion column by taking the barrier layer as a mask, forming a second source-drain doped region in the top region of the fin portion column, and forming a first source-drain doped region in the bottom region of the fin portion column.
Referring to fig. 26, a first conductive structure 311 is formed to connect the bottom region I of the fin pillar 201.
In this embodiment, the first conductive structure 311 is used to electrically connect the bottom region I of the fin pillar 201 to an external circuit.
After the first source-drain doped region 361 is formed, the first conductive structure 311 is formed, and the first conductive structure 311 is in contact with the first source-drain doped region 361.
In this embodiment, the method for forming the first conductive structure 311 includes: forming a protective layer on the surface of the sidewall of the fin pillar 201; and performing metallization processing on the surface of the substrate 200 and the top surface of the fin portion column 201 by using the protection layer as a mask to form a first conductive structure 311.
In this embodiment, the step of forming the protective layer includes: performing fifth oxidation treatment on the side wall of the fin portion pillar 201, and forming an initial protection layer on the side wall and the top surface of the fin portion pillar 201; and carrying out anisotropic etching treatment on the initial protection layer, and removing the initial protection layer on the tops of the fin portion columns 201 and the surface of the substrate 200 to form a protection layer.
The step of the fifth oxidation treatment includes: a thermal oxidation process or an in-situ steam generation process.
In this embodiment, the material of the protection layer is silicon oxide. In other embodiments, the process of forming the protective layer includes a chemical gas deposition process, an atomic layer deposition process, or a physical vapor deposition process. The protective layer is made of silicon nitride, silicon oxide or silicon oxynitride.
The step of metallization processing comprises: forming a metal layer on the surface of the substrate 200, the top and the sidewall surface of the fin portion pillar 201, and the surface of the protection layer; and performing second annealing treatment on the metal layer to enable the metal layer to react with the substrate 200 and the top of the fin portion column 201, forming the first conductive structure 311 on the surface of the substrate 200, and forming the first conductive structure 311 on the surface of the top of the fin portion column 201.
In this embodiment, the metal layer is made of nickel or cobalt. The first conductive structure 311 is made of nickel-silicon, nickel-germanium, nickel-cobalt or silicon-cobalt.
In other embodiments, the fin top does not have a first conductive structure. The step of forming the first conductive structure comprises: forming a first initial conductive structure on the substrate, wherein the first initial conductive structure covers the top region, the channel region and the side wall of the top region of the fin column; and etching the first initial conductive structure, removing the first initial conductive structure of the top region and the channel region, and forming a first conductive structure covering the side wall of the bottom region.
The first initial conductive structure includes: a third metallization layer on the sidewalls and top surface of the fin pillar 201 and on the surface of the substrate; a first conductive layer on the surface of the third metallization layer, the surface of the first conductive layer being higher than the top surface of the fin pillar 201.
The method of removing the first initial conductive structure of the top region and the channel region comprises: removing the first conductive layer of the top region and the channel region; and removing the first metallization layer of the top region and the channel region.
In this embodiment, the forming method further includes: a first isolation layer 312 is formed on top of the first conductive structure 311 on the surface of the substrate 200.
The forming step of the first isolation layer 312 is the same as that of the previous embodiment, and is not repeated herein.
Referring to fig. 27, after the first isolation layer 312 is formed, a first gate oxide layer 321 and a second gate oxide layer 322 are formed on the sidewall surface of the channel region II of the fin pillar 201, and the thicknesses of the first gate oxide layer 321 and the second gate oxide layer 322 are different.
The forming steps of the first gate oxide 321 and the second gate oxide 322 are the same as those of the previous embodiment, and are not described herein again, except that: before the gate structure 330 is formed, the fin pillar 201 does not have the first gate oxide 321 on top.
Referring to fig. 28, a gate structure 330 is formed to cover the channel region II, the first gate oxide 321 and the second gate oxide 322.
In this embodiment, the gate structure 330 includes: a gate dielectric layer covering the channel region II, the first gate oxide 321 and the second gate oxide 322; and the grid electrode covers the grid dielectric layer.
The gate structure 330 is located on the top surface of the first isolation layer 312.
The step of forming the gate structure 330 includes: forming an initial high-k dielectric layer of a first gate oxide 321 and a second gate oxide 322 covering the channel region II and the top region III; forming a gate layer covering the initial high-k dielectric layer, wherein the top surface of the gate layer is higher than the top surface of the fin portion pillar 201; and performing back etching on the gate layer and the initial high-k dielectric layer, removing the initial high-k dielectric layer of the top area III to form a high-k dielectric layer, and removing the gate layer of the top area III to form a gate.
The high-k dielectric layer is made of a high-k dielectric material; the grid electrode is made of metal.
In the present embodiment, the process steps for forming the gate structure 330 are few, and the process can be simplified.
In addition, in this embodiment, the gate structures 330 on the sidewall surfaces of the adjacent fin pillars 201 are in contact with each other to form an integral structure, so that the gates on the surfaces of the adjacent fin pillars 201 have the same potential.
In other embodiments, after forming the gate structure, the method further includes: forming a first graphical layer covering the grid electrode structure, the side wall of the top area of the fin portion column and the top of the fin portion column; etching the grid electrode structure by taking the first pattern layer as a mask to separate the grid electrode structures on the side wall surfaces of the adjacent fin portion columns; or, further comprising: forming a second patterned layer on the top surfaces of the gate layer and the initial high-k dielectric layer; etching the gate layer and the initial high-k dielectric layer by taking the second pattern layer as a mask to form initial gate structures, wherein the initial gate structures on the side wall surfaces of the adjacent fin columns are mutually separated; and etching the initial gate structure, and removing the initial gate structure in the top area to form a gate structure.
Referring to fig. 29, after the gate structure 330 is formed, the second gate oxide layer 322 in the top region III is removed; a second isolation layer 340 is formed on the top surface of the gate structure 330.
In this embodiment, the top surface of the second isolation layer 340 is lower than the top surface of the fin pillar 201; after forming the second isolation layer 340, the exposed top region III of the second gate oxide layer 322 of the second isolation layer 340 is removed.
After forming the second isolation layer 340, the exposed top region III of the second gate oxide layer 322 of the second isolation layer 340 is removed. During the process of removing the top III second gate oxide 322 exposed by the second isolation layer 340, the second isolation layer 340 can protect the gate structure 330, reducing the loss of the gate structure 330.
In other embodiments, before forming the second isolation layer, the second gate oxide layer exposed by the gate structure is removed; the second isolation layer top surface is lower than, flush with, or higher than the fin pillar top surface.
In this embodiment, the method for removing the top-region III second gate oxide layer 322 is the same as that in the previous embodiment.
With continued reference to fig. 29, a second source-drain doped region 362 is formed in the top region III of the fin pillar 201.
In this embodiment, after the second isolation layer 340 is formed, the second source-drain doped region 362 is formed.
After the second isolation layer 340 is formed, the second source-drain doped region 362 is formed, so that damage to the gate structure 330 in the process of forming the second source-drain doped region 362 can be reduced.
In this embodiment, the method for forming the second source-drain doped region 362 includes: and performing ion implantation on the top region III of the fin pillar 201 by using the second isolation structure 340 as a mask to form a second source-drain doped region 362.
In other embodiments, the second source-drain doped region may be formed before the second isolation layer is formed and after the gate structure is formed.
In other embodiments, the forming method does not include the step of forming a second source drain doped region in the fin column top region. The top surface of the second isolation layer is higher than or flush with the top area of the fin column; the forming method further includes: removing the top area of the fin portion column, and forming a source drain groove in the second isolation layer; forming a second source-drain doping layer in the source-drain groove; alternatively, the forming method comprises: and forming a second source-drain doping layer on the top of the fin column top region and the surface of the side wall. The process for forming the second source-drain doping layer comprises an epitaxial growth process.
The material of the second isolation layer 340 is silicon oxide or a low-k dielectric material.
Referring to fig. 30, after the first source/drain doped region 361 is formed, a second conductive structure 350 electrically connected to the top region III of the fin pillar 201 is formed.
In this embodiment, the second conductive structure 350 is in contact with the first conductive structure 311 on the top surface of the fin pillar 201.
The step of forming the second conductive structure 350 includes: forming a third isolation layer 341 on the second isolation layer 340 to cover the top and sidewalls of the fin pillar 201; forming a second contact hole in the third isolation layer 341, wherein the bottom of the second contact hole exposes the first conductive structure 311 at the top of the fin pillar 201; a second conductive structure 350 is formed in the second contact hole.
In this embodiment, the third isolation layer 341 is made of silicon oxide or a low-k dielectric material.
In other embodiments, a top surface of the second isolation layer is higher than a surface of the first conductive structure at the top of the fin pillar; the forming method may not form the third isolation layer. The step of forming the second conductive structure comprises: forming a third contact hole in the second isolation layer, wherein the bottom of the third contact hole is exposed out of the first conductive structure at the top of the fin portion column; and forming a second conductive structure in the third contact hole. Or the top surface of the second isolation layer is lower than or flush with the surface of the first conductive structure at the top of the fin column; the second conductive structure is located on the top surface of the second isolation layer, covers the side wall of the top area of the fin portion column, and is located on the surface of the first conductive structure on the top of the fin portion column.
In other embodiments, the top surface of the second isolation layer is lower than the top surface of the fin pillar, and the top surface of the fin pillar does not have the first conductive structure. The second conductive structure covers the sidewalls and the top surface of the fin column top region. The second conductive structure includes: the fourth metallization layer is positioned on the side wall and the top surface of the second source drain doped region; a second conductive layer overlying the fourth metallization layer.
The step of forming the second conductive structure includes: forming a fourth metallization layer on the side wall and the top surface of the second source drain doped region; and forming a second conducting layer on the second isolating layer, wherein the second conducting layer covers the surface of the fourth metallization layer.
With continued reference to fig. 24, embodiments of the present invention further provide a semiconductor structure, comprising: the semiconductor device comprises a substrate 200, wherein a fin part column 201 is arranged on the substrate 200, and the fin part column 201 comprises a bottom area A, a channel area B positioned on the bottom area A and a top area C positioned on the channel area B; the first gate oxide layer 231 and the second gate oxide layer 232 are positioned on the surface of the side wall of the channel region B of the fin portion pillar 201, the second gate oxide layer 232 is positioned on the surface of the top of the first gate oxide layer 231, and the thicknesses of the first gate oxide layer 231 and the second gate oxide layer 232 are different; a gate structure 263 covering said first gate oxide layer 231 and said second gate oxide layer 232.
The semiconductor structure further includes: a first isolation layer 220 on the substrate 200, the first isolation layer 220 covering the fin pillar 201 bottom region a; a second isolation layer 262 on the top surface of the gate structure 263, wherein the second isolation layer 262 covers the sidewall of the top region C of the fin pillar 201.
It should be noted that the arrangement direction of the bottom region a, the channel region B and the top region C is perpendicular to the surface of the substrate 200, the arrangement direction of the source region, the drain region and the gate of the formed semiconductor structure is perpendicular to the surface of the substrate 200, and the area of the surface of the substrate 200 occupied by the formed semiconductor structure is small, so that the integration level of the formed semiconductor structure is high. In addition, the surface of the side wall of the channel region B of the fin column 201 is provided with a first gate oxide layer 231 and a second gate oxide layer 232, the thicknesses of the first gate oxide layer 231 and the second gate oxide layer 232 are different, so that the threshold voltage of the semiconductor structure is not too high, and the first gate oxide layer 231 and the second gate oxide layer 232 of the semiconductor structure are not easy to be broken down, thereby improving the performance of the formed semiconductor structure.
In this embodiment, the semiconductor structure further includes: and the first source-drain doping layer 211 is positioned on the surface of the substrate 200, and the first source-drain doping layer 211 covers the surface of the top region C of the fin column 201. In other embodiments, the semiconductor structure further comprises: and the first source-drain doped region is positioned in one or the combination of the substrate and the bottom region of the fin column.
In this embodiment, the semiconductor structure further includes: a dielectric layer 260 on the first isolation layer 220, wherein the dielectric layer 260 covers the sidewall of the gate structure 263; the top surface of the dielectric layer 260 is higher than or flush with the top surface of the fin portion pillar 201; the dielectric layer 260 has an isolation opening therein, and the bottom of the isolation opening exposes the top of the gate structure 263; the second isolation layer 262 is located in the isolation opening.
In other embodiments, the semiconductor structure does not include the dielectric layer. And the grid structures of the first grid oxide layer and the second grid oxide layer which cover the channel region of the fin part column are mutually contacted.
In this embodiment, the semiconductor structure further includes: a second interconnect structure in the second isolation structure, the second interconnect structure contacting the fin pillar 201 top region C.
In other embodiments, the semiconductor structure does not include the second interconnect structure. And the second isolation layer surface is lower than or flush with the top area top surface. The semiconductor structure further includes: and the second conductive structure is positioned at the top of the second structure and covers the surface of the top area of the fin column.
In this embodiment, the semiconductor structure further includes: and the second source-drain doped region is positioned in the top region C of the fin column 201. In other embodiments, the semiconductor structure includes: and the second source-drain doping layer is positioned in the top region of the fin portion column or on the surface of the top region of the fin portion column.
In other embodiments, a top surface of the second isolation layer is lower than the fin pillar top region. The semiconductor structure further includes: a third isolation layer on the second isolation layer, the third isolation layer covering the top and sidewalls of the top region. Alternatively, the semiconductor structure further comprises: a second conductive structure on a top surface of the second isolation layer, the second conductive structure covering the top region sidewall and top surface.
The semiconductor structure further includes: the first source-drain doping layer 211 is located on the surface of the substrate 200, the first source-drain doping layer 211 covers the bottom area a of the fin column 201, and the first isolation layer 220 covers the top surface of the first source-drain doping layer 211; a first contact hole in the dielectric layer 260, wherein the bottom of the first contact hole exposes the first source-drain doping layer 211; a first highly doped region located in the first source drain doped layer 211 at the bottom of the first contact hole; a first interconnect structure 270 in the first contact hole.
The bottom region a of the substrate 200 is used for connecting a first potential, and the top region C of the fin pillar 201 is used for connecting a second potential; the first potential is greater than the second potential, and the thickness of the first gate oxide 321 is greater than that of the second gate oxide 322; or, the second potential is greater than the first potential, and the thickness of the first gate oxide 321 is less than that of the second gate oxide 322.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part column, and the fin part column comprises a bottom region, a channel region positioned on the bottom region and a top region positioned on the channel region;
forming a first gate oxide layer and a second gate oxide layer on the surface of the side wall of the fin part column channel region, wherein the second gate oxide layer is positioned on the surface of the top of the first gate oxide layer, and the thicknesses of the first gate oxide layer and the second gate oxide layer are different;
forming a grid structure covering the side walls of the first grid oxide layer and the second grid oxide layer;
the thickness of the first gate oxide layer is larger than that of the second gate oxide layer, and the second gate oxide layer is formed after the first gate oxide layer is formed; the method for forming the first gate oxide layer comprises the following steps: performing first oxidation treatment on the fin part column channel region and the top region, and forming a first initial gate oxide layer on the surfaces of the fin part column channel region and the top region; removing the first initial gate oxide layer of the top region and part of the channel region in contact with the top region to form a first gate oxide layer; the method for forming the second gate oxide layer comprises the following steps: performing second oxidation treatment on the fin portion column, and forming a second gate oxide layer on the surface of the exposed fin portion column;
or the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer; the method for forming the first gate oxide layer and the second gate oxide layer comprises the following steps: performing third oxidation treatment on the fin part column channel region and the top region, and forming first gate oxide layers on the surfaces of the side walls of the fin part column channel region and the top region; forming a pattern layer covering the first gate oxide layer, wherein the top surface of the pattern layer is lower than that of the channel region; performing fourth oxidation treatment on the fin part column by taking the graphic layer as a mask, and increasing the thickness of the exposed first gate oxide layer to form a second gate oxide layer;
the fin portion column bottom region is used for being connected with a first potential, and the fin portion column top region is used for being connected with a second potential; the first electric potential is greater than the second electric potential, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer; or the second potential is greater than the first potential, and the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer.
2. The method of forming a semiconductor structure of claim 1, wherein when the thickness of said first gate oxide layer is greater than the thickness of said second gate oxide layer, further comprising: forming a first isolation layer on the substrate, wherein the first isolation layer covers the bottom region of the fin column, and the grid structure is positioned on the top surface of the first isolation layer; forming a second isolation layer on the top surface of the grid structure, wherein the second isolation layer covers the side wall of the top area of the fin column;
the method for removing the top region and the part of the channel region first initial gate oxide layer contacted with the top region comprises the following steps: forming a sacrificial layer on the top surface of the first isolation layer, wherein the sacrificial layer completely covers the top surface of the first isolation layer and covers a part of the first initial gate oxide layer of the channel region, the top surface of the sacrificial layer is lower than the top surface of the channel region, and the material of the sacrificial layer is different from that of the first isolation layer; and etching the first initial gate oxide layer by taking the sacrificial layer as a mask, and removing the exposed first initial gate oxide layer to form a first gate oxide layer.
3. The method for forming a semiconductor structure according to claim 2, wherein the sacrificial layer is made of polysilicon, amorphous silicon, amorphous carbon, or an organic dielectric material; the first isolation layer is made of silicon oxide, silicon nitride or low-k dielectric materials.
4. The method of forming a semiconductor structure of claim 1, wherein the first oxidation process comprises an in-situ water vapor generation process; the technological parameters of the first oxidation treatment comprise that the reaction temperature is 850-1050 ℃;
the second oxidation treatment process comprises an in-situ water vapor generation process; the technological parameters of the second oxidation treatment comprise that the reaction temperature is 850-1050 ℃.
5. The method of forming a semiconductor structure of claim 1, wherein when the thickness of said first gate oxide layer is greater than the thickness of said second gate oxide layer, the thickness of said first gate oxide layer is between 35 angstroms and 45 angstroms; the thickness of the second gate oxide layer is 13-17 angstroms.
6. The method of forming a semiconductor structure of claim 1, wherein the removing the first initial gate oxide layer of the top region and the portion of the channel region in contact with the top region comprises: forming a protective side wall covering a part of the side wall of the first initial gate oxide layer, wherein the top of the protective side wall is lower than the surface of the top of the channel region; and etching the first initial gate oxide layer by taking the protective side wall as a mask, and removing the first initial gate oxide layer exposed by the protective side wall to form a first gate oxide layer.
7. The method of forming a semiconductor structure of claim 1, further comprising, after forming the gate structure: and removing the second gate oxide layer in the top area.
8. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: forming a first source drain doping layer on the surface of the substrate, wherein the first source drain doping layer covers the side wall of the bottom area of the fin portion column; the grid structure is positioned at the top of the first source-drain doped layer.
9. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: forming a first conductive structure on the surface of the substrate, wherein the first conductive structure is electrically connected with the bottom region of the fin column; the gate structure is located on top of the first conductive structure.
10. The method of forming a semiconductor structure of claim 1, further comprising, after forming the first gate oxide layer and the second gate oxide layer: forming a dielectric layer on the substrate; the dielectric layer covers the side wall of the grid structure;
the method for forming the grid structure and the dielectric layer comprises the following steps: forming a pseudo gate structure covering the first gate oxide layer, the second gate oxide layer and the side wall of the top area of the fin portion column; forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure and exposes the top surface of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the dielectric layer; forming a first gate structure layer in the gate opening; and removing the first grid structure layer in the top area to form a grid structure.
11. The method of claim 10, wherein the number of the fin pillars is multiple, and gate structures on surfaces of the multiple fin pillars are separated from each other;
the method for forming the dummy gate structure comprises the following steps: forming a dummy gate layer on the substrate, wherein the dummy gate layer covers the side wall of the channel region of the fin portion column, the side wall of the top region and the surface of the top portion; and etching the pseudo gate layer, removing part of the pseudo gate layer to form a pseudo gate structure, wherein the pseudo gate structures covering the adjacent fin portion columns are mutually separated.
12. The method of forming a semiconductor structure of claim 10, further comprising: forming a first source drain doping layer on the surface of the substrate, wherein the first source drain doping layer covers the side wall of the bottom area of the fin portion column; the grid structure is positioned at the top of the first source-drain doping layer;
after the gate structure is formed, the method further comprises the following steps: forming a first contact hole in the dielectric layer, wherein the bottom of the first contact hole is exposed out of the first source drain doping layer; after the first contact hole is formed, performing first supplementary ion implantation on the first source drain doping layer exposed at the bottom of the first contact hole, and forming a first high doping region in the first source drain doping layer; and forming a first interconnection structure in the first contact hole after the first supplementary ion implantation.
13. The method of forming a semiconductor structure of claim 1, wherein forming the gate structure comprises: forming a second grid structure layer on the top of the substrate, wherein the second grid structure layer covers the first grid oxide layer, the second grid oxide layer and the side wall of the top area of the fin part column; and etching the second gate structure layer, and removing the second gate structure layer in the top region to form a gate structure.
14. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: forming a first source drain doped region in the bottom region of the fin column or the substrate; after the gate structure is formed, the method further comprises the following steps: performing ion implantation on the fin portion column top region, and forming a second source drain doped region in the fin portion column top region;
or, before forming the gate structure, further comprising: forming a barrier layer on the surface of the side wall of the fin part column channel region; performing ion implantation on the fin portion column by taking the barrier layer as a mask, forming a first source drain doped region in the bottom region of the fin portion column, and forming a second source drain doped region in the top region of the fin portion column;
or, further comprising: forming a second isolation layer on the top surface of the gate structure, wherein the second isolation layer covers the side wall of the top region of the fin column, removing the top region of the fin column, and forming a source drain groove in the second isolation layer; and forming a second source-drain doping layer in the source-drain groove.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101399207A (en) * 2007-09-24 2009-04-01 国际商业机器公司 Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby
CN104425608B (en) * 2013-08-19 2019-05-07 爱思开海力士有限公司 Three-dimensional semiconductor device, variable resistance memory device and its manufacturing method including it

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940751B2 (en) * 2002-04-26 2005-09-06 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
JP2011035169A (en) * 2009-07-31 2011-02-17 Renesas Electronics Corp Nonvolatile semiconductor memory device and method of manufacturing the same
DE102015116473A1 (en) * 2015-09-29 2017-03-30 Infineon Technologies Austria Ag SEMICONDUCTOR ELEMENT AND METHOD

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101399207A (en) * 2007-09-24 2009-04-01 国际商业机器公司 Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby
CN104425608B (en) * 2013-08-19 2019-05-07 爱思开海力士有限公司 Three-dimensional semiconductor device, variable resistance memory device and its manufacturing method including it

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