CN109947671B - Address translation method and device, electronic equipment and storage medium - Google Patents
Address translation method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides an address conversion method, an address conversion device, electronic equipment and a storage medium, wherein the method comprises the following steps: determining address information to be converted according to the acquired conversion instruction; acquiring a target address corresponding to the conversion instruction in a kernel by utilizing an address incidence relation according to the address information to be converted; because the address association relationship is a mapping relationship between the address information of the first array corresponding to the first type and the address information of the second array corresponding to the second type, which is generated based on the address information stored in the memory in advance according to the preset write strategy, the mutual conversion between the target address and the address to be converted can be realized based on the address association relationship according to the address information to be converted determined by the conversion instruction, the operation is simple, the universality on different operating systems is realized, and the flexibility of the operating systems can be further improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an address translation method, an address translation apparatus, an electronic device, and a storage medium.
Background
At present, a driver using DMA (chinese: Direct Memory Access) will communicate with hardware connected to a bus interface, and since the hardware uses a physical address and the program code uses a virtual address, and the DMA-based hardware uses a bus address, i.e. a DMA address, a connection channel will be established between the DMA address and the physical address, so that the program code can Access the DMA address by accessing the corresponding physical address.
In the prior art, the conversion mode between the DMA address and the physical address is a fixed script written into the kernel of the DMA address corresponding to different chips or bridges, and cannot be modified randomly. Therefore, if a new conversion mode exists, a corresponding new implementation mode needs to be added to the kernel, and the applicability of the operating system on other kernels cannot be realized; and each new conversion mode is required to be modified in the kernel, so that the operation is complex.
Disclosure of Invention
In view of the above, embodiments of the present invention are proposed to provide an address translation method that overcomes or at least partially solves the above problems to ensure the versatility of an operating system on a kernel.
Correspondingly, the embodiment of the invention also provides an address conversion device, electronic equipment and a storage medium, which are used for ensuring the realization and application of the method.
In order to solve the above problem, an embodiment of the present invention discloses an address translation method, including:
determining address information to be converted according to the acquired conversion instruction;
acquiring a target address corresponding to the conversion instruction in a memory by utilizing an address incidence relation according to the address information to be converted;
the address association relationship is a mapping relationship between address information in a first array corresponding to the first type and address information in an array corresponding to the second type, and the address information in the first array and the address information in the second array are address information stored in the memory according to a write strategy.
Optionally, before the step of determining address information to be converted according to the obtained conversion instruction, the method further includes:
writing pre-acquired first address information and second address information into a target array according to the write strategy, wherein the first address information comprises a plurality of first types of address information, the second address information comprises a plurality of second types of address information, and the address information comprises addresses, address base addresses and address sizes;
and traversing the target array by utilizing a predetermined traversal function to split the target array into the first array and the second array, wherein the traversal function is a function set according to the type of address data which is added to the target header file in advance.
Optionally, the writing the first address information and the second address information into the target array according to the write strategy includes:
placing the plurality of first types of address information in close proximity to each other in the target array;
placing the plurality of second types of address information in close proximity to each other in the target array;
wherein an arrangement order of the plurality of first type address information coincides with an arrangement order of the plurality of second type address information.
Optionally, the traversing the target array by using a predetermined traversal function to split the target array into a first array corresponding to the first type and a second array corresponding to the second type includes:
traversing all address information in the target array;
sequentially placing the traversed address information with the address type being the first type into the first array;
and sequentially putting the traversed address information with the address type of the second type into the second array.
Optionally, the obtaining, according to the address information to be converted, a target address corresponding to the conversion instruction in a memory by using an address association relationship includes:
determining target address information according to the address information to be converted, wherein the target address information comprises the target address type, a target section corresponding to the target address and a target identifier corresponding to the target address;
and determining the target address by utilizing the address association relation according to the address information to be converted and the target address information.
Optionally, the address information to be converted includes an address to be converted and a type of the address to be converted, and determining the target address information according to the address information to be converted includes:
searching the address to be converted in an array corresponding to the type of the address to be converted to determine an address section where the address to be converted is located and an address identifier of the address to be converted;
determining that the target address type is the second type, the target sector is the address sector under the second array, and the target identifier is the address identifier under the second array, if the address type to be converted is the first type;
and under the condition that the type of the address to be converted is the second type, determining that the target address type is the first type, the target section is the address section under the first array, and the target identifier is the address identifier under the first array.
Optionally, the determining the target address according to the address information to be converted and the target address information by using the address association relationship includes:
acquiring a first address base address with the address information of the target identifier and a second address base address corresponding to the target section in the array corresponding to the target address type;
and adding the sum of the difference between the address to be converted and the second address base address and the first address to be used as the target address.
The embodiment of the invention also discloses an address conversion device, which comprises:
the information determining module is used for determining the address information to be converted according to the acquired conversion instruction;
the address acquisition module is used for acquiring a target address corresponding to the conversion instruction in the memory by utilizing an address incidence relation according to the address information to be converted;
the address association relationship is a mapping relationship between address information in a first array corresponding to a first type and address information in a second array corresponding to a second type, and the address information in the first array and the address information in the second array are address information stored in the memory according to a write strategy.
Optionally, the apparatus further comprises:
an address writing module, configured to write, before the step of determining address information to be converted according to the obtained conversion instruction, first address information and second address information, which are obtained in advance, into a target array according to the write strategy, where the first address information includes a plurality of pieces of address information of the first type, the second address information includes a plurality of pieces of address information of the second type, and the address information includes an address, an address base address, and an address size;
and the array traversing module is used for traversing the target array by utilizing a predetermined traversing function so as to split the target array into the first array and the second array, and the traversing function is a function set according to the address data types added to the target header file in advance.
Optionally, the address writing module is configured to:
placing the plurality of first types of address information in close proximity to each other in the target array;
placing the plurality of second types of address information in close proximity to each other in the target array;
wherein an arrangement order of the plurality of first type address information coincides with an arrangement order of the plurality of second type address information.
Optionally, the array traversal module includes:
the traversal submodule is used for traversing all address information in the target array;
the array generation submodule is used for sequentially placing the traversed address information with the address type being the first type into the first array;
and the array generation submodule is also used for sequentially putting the traversed address information with the address type being the second type into the second array.
Optionally, the address obtaining module includes:
the information determining submodule is used for determining target address information according to the address information to be converted, wherein the target address information comprises the target address type, a target section corresponding to the target address and a target identifier corresponding to the target address;
and the address determining submodule is used for determining the target address by utilizing the address association relation according to the address information to be converted and the target address information.
Optionally, the address information to be converted includes an address to be converted and a type of the address to be converted, and the information determining sub-module includes:
the address searching unit is used for searching the address to be converted in an array corresponding to the type of the address to be converted so as to determine an address section where the address to be converted is located and an address identifier of the address to be converted;
an information determining unit, configured to determine that the target address type is the second type, the target extent is the address extent in the second number group, and the target identifier is the address identifier in the second number group, when the address type to be converted is the first type;
the information determining unit is further configured to determine that the target address type is the first type, the target section is the address section in the first array, and the target identifier is the address identifier in the first array, when the address type to be converted is the second type.
Optionally, the address determination sub-module includes:
an offset obtaining unit, configured to obtain, in the array corresponding to the target address type, a first address base address having address information of the target identifier and a second address base address corresponding to the target segment;
and the address determination unit is used for adding the difference between the address to be converted and the second address base address and the first address to obtain the sum, and the sum is used as the target address.
An embodiment of the present invention also discloses an electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
determining address information to be converted according to the acquired conversion instruction;
acquiring a target address corresponding to the conversion instruction in a memory by utilizing an address incidence relation according to the address information to be converted;
the address association relationship is a mapping relationship between address information in a first array corresponding to a first type and address information in a second array corresponding to a second type, and the address information in the first array and the address information in the second array are address information stored in the memory according to a write strategy.
The embodiment of the invention also discloses a readable storage medium, and when instructions in the storage medium are executed by a processor of the electronic equipment, the electronic equipment can execute one or more address conversion methods in the embodiment of the invention.
The embodiment of the invention has the following advantages:
determining address information to be converted according to the acquired conversion instruction; acquiring a target address corresponding to the conversion instruction in a kernel by utilizing an address incidence relation according to the address information to be converted; because the address association relationship includes a mapping relationship between the address information in the first array corresponding to the first type and the address information in the second array corresponding to the second type, the address information in the first array and the address information in the second array are the address information stored in the memory according to the write strategy. Therefore, the mutual conversion between the target address and the address to be converted can be realized based on the address association relation determined when the address information is written in advance according to the address information to be converted determined by the conversion instruction, the operation is simple, the method can be suitable for different operating systems, the operating system does not need to be modified even when the address information is changed, and the flexibility of the operating system can be improved.
Drawings
FIG. 1 is a flow chart of the steps of an embodiment of an address translation method of the present invention;
FIG. 2 is a flow chart of steps in another address translation method embodiment of the present invention;
FIG. 3 is a flow chart of steps of yet another address translation method embodiment of the present invention;
FIG. 4 is a flow chart of steps of yet another address translation method embodiment of the present invention;
FIG. 5 is a flow chart of steps of yet another address translation method embodiment of the present invention;
FIG. 6 is a block diagram of an embodiment of an address translation device according to the present invention;
FIG. 7 is a block diagram of an alternative address translation device embodiment of the present invention;
fig. 8 is a block diagram of an electronic device for address translation according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, a flowchart illustrating steps of an embodiment of an address translation method of the present invention is shown, which may specifically include the following steps:
In a specific application, the technical scheme of the invention can realize the conversion between the DMA address and the physical address, thereby ensuring that the program code can access the DMA address by accessing the corresponding physical address. Since DMA is a data transfer method for reducing the workload of a CPU, it is possible to transfer data (particularly, transfer a large amount of data) without involvement of the CPU. For example, the direct data transmission of copying the data of the peripheral a to the peripheral B is realized by DMA, and a link that needs the participation of a CPU register in data transmission is eliminated, which is essentially to transmit the data from one area of the memory to another area of the memory (the data register of the peripheral is essentially a storage unit of the memory). Correspondingly, the technical scheme provided by the invention can also realize the operation of converting the physical address into the DMA address. Therefore, according to the conversion instruction acquired by the operating system, whether the DMA address is converted into the physical address or the physical address is converted into the DMA address is determined, and the following operation is performed to acquire the target address.
In addition, it should be noted that, because the address information stored in the memory is written into the corresponding target array and stored according to a preset write strategy, for example, the DMA address and the physical address are written in an adjacent and sequential manner, or the DMA address and the physical address are written in a preset order (address of odd identification is written first and address of even identification is written second) with a preset interval (each address information interval is 2 bytes), so that the address information in the first array and the address information in the second array have a one-to-one mapping relationship.
And 102, acquiring a target address corresponding to the conversion instruction in the memory by using the address association relation according to the address information to be converted.
The address association relationship is a mapping relationship between address information in a first array corresponding to the first type and address information in a second array corresponding to the second type, and the address information in the first array and the address information in the second array are address information stored in the memory according to a write strategy.
In a specific application, since the first type of address information and the second type of address information are stored in the memory in advance according to the write strategy, a mapping relationship between the two types of (first type and second type) address information generated correspondingly is used as an address association relationship. And then, by using the address association relationship, and according to the address information to be converted determined in step 101, the target address corresponding to the address to be converted is searched in the memory correspondingly, so that the conversion between the addresses can be realized. For example, when the address to be translated is a physical address, the corresponding lookup DMA address is used as the target address.
In summary, according to the technical scheme provided by the application, the address information to be converted is determined according to the obtained conversion instruction; acquiring a target address corresponding to a conversion instruction in a memory by utilizing an address association relation according to the address information to be converted; the address association relationship is a mapping relationship between the first type of address information and the second type of address information, and the first type of address information and the second type of address information are address information pre-stored in a memory according to a write strategy. Therefore, by utilizing the predetermined address mapping relation in the memory, the corresponding target address can be obtained when the DMA address and the physical address are converted, the operation is simple, meanwhile, the universality of various operating systems is realized, and the operation of modifying in the kernel to realize parameter transmission each time is omitted.
Optionally, referring to fig. 2, a flowchart illustrating steps of another embodiment of an address translation method according to the present invention is shown, before step 101, the method may further include the following steps:
The first address information comprises a plurality of first type address information, the second address information comprises a plurality of second type address information, and the address information comprises an address, an address base address and an address size.
Illustratively, a physical address and a DMA address are written into a target array as a first type of address information and a second type of address information, respectively, i.e., in an efi _ memory _ map _ logson.map [ ] array of type struct mem _ map, into which the first address information and the second address information are written according to a write strategy. It should be noted that, in addition to the physical address and the DMA address, the target array also stores attribute information corresponding thereto, i.e., an address base address and an address size.
Optionally, the step includes the following sub-steps:
sub-step a1, a plurality of address information of the first type are placed next to each other in the target array.
Sub-step a2, a plurality of address information of the second type are placed next to each other in the target array.
Wherein, the arrangement order of the plurality of first type address information is consistent with the arrangement order of the plurality of second type address information.
Illustratively, in a multi-way environment, address information of the same type is placed next to each other, and SYSTEM _ RAM _ LOW (LOW address of physical address) of all nodes are placed next to each other in an array; and the SYSTEM _ RAM _ HIGH (HIGH address of physical address) of all nodes are also placed in the array immediately adjacent; the DMA address types are also the same, the SYSTEM _ RAM _ LOW _ DMA (the LOW address of the DMA address) of all the nodes are immediately placed in the array, the SYSTEM _ RAM _ HIGH _ DMA (the HIGH address of the DMA address) of all the nodes is also immediately placed in the array, and based on the write strategy, it is further required to ensure that the ordering of the first address information of the first type in all the address information of the first type is consistent with the ordering of the second address information of the second type corresponding to the first address information in all the address information of the second type, and the storage order of the DMA addresses is consistent with the storage order of the physical addresses. That is, when the high address of the physical address of the node 1 is arranged at the second bit in the storage area of the physical high address, the high address of the DMA address of the corresponding node 1 is also arranged at the second bit in the storage area of the DMA high address, thereby ensuring that the physical address and the DMA address are mapped one by one after each type of address information is split in the following steps.
And 104, traversing the target array by using a predetermined traversal function so as to split the target array into a first array and a second array.
Wherein the traversal function is a function set according to the type of address data previously added to the target header file.
It should be noted that, since an address data type (SYSTEM _ RAM _ LOW; SYSTEM _ RAM _ HIGH) corresponding to a physical address is already present in a target header file (for storing all data transferred from firmware to a kernel: a boot _ param.h file) of a memory, in order to ensure that a mapping relationship (address association relationship) is generated between a DMA address and a physical address pre-stored in the memory, an address data type corresponding to a DMA address is added to the target header file in advance by using a BIOS (chinese: Basic Input Output SYSTEM; english: Basic Input Output SYSTEM), that is, two address data types are added to the boot _ param.h file: SYSTEM _ RAM _ LOW _ DMA and SYSTEM _ RAM _ HIGH _ DMA, wherein the SYSTEM _ RAM _ LOW _ DMA is used for identifying a LOW address of a DMA address; SYSTEM _ RAM _ HIGH _ DMA is used to identify the HIGH address of the DMA address. Because the kernel traverses all address information in the target array by using the address traversal function to classify the address information according to corresponding address types (a high address of a physical address and a low address of the physical address), but because two predefined address data types (DMA address types) cannot be identified by the original address traversal function, the original address traversal function is improved according to the newly added address data types so as to generate a new traversal function capable of identifying the newly defined address data types (the low address of the DMA address and the high address of the DMA). For example, a conditional select statement may be added to the original address traversal function to distinguish between the low address of the DMA address newly defined in the above step and the high address of the DMA to ensure that the address information in the target array can be fully classified.
Illustratively, the first array includes a first type of address information; the second array includes a second type of address information.
In a specific application, the kernel splits data in efi _ memory _ map _ loongson.map [ ] arrays into two arrays according to the address types (high address of physical address, low address of physical address, high address of DMA address, low address of DMA address) by using a traversal function, wherein the first array (ls _ phy _ map) is used for storing start (base address, a 64-bit 2-system address for indicating the start address of the low address) and size (size) of the low address of the physical address and start and size (size) of the high address of the physical address; the second array (ls _ DMA _ map) is used to store the start and size of the lower address of the DMA address and the start and size of the lower address of the DMA address, thereby facilitating the one-to-one mapping of the first address to the second address or the second address to the first address at step 102.
Illustratively, this step may include the sub-steps of:
substep B1, traverse all address information in the target array.
And a sub-step B2 of sequentially putting the traversed address information with the first type of address into the first array.
And a sub-step B3 of sequentially putting the traversed address information with the second type into a second array.
In specific application, the kernel performs traversal of all address information by using a traversal function, and when the address information of a first type is encountered, the address information is put into a first array; when the second type of address information is encountered, the second array is put in, and because the address information of each type is written into the target array according to the same sequence by using a preset write strategy, the address information in the first array and the address information in the second array which are split after traversal are in one-to-one correspondence, namely, the DMA address corresponds to the physical address. Furthermore, when the address information changes or the conversion mode of the address information changes, the kernel of the operating system does not need to be changed, and only the written address information needs to be correspondingly modified, so that the operating system can still be started and used on other kernels, and the universality of the operating system is realized.
Optionally, referring to fig. 3, which is a flowchart illustrating a step of another embodiment of the address translation method according to the present invention, where the step 102 obtains a target address corresponding to the translation instruction in a memory according to the address information to be translated by using an address association relationship may include the following steps:
The target address information includes a target address type, a target section corresponding to the target address, and a target identifier corresponding to the target address.
Exemplarily, a section where the target address is located is determined according to the address information to be translated, that is, whether the target address is a high address or a low address is determined, and if the address to be translated is a high address of a physical address, the corresponding target address is a high address of a DMA address; otherwise, if the address to be converted is the low address of the DMA address, the corresponding target address is the low address of the physical address. Illustratively, the identification information of each address is used for distinguishing the node to which the address belongs, for example, the high address first node, and the corresponding tag information is H1; the low address second node has corresponding label information L2. Therefore, the type of the target address, the target section corresponding to the target address and the target identifier corresponding to the target address can be respectively determined according to the address information to be converted.
Optionally, as shown in fig. 4, the step may include the following steps:
Illustratively, the address to be converted is searched in the array corresponding to the address type to be converted, when the address paddr to be converted is a physical address, the array corresponding to the address type to be converted is ls _ phy _ map, and the corresponding traversal manner is as follows:
(paddr>＝ls_phy_map[i].mem_start)&&
(paddr<(ls_phy_map[i].mem_start+ls_phy_map[i].mem_size)
starting from 0, i is searched until the maximum number of addresses stored in the corresponding ls _ phy _ map is searched.
In specific application, according to the address information to be converted, the section where the address to be converted is located and the address identifier of the address to be converted are searched and determined, and then the target address information is correspondingly determined. For example, the type of the address to be converted is a first type, the address section where the address to be converted is located and found in the first array is a high address section, and the address identifier of the address to be converted is 1, that is, the address to be converted corresponds to H1 of the first array, it may be determined that the type of the target address is a second type, and the target section is a high address section of the second array and the target identifier is 1, that is, the target address corresponds to H1 of the second array.
And step 1022, determining the target address by using the address association relationship according to the address information to be converted and the target address information.
For example, since the first address information and the second address information are written in a one-to-one correspondence manner in step 105, the target address may be correspondingly obtained in the first type array and the second type array according to the target address type and the target address identification information.
Optionally, as shown in fig. 5, the step may include the following steps:
For example, when the type of the address to be translated is a first type, for example, the address is a physical address, and the identification information is H1, the address information of the corresponding address to be translated may be looked up in the array corresponding to the physical address (the array of the first type).
For example, the address association relationship may be expressed as the following formula:
the destination address (start + of the address with destination identification — start of the segment where the address to be translated is located), for example, when the address to be translated is a physical address (paddr), the translation expression of the destination address (daddr) is:
daddr＝ls_dma_map[i].mem_start+(paddr-ls_phy_map[i].mem_start)；
correspondingly, when the address to be translated is a DMA address (daddr), the translation expression of the destination address (paddr) is:
paddr＝ls_phy_map[i].mem_start+(daddr-ls_dma_map[i].mem_start)。
it should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 6, a block diagram of an embodiment of an address translation device according to the present invention is shown, which may specifically include the following modules:
an information determining module 610, configured to determine address information to be converted according to the obtained conversion instruction;
an address obtaining module 620, configured to obtain, according to the address information to be converted, a target address corresponding to the conversion instruction in the memory by using the address association relationship;
the address association relationship is a mapping relationship between address information in a first array corresponding to the first type and address information in a second array corresponding to the second type, and the address information in the first array and the address information in the second array are address information stored in the memory according to a write strategy.
Optionally, referring to fig. 7, a block diagram of a structure of another embodiment of the address translation apparatus of the present invention is shown, which may specifically include the following modules:
an address writing module 630, configured to write, before the step of determining address information to be converted according to the obtained conversion instruction, first address information and second address information, which are obtained in advance, into the target array according to a write policy, where the first address information includes a plurality of first-type address information, the second address information includes a plurality of second-type address information, and the address information includes an address, an address base address, and an address size.
The array traversal module 640 is configured to traverse the target array by using a predetermined traversal function to split the target array into a first array and a second array, where the traversal function is a function set according to a type of address data that is added to the target header file in advance.
Optionally, the address writing module 630 is configured to:
placing a plurality of first types of address information in close proximity to each other in a target array;
placing a plurality of second type address information in close proximity to each other in a target array;
wherein, the arrangement order of the plurality of first type address information is consistent with the arrangement order of the plurality of second type address information.
Optionally, the array traversal module 640 includes:
the traversal submodule is used for traversing all address information in the target array;
the array generation submodule is used for sequentially putting the traversed address information with the first type into a first array;
and the array generation submodule is also used for sequentially putting the traversed address information with the second type into a second array.
Optionally, the address obtaining module 620 includes:
the information determining submodule 621 is configured to determine target address information according to the address information to be converted, where the target address information includes a target address type, a target segment corresponding to the target address, and a target identifier corresponding to the target address.
And the address determining submodule 622 is configured to determine the target address by using the address association relationship according to the address information to be converted and the target address information.
Optionally, the address information to be converted includes an address to be converted and an address type to be converted, and the information determining sub-module 621 includes:
the address searching unit is used for searching the address to be converted in the array corresponding to the type of the address to be converted so as to determine an address section where the address to be converted is located and the address identifier of the address to be converted;
the information determining unit is used for determining that the target address type is a second type, the target sector is an address sector under a second array and the target identifier is an address identifier under the second array under the condition that the type of the address to be converted is a first type;
the information determining unit is further configured to determine that the target address type is the first type, the target section is an address section under a first array, and the target identifier is an address identifier under the first array, when the type of the address to be converted is the second type.
Optionally, the address determination sub-module 622 includes:
and the offset acquisition unit is used for acquiring a first address base address with address information of a target identifier and a second address base address corresponding to the target section in an array corresponding to the target address type.
And the address determination unit is used for adding the difference between the address to be converted and the second address base address and the first address to obtain a target address.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as a memory comprising instructions, executable by a processor of an electronic device to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium, instructions in which, when executed by a processor of a terminal, enable the terminal to perform an address translation method, the method comprising:
determining address information to be converted according to the acquired conversion instruction;
acquiring a target address corresponding to a conversion instruction in a memory by utilizing an address association relation according to the address information to be converted;
the address association relationship is a mapping relationship between address information in a first array corresponding to the first type and address information in a second array corresponding to the second type, and the address information in the first array and the address information in the second array are address information pre-stored in the memory according to a write strategy.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
FIG. 8 is a block diagram illustrating a structure of an electronic device 800 for address translation, according to an example embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
Referring to fig. 8, electronic device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.
The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing elements 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operation at the device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The power components 804 provide power to the various components of the electronic device 800. Power components 804 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for electronic device 800.
The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 800 is in an operation mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 818. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the electronic device 800. For example, the sensor assembly 814 may detect an open/closed state of the device 800, the relative positioning of components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, orientation or acceleration/deceleration of the electronic device 800, and a change in the temperature of the electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 814 receives a broadcast signal or broadcast associated information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communications component 814 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The address translation method and apparatus, the electronic device, and the storage medium provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the description of the above examples is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. An address translation method, the method comprising:
determining address information to be converted according to the acquired conversion instruction;
acquiring a target address corresponding to the conversion instruction in a memory by using an address association relation according to the address information to be converted, wherein the method comprises the following steps: determining target address information according to the address information to be converted, wherein the target address information comprises the target address type, a target section corresponding to the target address and a target identifier corresponding to the target address; determining the target address by utilizing the address association relation according to the address information to be converted and the target address information;
the address association relationship is a mapping relationship between address information in a first array corresponding to a first type and address information in a second array corresponding to a second type, and the address information in the first array and the address information in the second array are address information stored in a memory according to a write strategy.
2. The method according to claim 1, wherein before the step of determining address information to be converted according to the obtained conversion instruction, the method further comprises:
writing pre-acquired first address information and second address information into a target array according to the write strategy, wherein the first address information comprises a plurality of first types of address information, the second address information comprises a plurality of second types of address information, and the address information comprises addresses, address base addresses and address sizes;
and traversing the target array by utilizing a predetermined traversal function to split the target array into the first array and the second array, wherein the traversal function is a function set according to the type of address data which is added to the target header file in advance.
3. The method of claim 2, wherein writing the first address information and the second address information into the target array according to the write strategy comprises:
placing the plurality of first types of address information in close proximity to each other in the target array;
placing the plurality of second types of address information in close proximity to each other in the target array;
wherein an arrangement order of the plurality of first type address information coincides with an arrangement order of the plurality of second type address information.
4. The method of claim 2 or 3, wherein traversing the target array using a predetermined traversal function to split the target array into a first array corresponding to the first type and a second array corresponding to the second type comprises:
traversing all address information in the target array;
sequentially placing the traversed address information with the address type being the first type into the first array;
and sequentially putting the traversed address information with the address type of the second type into the second array.
5. The method of claim 1, wherein the address information to be translated includes an address to be translated and a type of the address to be translated, and the determining the target address information according to the address information to be translated includes:
searching the address to be converted in an array corresponding to the type of the address to be converted to determine an address section where the address to be converted is located and an address identifier of the address to be converted;
determining that the target address type is the second type, the target sector is the address sector under the second array, and the target identifier is the address identifier under the second array, if the address type to be converted is the first type;
and under the condition that the type of the address to be converted is the second type, determining that the target address type is the first type, the target section is the address section under the first array, and the target identifier is the address identifier under the first array.
6. The method according to claim 1, wherein the determining the target address by using the address association relationship according to the address information to be converted and the target address information comprises:
acquiring a first address base address with the address information of the target identifier and a second address base address corresponding to the target section in an array corresponding to the target address type;
and adding the sum of the difference between the address to be converted and the second address base address and the first address to be used as the target address.
7. An address translation device, the device comprising:
the information determining module is used for determining the address information to be converted according to the acquired conversion instruction;
an address obtaining module, configured to obtain, according to the address information to be converted, a target address corresponding to the conversion instruction in a memory by using an address association relationship, where the address obtaining module includes: the information determining submodule is used for determining target address information according to the address information to be converted, wherein the target address information comprises the target address type, a target section corresponding to the target address and a target identifier corresponding to the target address; the address determining submodule is used for determining the target address by utilizing the address association relation according to the address information to be converted and the target address information;
the address association relationship is a mapping relationship between address information in a first array corresponding to a first type and address information in a second array corresponding to a second type, and the address information in the first array and the address information in the second array are address information stored in a memory according to a write strategy.
8. The apparatus of claim 7, further comprising:
an address writing module, configured to write, before the step of determining address information to be converted according to the obtained conversion instruction, first address information and second address information, which are obtained in advance, into a target array according to the write strategy, where the first address information includes a plurality of pieces of address information of the first type, the second address information includes a plurality of pieces of address information of the second type, and the address information includes an address, an address base address, and an address size;
and the array traversing module is used for traversing the target array by utilizing a predetermined traversing function so as to split the target array into the first array and the second array, and the traversing function is a function set according to the address data types added to the target header file in advance.
9. The apparatus of claim 8, wherein the address writing module is configured to:
placing the plurality of first types of address information in close proximity to each other in the target array;
placing the plurality of second types of address information in close proximity to each other in the target array;
wherein an arrangement order of the plurality of first type address information coincides with an arrangement order of the plurality of second type address information.
10. The apparatus of claim 8 or 9, wherein the array traversal module comprises:
the traversal submodule is used for traversing all address information in the target array;
the array generation submodule is used for sequentially placing the traversed address information with the address type being the first type into the first array;
and the array generation submodule is also used for sequentially putting the traversed address information with the address type being the second type into the second array.
11. The apparatus according to claim 7, wherein the address information to be translated includes an address to be translated and a type of the address to be translated, and the information determining sub-module includes:
the address searching unit is used for searching the address to be converted in an array corresponding to the type of the address to be converted so as to determine an address section where the address to be converted is located and an address identifier of the address to be converted;
an information determining unit, configured to determine that the target address type is the second type, the target extent is the address extent in the second number group, and the target identifier is the address identifier in the second number group, when the address type to be converted is the first type;
the information determining unit is further configured to determine that the target address type is the first type, the target section is the address section in the first array, and the target identifier is the address identifier in the first array, when the address type to be converted is the second type.
12. The apparatus of claim 7, wherein the address determination submodule comprises:
an offset obtaining unit, configured to obtain, in the array corresponding to the target address type, a first address base address having address information of the target identifier and a second address base address corresponding to the target segment;
and the address determination unit is used for adding the difference between the address to be converted and the second address base address and the first address to obtain the sum, and the sum is used as the target address.
13. An electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors the one or more programs including instructions for:
determining address information to be converted according to the acquired conversion instruction;
acquiring a target address corresponding to the conversion instruction in a memory by using an address association relation according to the address information to be converted, wherein the method comprises the following steps: determining target address information according to the address information to be converted, wherein the target address information comprises the target address type, a target section corresponding to the target address and a target identifier corresponding to the target address; determining the target address by utilizing the address association relation according to the address information to be converted and the target address information;
the address association relationship is a mapping relationship between address information in a first array corresponding to a first type and address information in a second array corresponding to a second type, and the address information in the first array and the address information in the second array are address information stored in a memory according to a write strategy.
14. A readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the address translation method according to any of method claims 1-6.
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