CN109903730B

CN109903730B - Buffer circuit

Info

Publication number: CN109903730B
Application number: CN201910112826.XA
Authority: CN
Inventors: 刘立伟; 陈彦渊; 黄柏文; 庄凯杰; 邓至刚
Original assignee: Yili Technology Cayman Co Ltd
Current assignee: ILI Techonology Corp
Priority date: 2019-02-13
Filing date: 2019-02-13
Publication date: 2021-04-06
Anticipated expiration: 2039-02-13
Also published as: CN109903730A

Abstract

A buffer circuit includes an operational amplifier, a first switch circuit and a second switch circuit. The operational amplifier has a first and a second input terminal, a first and a second output terminal. The operational amplifier comprises a front stage circuit, a first output stage and a second output stage. The front-stage circuit is coupled to the first input terminal to receive the input signal, and coupled to the second input terminal to receive the feedback signal and generate an amplified signal. The first output stage is coupled between the front-stage circuit and the first output terminal, and generates a first output signal according to the amplified signal to drive the first load. The second output stage is coupled between the front-stage circuit and the second output terminal, and generates a second output signal according to the amplified signal to drive a second load. The first switch circuit is coupled between the first output terminal and the second input terminal. The second switch circuit is coupled between the second output terminal and the second input terminal. When the first switch circuit is turned on and the first output stage generates the first output signal to drive the first load, the second switch circuit is turned off and the second output stage is disabled.

Description

Buffer circuit

Technical Field

The present invention relates to a buffer circuit, and more particularly, to a buffer circuit with high slew rate.

Background

A panel of the liquid crystal display device includes a plurality of liquid crystal display cells (liquid crystal cells). It is known that applying a voltage of the same polarity to a liquid crystal layer in a liquid crystal display cell for a long time causes charge ions to remain at the interface between the liquid crystal layer and an alignment film, thereby generating an internal electric field. This may cause a change in light transmission characteristics of liquid crystal molecules therein, causing irreversible damage to the liquid crystal panel. Therefore, the source driver of the liquid crystal display device usually prevents the liquid crystal molecules from being damaged by the driving voltage of the same polarity being continuously applied thereto by continuously changing the polarity of the driving voltage applied to the liquid crystal display unit.

In detail, in order to satisfy the requirement of outputting driving voltages with different polarities, a transmission gate is generally disposed at an output end of an output buffer circuit of a source driver to switch the driving voltage output to a data line. Although this method can satisfy the requirement of switching the polarity of the driving voltage, the pass gate for switching the polarity of the driving voltage has a certain resistance, which reduces the Slew Rate (Slew Rate) of the output buffer circuit, thereby affecting the charging and discharging speed and characteristics of the pixel capacitor and reducing the display quality of the liquid crystal display device.

Disclosure of Invention

Accordingly, the present invention is directed to a buffer circuit with high slew rate to solve the problems of the prior art.

The buffer circuit of the invention comprises an operational amplifier, a first switch circuit and a second switch circuit. The operational amplifier has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The operational amplifier comprises a front-stage circuit, a first output stage and a second output stage. The front-stage circuit is coupled to the first input terminal to receive the input signal, and coupled to the second input terminal to receive the feedback signal, and generates an amplified signal accordingly. The first output stage is coupled between the front-stage circuit and the first output terminal, and is used for generating a first output signal according to the amplified signal to drive a first load. The second output stage is coupled between the previous stage circuit and the second output terminal, and is configured to generate a second output signal according to the amplified signal to drive the second load, wherein a polarity of the second output signal is the same as a polarity of the first output signal. The first switch circuit is coupled between the first output terminal and the second input terminal, and is used for transmitting the first output signal to the second input terminal as a feedback signal when being conducted. The second switch circuit is coupled between the second output terminal and the second input terminal, and is used for transmitting a second output signal to the second input terminal as a feedback signal when the second switch circuit is switched on. When the first switch circuit is switched on and the first output stage generates a first output signal to drive the first load, the second switch circuit is switched off and the second output stage is disabled; and when the second switch circuit is turned on and the second output stage generates the second output signal to drive the second load, the first switch circuit is turned off and the first output stage is disabled, at least one of the two.

Based on the above, in the buffer circuit provided by the present invention, the first output stage of the operational amplifier is used to drive the first load, and the second output stage of the operational amplifier is used to drive the second load, so that compared with the conventional buffer circuit in which different loads are alternately driven by the same output stage through switching the transmission gates, the buffer circuit of the present invention can omit the transmission gate for switching the polarity of the driving voltage between the operational amplifier and the load, which not only reduces the circuit area of the buffer circuit, but also effectively increases the slew rate of the output signal of the buffer circuit, thereby increasing the driving capability of the buffer circuit.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1A is a circuit diagram of a buffer circuit according to an embodiment of the invention;

FIG. 1B is a circuit diagram of a buffer circuit according to another embodiment of the present invention;

FIG. 2A is a circuit diagram illustrating an operational amplifier of the embodiment of FIG. 1A according to one embodiment of the invention;

FIG. 2B is a circuit diagram of the operational amplifier of the embodiment of FIG. 1B according to an embodiment of the present invention;

FIG. 3A is a circuit diagram of a buffer circuit according to another embodiment of the present invention;

FIG. 3B is a circuit diagram of a buffer circuit according to another embodiment of the present invention;

FIG. 4A is a circuit diagram illustrating the operational amplifier of the embodiment of FIG. 3A according to one embodiment of the present invention;

FIG. 4B is a circuit diagram of the operational amplifier of FIG. 3B according to one embodiment of the invention.

The reference numbers illustrate:

100. 200, 500, 600: buffer circuit

110. 210: first switch circuit

120. 220, and (2) a step of: second switch circuit

130. 230, 330, 430, 530, 630, 730, 830: operational amplifier

131. 231, 331, 431, 731, 831: a first output stage

132. 232, 332, 432, 732, 832: second output stage

133. 233, 333, 433, 733, 833: preceding stage circuit

143. 243, and (3) a step of: third switch circuit

144. 244: fourth switch circuit

145: substrate voltage switching circuit

211_ 1A: first differential pair

211_ 1B: second differential pair

211_ 2A: a first current source

211_ 2B: a second current source

213A: first active load

213B: second active load

331_1, 431_1, 731_1, 831_1, 332_1, 432_1, 732_1, 832_ 1: switching circuit

331_2, 431_2, 731_2, 831_2, 332_2, 432_2, 732_2, 832_ 2: output circuit

534. 634, 734, 834: feedback output stage

AGND: ground voltage terminal

AVBN1H, AVBN2H, AVBN3H, AVBN4H, AVBN5H, AVBP1H, AVBP2H, AVBP3H, AVBP4H, AVBP 5H: positive bias voltage

AVBN1L, AVBN2L, AVBN3L, AVBN4L, AVBN5L, AVBP1L, AVBP2L, AVBP3L, AVBP4L, AVBP 5L: negative bias voltage

AVF1, AVF 2: feedback signal

HPT: control voltage

HPTB: inverted control voltage

IT1, IT 3: a first input terminal

IT2, IT 4: second input terminal

M31, M32, M41, M42, M51 to M58, M71, M72, M81, M82, N1A, N2A, N3A, N4A, N5 to N9, N9A, N9B, N10, N11, P1A, P2A, P3A, P4A, P5 to P9, P9A, P9B, P10, P11, NSW1A, PSW1A, NSW1B, PSW 1B: transistor with a metal gate electrode

MCN, MCP: miller capacitance

NAVDD: negative voltage terminal

OT1, OT 3: a first output terminal

OT2, OT 4: second output terminal

OUT1A, OUT 2A: first output signal

OUT1B, OUT 2B: second output signal

PAVDD: positive voltage terminal

S11-S18: switching signal

SN: second sub-amplified signal

SP: first sub-amplified signal

SNDA, SNDB, SPDA, SPDB: signal

SW11, SW12, SW21, SW 22: grounding switch

SW1A, SW2A, SW3A, SW4A, SW5A, SW1B, SW2B, SW3B, SW4B, SW 5B: switch with a switch body

SWA _ P, SWB _ P, SWA _ N, SWB _ N: selection signal

SWAB _ P, SWBB _ P, SWAB _ N, SWBB _ N: inverted select signal

TG11, TG12, TG21, TG 22: transmission gate

VAP, VAN: amplifying a signal

VINP, VINN: input signal

VNW1, VNW2, VPW1, VPW 2: base voltage

Y1, Y2: load(s)

Detailed Description

Fig. 1A is a circuit diagram of a buffer circuit according to an embodiment of the invention. Please refer to fig. 1A. The buffer circuit 100 may be disposed in a source driver of a display device, and is configured to generate a positive voltage signal to drive a pixel of a display panel. The buffer circuit 100 may include a first switch circuit 110, a second switch circuit 120, and an operational amplifier 130, but the present invention is not limited thereto. The operational amplifier 130 has a first input terminal IT1, a second input terminal IT2, a first output terminal OT1, and a second output terminal OT 2. The operational amplifier 130 may include a pre-stage 133, a first output stage 131, and a second output stage 132. The front-stage circuit 133 is coupled to the first input terminal IT1 for receiving the input signal VINP, and coupled to the second input terminal IT2 for receiving the feedback signal AVF1, and accordingly generates the amplified signal VAP, wherein the input signal VINP is a positive voltage signal. The first output stage 131 is coupled between the previous stage 133 and the first output terminal OT1 for generating a first output signal OUT1A to drive the load Y1 according to the amplified signal VAP, wherein the first output signal OUT1A is a positive voltage signal. The second output stage 132 is coupled between the previous stage circuit 133 and the second output terminal OT2 for generating a second output signal OUT1B to drive the load Y2 according to the amplified signal VAP, wherein the polarity of the second output signal OUT1B is the same as the polarity of the first output signal OUT 1A. In the present embodiment, the load Y1 and the load Y2 are two data lines (or source lines) of the display panel, respectively.

The first switch circuit 110 is coupled between the first output terminal OT1 and the second input terminal IT 2. The first switch circuit 110 is configured to transmit the first output signal OUT1A to the second input terminal IT2 as the feedback signal AVF1 when being turned on. The second switch circuit 120 is coupled between the second output terminal OT2 and the second input terminal IT 2. The second switch circuit 120 is configured to transmit the second output signal OUT1B to the second input terminal IT2 as the feedback signal AVF1 when being turned on.

Specifically, when the first switch circuit 110 is turned on and the first output stage 131 generates the positive polarity first output signal OUT1A to drive the load Y1, the second switch circuit 120 is turned off and the second output stage 132 is disabled, so that the second output terminal OT2 is in a high impedance state and stops driving the load Y2. At this time, the load Y2 can be driven by the negative polarity output signal generated by another buffer circuit.

Alternatively, when the second switch circuit 120 is turned on and the second output stage 132 generates the positive polarity second output signal OUT1B to drive the load Y2, the first switch circuit 110 is turned off and the first output stage 131 is disabled, such that the first output terminal OT1 is in a high impedance state and the driving of the load Y1 is stopped. At this time, the load Y1 can be driven by the negative polarity output signal generated by another buffer circuit.

Since the first output stage 131 is only used for driving the load Y1 and the second output stage 132 is only used for driving the load Y2, the transmission gate for switching the polarity of the driving voltage between the buffer circuit 100 and the loads Y1 and Y2 can be omitted compared to the conventional buffer circuit in which different loads are alternately driven by the same output stage by switching the transmission gate. The present invention not only can reduce the circuit area of the buffer circuit 100, but also can effectively improve the slew rate of the output signal of the buffer circuit 100, thereby improving the driving capability of the buffer circuit 100.

In addition, as shown in fig. 1A, the buffer circuit 100 may further optionally include a third switch circuit 143 and a fourth switch circuit 144. The third switch circuit 143 is coupled between the first output terminal OT1 and the load Y1, and transmits the first output signal OUT1A to the load Y1 when turned on. The fourth switch circuit 144 is coupled between the second output terminal OT2 and the load Y2, and transmits the second output signal OUT1B to the load Y2 when being turned on.

Further, the third switch circuit 143 may include a ground switch SW11 and a transmission gate TG 11. The ground switch SW11 is coupled between the first output terminal OT1 and the ground voltage terminal AGND. The transmission gate TG11 is coupled between the first output terminal OT1 and the load Y1, wherein the ground switch SW11 is in an opposite on-off state from the transmission gate TG 11. In addition, the transmission gate TG11 includes a P-type transistor M31 and an N-type transistor M32. The first terminal of the P-type transistor M31 is coupled to the first output terminal OT1, the second terminal of the P-type transistor M31 is coupled to the load Y1, and the control terminal of the P-type transistor M31 is coupled to the ground voltage terminal AGND. The first terminal of the N-type transistor M32 is coupled to the first output terminal OT1, the second terminal of the N-type transistor M32 is coupled to the load Y1, and the control terminal of the N-type transistor M32 receives the control voltage HPT.

Similarly, the fourth switching circuit 144 may include a ground switch SW12 and a transmission gate TG 12. The ground switch SW12 is coupled between the second output terminal OT2 and the ground voltage terminal AGND. The transmission gate TG12 is coupled between the second output terminal OT2 and the load Y2, wherein the ground switch SW12 is in an opposite on-off state to the transmission gate TG 12. In addition, the transmission gate TG12 includes a P-type transistor M41 and an N-type transistor M42. The first terminal of the P-type transistor M41 is coupled to the second output terminal OT2, the second terminal of the P-type transistor M41 is coupled to the load Y2, and the control terminal of the P-type transistor M41 is coupled to the ground voltage terminal AGND. The first terminal of the N-type transistor M42 is coupled to the second output terminal OT2, the second terminal of the N-type transistor M42 is coupled to the load Y2, and the control terminal of the N-type transistor M42 receives the inverted control voltage HPTB.

When the first output stage 131 generates the first output signal OUT1A to drive the load Y1, the second output stage 132 is disabled. At this time, the transmission gate TG11 is turned on, and the ground switch SW11 is turned off, so that the first output signal OUT1A can be transmitted to the load Y1 through the transmission gate TG 11. The transmission gate TG12 is turned off and the ground switch SW12 is turned on, so that the second output terminal OT2 is grounded by the turned-on ground switch SW 12. Therefore, the voltage polarity of the second output terminal OT2 opposite to the voltage polarity of the load Y2 can be prevented from causing the voltage across the two terminals of the transmission gate TG12 to be too high and damaged.

Similarly, when the second output stage 132 generates the second output signal OUT1B to drive the load Y2, the first output stage 131 is disabled. At this time, the transmission gate TG12 is turned on, and the ground switch SW12 is turned off, so that the second output signal OUT1B can be transmitted to the load Y2 through the transmission gate TG 12. The transmission gate TG11 is turned off and the ground switch SW11 is turned on, so that the first output terminal OT1 is grounded by the turned-on ground switch SW 11. Therefore, the voltage polarity of the first output terminal OT1 opposite to the voltage polarity of the load Y1 can be prevented from causing the voltage across the two terminals of the transmission gate TG11 to be too high and damaged.

In addition, as shown in fig. 1A, the buffer circuit 100 may also optionally include a substrate voltage switching circuit 145. The substrate voltage switching circuit 145 includes P-type transistors M51, M53, M55, M57, and N-type transistors M52, M54, M56, M58. The P-type transistor M51 and the N-type transistor M52 are connected in series between the positive voltage terminal PAVDD and the ground voltage terminal AGND, and the P-type transistor M51 and the N-type transistor M52 are controlled by the switching signals S11 and S12, respectively, to provide the substrate voltage VNW1 of the P-type transistor M31 in the transmission gate TG11, so as to avoid the forward substrate bias generated when the P-type transistor M31 is turned on or off. The P-type transistor M53 and the N-type transistor M54 are connected in series between a ground voltage terminal AGND and a negative voltage terminal NAVDD, and the P-type transistor M53 and the N-type transistor M54 are controlled by switching signals S13 and S14, respectively, to provide a substrate voltage VPW1 of the N-type transistor M32 in the transmission gate TG11, so as to avoid forward substrate bias when the N-type transistor M32 is turned on or off. The P-type transistor M55 and the N-type transistor M56 are connected in series between the positive voltage terminal PAVDD and the ground voltage terminal AGND, and the P-type transistor M55 and the N-type transistor M56 are controlled by the switching signals S15 and S16, respectively, to provide the substrate voltage VNW2 of the P-type transistor M41, so as to avoid the forward substrate bias generated when the P-type transistor M41 in the transmission gate TG12 is turned on or off. The P-type transistor M57 and the N-type transistor M58 are connected in series between a ground voltage terminal AGND and a negative voltage terminal NAVDD, and the P-type transistor M57 and the N-type transistor M58 are controlled by switching signals S17 and S18, respectively, to provide a substrate voltage VPW2 of the N-type transistor M42, so as to avoid forward substrate bias when the N-type transistor M42 in the transmission gate TG12 is turned on or off.

Fig. 1B is a circuit diagram of a buffer circuit according to another embodiment of the invention. Please refer to fig. 1B. The buffer circuit 200 may be disposed in a source driver of a display device, and is used for generating a negative voltage signal to drive a pixel of a display panel. The buffer circuit 200 may include a first switch circuit 210, a second switch circuit 220, and an operational amplifier 230, but the present invention is not limited thereto. The operational amplifier 230 has a first input terminal IT3, a second input terminal IT4, a first output terminal OT3, and a second output terminal OT 4. The operational amplifier 230 may include a front stage 233, a first output stage 231, and a second output stage 232. The front stage 233 is coupled to the first input terminal IT3 for receiving the input signal VINN, and coupled to the second input terminal IT4 for receiving the feedback signal AVF2, and generates the amplified signal VAN according to the received input signal VINN, wherein the input signal VINN is a negative voltage signal. The first output stage 231 is coupled between the previous stage 233 and the first output terminal OT3, and is configured to generate a first output signal OUT2A according to the amplified signal VAN to drive the load Y2, wherein the first output signal OUT2A is a negative voltage signal. The second output stage 232 is coupled between the previous stage 233 and the second output terminal OT4 for generating a second output signal OUT2B to drive the load Y1 according to the amplified signal VAN, wherein the polarity of the second output signal OUT2B is the same as the polarity of the first output signal OUT 2A. In the present embodiment, the load Y1 and the load Y2 are two data lines (or source lines) of the display panel, respectively.

The first switch circuit 210 is coupled between the first output terminal OT3 and the second input terminal IT 4. The first switch circuit 210 is configured to transmit the first output signal OUT2A to the second input terminal IT4 as the feedback signal AVF2 when being turned on. The second switch circuit 220 is coupled between the second output terminal OT4 and the second input terminal IT 4. The second switch circuit 220 is configured to transmit the second output signal OUT2B to the second input terminal IT4 as the feedback signal AVF2 when being turned on.

Referring to fig. 1A and fig. 1B, in the first embodiment of the invention, when the first switch circuit 210 is turned on and the first output stage 231 generates the negative first output signal OUT2A to drive the load Y2, the second switch circuit 220 is turned off and the second output stage 232 is disabled, so that the second output terminal OT4 is in a high impedance state and stops driving the load Y1. At this time, the load Y1 can be driven by the first output signal OUT1A (with positive polarity) generated by the first output stage 131 of the buffer circuit 100 of fig. 1A.

In the second embodiment of the present invention, when the second switch circuit 220 is turned on and the second output stage 232 generates the negative polarity second output signal OUT2B to drive the load Y1, the first switch circuit 210 is turned off and the first output stage 231 is disabled, such that the first output terminal OT3 is in a high impedance state and stops driving the load Y2. At this time, the load Y2 can be driven by the second output signal OUT1B (with positive polarity) generated by the second output stage 132 of the buffer circuit 100 of fig. 1A. Of course, the first embodiment and the second embodiment can also be implemented.

Since the first output stage 231 is only used for driving the load Y2 and the second output stage 232 is only used for driving the load Y1, compared to the conventional buffer circuit in which different loads are alternately driven by the same output stage by switching transmission gates, the buffer circuit 200 of the present embodiment can omit the transmission gate for switching the polarity of the driving voltage between the load Y1 and the load Y2, which not only reduces the circuit area of the buffer circuit 200, but also effectively increases the slew rate of the output signal of the buffer circuit 200, thereby increasing the driving capability of the buffer circuit 200.

In addition, as shown in fig. 1B, the buffer circuit 200 may further optionally include a third switch circuit 243 and a fourth switch circuit 244. The third switch circuit 243 is coupled between the first output terminal OT3 and the load Y2, and transmits the first output signal OUT2A to the load Y2 when being turned on. The fourth switch circuit 244 is coupled between the second output terminal OT4 and the load Y1, and transmits the second output signal OUT2B to the load Y1 when being turned on.

Further, the third switch circuit 243 may include a ground switch SW21 and a transmission gate TG 21. The ground switch SW21 is coupled between the first output terminal OT3 and the ground voltage terminal AGND. The transmission gate TG21 is coupled between the first output terminal OT3 and the load Y2, wherein the ground switch SW21 is in an opposite on-off state from the transmission gate TG 21. In addition, the transmission gate TG21 includes a P-type transistor M71 and an N-type transistor M72. The first terminal of the P-type transistor M71 is coupled to the first output terminal OT3, the second terminal of the P-type transistor M71 is coupled to the load Y2, and the control terminal of the P-type transistor M71 receives the inverted control voltage HPTB. The first terminal of the N-type transistor M72 is coupled to the first output terminal OT3, the second terminal of the N-type transistor M72 is coupled to the load Y2, and the control terminal of the N-type transistor M72 is coupled to the ground voltage terminal AGND. The operation of the ground switch SW21 and the transmission gate TG21 is similar to the operation of the ground switch SW12 and the transmission gate TG12 in fig. 1A, so that the above description can be analogized, and the description thereof is omitted.

Similarly, the fourth switching circuit 244 may include a ground switch SW22 and a transmission gate TG 22. The ground switch SW22 is coupled between the second output terminal OT4 and the ground voltage terminal AGND. The transmission gate TG22 is coupled between the second output terminal OT4 and the load Y1, wherein the ground switch SW22 is in an opposite on-off state to the transmission gate TG 22. In addition, the transmission gate TG22 includes a P-type transistor M81 and an N-type transistor M82. The first terminal of the P-type transistor M81 is coupled to the second output terminal OT4, the second terminal of the P-type transistor M81 is coupled to the load Y1, and the control terminal of the P-type transistor M81 receives the control voltage HPT. The first terminal of the N-type transistor M82 is coupled to the second output terminal OT4, the second terminal of the N-type transistor M82 is coupled to the load Y1, and the control terminal of the N-type transistor M82 is coupled to the ground voltage terminal AGND. The operation of the ground switch SW22 and the transmission gate TG22 is similar to the operation of the ground switch SW11 and the transmission gate TG11 in fig. 1A, so that the above description can be referred to, and the description thereof is omitted.

In addition, the buffer circuit 200 may also optionally include a substrate voltage switching circuit (not shown). The structure and function of the substrate voltage switching circuit are similar to those of the substrate voltage switching circuit 145 in fig. 1A, and therefore, the above description can be referred to, and will not be repeated herein.

Referring to fig. 1A and fig. 2A in combination, fig. 2A is a circuit diagram of an operational amplifier according to the embodiment of fig. 1A according to an embodiment of the invention. The operational amplifier 330 includes a pre-stage 333, a first output stage 331, and a second output stage 332. The front-stage circuit 333 includes a first differential pair 211_1A, a second differential pair 211_1B, a first current source 211_2A, a second current source 211_2B, a first active load 213A, a second active load 213B, a first impedance provider formed by transistors N10 and P10, a second impedance provider formed by transistors N11 and P11, and miller capacitors MCP and MCN.

The first differential pair 211_1A and the second differential pair 211_1B form an input stage of the front stage circuit 333. The first differential pair 211_1A includes a first differential pair formed by transistors N2A, N1A, wherein the transistor N2A receives the input signal VINP, and the transistor N1A receives the feedback signal AVF 1. The second differential pair 211_1B includes a second differential pair formed by transistors P2A, P1A, wherein the transistor P2A receives the input signal VINP, and the transistor P1A receives the feedback signal AVF 1. The first differential pair 211_1A and the second differential pair 211_1B are complementary in shape.

The first current source 211_2A includes transistors N3A and N4A. Transistor N4A receives the positive bias voltage AVBN2H and transistor N3A receives the positive bias voltage AVBN 1H. The first current source 211_2A is coupled between the first differential pair 211_1A and the ground voltage terminal AGND. The second current source 211_2B includes transistors P4A and P3A. Transistor P4A receives a positive bias voltage AVBP2H and transistor P3A receives a positive bias voltage AVBP 1H. The second current source 211_2B is coupled between the second differential pair 211_1B and the positive voltage terminal PAVDD. In the present embodiment, the first current source 211_2A and the second current source 211_2B are complementary.

The first active load 213A is formed by transistors P5-P8, and the second active load 213B is formed by transistors N5-N8. The first active load 213A is coupled between the positive voltage terminal PAVDD and the first differential pair 211_ 1A. The second active load 213B is coupled between the ground voltage terminal AGND and the second differential pair 211_ 1B. The first active load 213A and the second active load 213B have complementary shapes. The first terminals of the transistors P5 and P6 are connected to the positive voltage terminal PAVDD, the control terminals of the transistors P5 and P6 are coupled to each other and to the second terminal of the transistor P7, and the second terminals of the transistors P5 and P6 are coupled to the first terminals of the transistors P7 and P8, respectively. In addition, the control terminals of the transistors P7 and P8 commonly receive the positive bias voltage AVBP 4H. First terminals of the transistors N5 and N6 are coupled to the ground voltage terminal AGND, control terminals of the transistors N5 and N6 are coupled to each other and to the first terminal of the transistor N7, and second terminals of the transistors N5 and N6 are coupled to second terminals of the transistors N7 and N8, respectively. In addition, the control terminals of the transistors N7, N8 commonly receive the positive bias voltage AVBN 4H.

The first impedance provider formed by the transistors N10 and P10 is coupled between the first active load 213A and the second active load 213B, and the second impedance provider formed by the transistors N11 and P11 is coupled between the first active load 213A and the second active load 213B. The second impedance provider formed by the transistors N11 and P11, together with the first active load 213A and the second active load 213B, forms a gain stage circuit of the front stage circuit 333, and generates an amplified signal VAP (shown in fig. 1A) including the first sub-amplified signal SP and the second sub-amplified signal SN.

More specifically, the transistors N10 and P10 are coupled in parallel between the second terminal of the transistor P7 and the first terminal of the transistor N7. The control terminals of the transistors N10 and P10 receive the positive bias voltages AVBN3H and AVBP3H, respectively. The transistors N11 and P11 are coupled in parallel between the second terminal of the transistor P8 and the first terminal of the transistor N8. The control terminals of the transistors N11 and P11 receive the positive bias voltages AVBN5H and AVBP5H, respectively.

The first output stage 331 includes a switch circuit 331_1 and an output circuit 331_ 2. The switch circuit 331_1 is coupled to the front-stage circuit 333 and turns on or off the first signal transmission channel according to the selection signal SWA _ P. The output circuit 331_2 is coupled to the switch circuit 331_1, receives the first sub-amplified signal SP and the second sub-amplified signal SN through the first signal transmission channel, and generates the first output signal OUT1A according to the first sub-amplified signal SP and the second sub-amplified signal SN.

The switch circuit 331_1 includes switches SW1A-SW 5A. The switches SW1A, SW2A and SW3A are configured by transmission gates, and the switches SW4A and SW5A are respectively configured by the transistors PSW1A and the transistors NSW 1A. The switches SW1A and SW2A are controlled by the selection signal SWA _ P and the inverted selection signal SWAB _ P to be turned on or off, and provide a first signal transmission path to transmit the first sub-amplified signal SP and the second sub-amplified signal SN to the output circuit 331_2, respectively. The switch SW3A is coupled between the output terminal of the output circuit 331_2 and the miller capacitors MCP and MCN of the previous stage circuit 333. The switch SW3A is turned on or off by the selection signal SWA _ P and the inverted selection signal SWAB _ P. The switch SW4A is coupled between the first input terminal of the output circuit 331_2 and the positive voltage terminal PAVDD, and is turned on or off according to the selection signal SWA _ P. The switch SW5A is coupled between the second input terminal of the output circuit 331_2 and the ground voltage terminal AGND, and is turned on or off according to the inverted selection signal SWAB _ P.

The switches SW4A and SW5A are respectively used as a pull-up switch and a pull-down switch, and are turned on when the switches SW1A and SW2A are turned off to respectively provide the voltage of the positive voltage terminal PAVDD and the voltage of the ground voltage terminal AGND to the first input terminal and the second input terminal of the output circuit 331_ 2. The on-off states of the switches SW1A, SW2A and SW3A are the same, the on-off states of the switches SW4A and SW5A are the same, the on-off states of the switches SW1A and SW4A are complementary (opposite), and the on-off states of the switches SW2A and SW5A are complementary (opposite).

The output circuit 331_2 includes a transistor P9A and a transistor N9A. Transistor P9A and transistor N9A receive signals SPDA and SNDA, respectively. When the switches SW1A and SW2A are turned on, the signals SPDA and SNDA are equal to the first sub-amplified signal SP and the second sub-amplified signal SN, respectively, and the output circuit 331_2 generates the first output signal OUT1A to drive the pixel. On the other hand, when the switches SW1A and SW2A are turned off, the signals SPDA and SNDA are equal to the voltage of the positive voltage terminal PAVDD and the voltage of the ground voltage terminal AGND, respectively, and at this time, the output circuit 331_2 stops generating the first output signal OUT1A, and makes the first output signal OUT1A in a high impedance state.

The second output stage 332 includes a switching circuit 332_1 and an output circuit 332_ 2. The switch circuit 332_1 is coupled to the front-stage circuit 333 and turns on or off the second signal transmission channel according to the selection signal SWB _ P. The output circuit 332_2 is coupled to the switch circuit 332_1, receives the first sub-amplified signal SP and the second sub-amplified signal SN through the second signal transmission channel, and generates the second output signal OUT1B according to the first sub-amplified signal SP and the second sub-amplified signal SN.

The switch circuit 332_1 includes switches SW1B-SW 5B. The switches SW1B, SW2B and SW3B are configured by transmission gates, and the switches SW4B and SW5B are respectively configured by the transistors PSW1B and the transistors NSW 1B. The switches SW1B and SW2B are controlled by the selection signal SWB _ P and the inverted selection signal SWBB _ P to be turned on or off, and provide a second signal transmission channel to transmit the first sub-amplified signal SP and the second sub-amplified signal SN to the output circuit 332_2, respectively. The switch SW3B is coupled between the output terminal of the output circuit 332_2 and the miller capacitors MCP and MCN of the previous stage circuit 333. The switch SW3B is turned on or off by the selection signal SWB _ P and the inverted selection signal SWBB _ P. The switch SW4B is coupled between the first input terminal of the output circuit 332_2 and the positive voltage terminal PAVDD, and is turned on or off according to the selection signal SWB _ P. The switch SW5B is coupled between the second input terminal of the output circuit 332_2 and the ground voltage terminal AGND, and is turned on or off according to the inverted selection signal SWBB _ P.

The switches SW4B and SW5B are respectively used as a pull-up switch and a pull-down switch, and are turned on when the switches SW1B and SW2B are turned off, so as to respectively provide the voltage of the positive voltage terminal PAVDD and the voltage of the ground voltage terminal AGND to the first input terminal and the second input terminal of the output circuit 332_ 2. The on-off states of the switches SW1B, SW2B and SW3B are the same, the on-off states of the switches SW4B and SW5B are the same, the on-off states of the switches SW1B and SW4B are complementary (opposite), and the on-off states of the switches SW2B and SW5B are complementary (opposite).

The output circuit 332_2 includes a transistor P9B and a transistor N9B. Transistor P9B and transistor N9B receive signals SPDB and SNDB, respectively. When the switches SW1B and SW2B are turned on, the signals SPDB and SNDB are equal to the first sub-amplified signal SP and the second sub-amplified signal SN, respectively, and the output circuit 332_2 generates the second output signal OUT1B to drive the pixel. On the other hand, when the switches SW1B and SW2B are turned off, the signals SPDB and SNDB are equal to the voltage of the positive voltage terminal PAVDD and the voltage of the ground voltage terminal AGND, respectively, and at this time, the output circuit 332_2 stops generating the second output signal OUT1B, and makes the second output signal OUT1B in a high impedance state.

It should be noted that the on/off states of the switches SW1B, SW2B, SW3B are complementary (opposite) to the on/off states of the switches SW1A, SW2A, SW 3A. In other words, when the output circuit 332_2 generates the second output signal OUT1B to drive the pixel, the output circuit 332_1 stops generating the first output signal OUT1A and makes the first output signal OUT1A in a high impedance state, and vice versa.

Referring to fig. 2B, fig. 2B is a circuit diagram of the operational amplifier shown in fig. 1B according to an embodiment of the invention. The operational amplifier 430 includes a front stage 433, a first output stage 431, and a second output stage 432. The first output stage 431 includes a switching circuit 431_1 and an output circuit 431_ 2. The second output stage 432 includes a switch circuit 432_1 and an output circuit 432_ 2.

The operational amplifier 430 of fig. 2B is similar to the operational amplifier 330 of fig. 2A, and the difference between the two is that the operational amplifier 330 is coupled between the positive voltage terminal PAVDD and the ground voltage terminal AGND, that is, the operational amplifier 330 is implemented in a positive power domain (positive power domain), and the operational amplifier 430 is coupled between the negative voltage terminal NAVDD and the ground voltage terminal AGND, that is, the operational amplifier 430 is implemented in a negative power domain (negative power domain). Therefore, in the front stage circuit 433, the transistor N4A receives the negative bias voltage AVBN2L, the transistor N3A receives the negative bias voltage AVBN1L, the transistor P4A receives the negative bias voltage AVBP2L, the transistor P3A receives the negative bias voltage AVBP1L, the control terminals of the transistors P7 and P8 commonly receive the negative bias voltage AVBP4L, and the control terminals of the transistors N7 and N8 commonly receive the negative bias voltage AVBN 4L. In addition, the selection signals SWA _ N, SWB _ N and the inverted selection signal SWAB _ N, SWBB _ N in the switch circuits 431_1 and 432_1 are negative polarity signals, compared to the selection signals SWA _ P, SWB _ P and the inverted selection signal SWAB _ P, SWBB _ P in the switch circuits 331_1 and 332_1, which are positive polarity signals. Details of the implementation and operation of the operational amplifier 430 in fig. 2B can be obtained by analogy with the description of fig. 2A, and are not repeated herein.

Fig. 3A is a circuit diagram of a buffer circuit according to another embodiment of the invention. Please refer to fig. 3A. The buffer circuit 500 may include the first switch circuit 110, the second switch circuit 120, the operational amplifier 530, the third switch circuit 143, the fourth switch circuit 144, and the substrate voltage switching circuit 145, but the present invention is not limited thereto. The first switch circuit 110, the second switch circuit 120, the third switch circuit 143, the fourth switch circuit 144, and the substrate voltage switching circuit 145 in fig. 3A are similar to the first switch circuit 110, the second switch circuit 120, the third switch circuit 143, the fourth switch circuit 144, and the substrate voltage switching circuit 145 in fig. 1A, respectively, so that the related description of fig. 1A can be referred to, and the description thereof is omitted.

The operational amplifier 530 of fig. 3A is similar to the operational amplifier 130 of fig. 1A, with the difference that the operational amplifier 530 further includes a feedback output stage 534. The feedback output stage 534 is coupled between the previous stage 133 and the second input terminal IT2 for generating a third output signal as the feedback signal AVF1 according to the amplified signal VAP. In the embodiment shown in fig. 3A, since the feedback signal AVF1 can be provided from the feedback output stage 534 to the second input terminal IT2, the first switch circuit 110 and the second switch circuit 120 can both be turned off, and the first output stage 131 and the second output stage 132 can both be disabled, so that the first output terminal OT1 and the second output terminal OT2 are both in a high impedance state, thereby implementing the application of the buffer circuit 500 providing a high impedance output. For details and operations of the operational amplifier 530 in fig. 3A, reference may be made to the above description of the operational amplifier 130 in fig. 1A, and further description thereof is omitted here.

Fig. 3B is a circuit diagram of a buffer circuit according to another embodiment of the invention. Please refer to fig. 3B. The buffer circuit 600 may include the first switch circuit 210, the second switch circuit 220, the operational amplifier 630, the third switch circuit 243, and the fourth switch circuit 244, but the present invention is not limited thereto. The first switch circuit 210, the second switch circuit 220, the third switch circuit 243, and the fourth switch circuit 244 in fig. 3B are respectively similar to the first switch circuit 210, the second switch circuit 220, the third switch circuit 243, and the fourth switch circuit 244 in fig. 1B, so that the related description of fig. 1B can be referred to, and the description thereof is omitted.

Operational amplifier 630 of fig. 3B is similar to operational amplifier 230 of fig. 1B, with the difference that operational amplifier 630 further includes a feedback output stage 634. The feedback output stage 634 is coupled between the previous stage 233 and the second input terminal IT4 for generating a third output signal as the feedback signal AVF2 according to the amplified signal VAN. In the embodiment shown in fig. 3B, since the feedback signal AVF2 can be provided from the feedback output stage 634 to the second input terminal IT4, the first switch circuit 210 and the second switch circuit 220 can both be turned off, and the first output stage 231 and the second output stage 232 can both be disabled, so that the first output terminal OT3 and the second output terminal OT4 are both in a high impedance state, thereby implementing the application of the buffer circuit 600 to provide a high impedance output. For details and operations of the operational amplifier 630 in fig. 3B, reference may be made to the above description of the operational amplifier 230 in fig. 1B, and further description is omitted here.

Referring to fig. 4A, fig. 4A is a circuit diagram of the operational amplifier shown in fig. 3A according to an embodiment of the invention. The operational amplifier 730 includes a pre-stage circuit 733, a first output stage 731, a second output stage 732, and a feedback output stage 734. The front-stage circuit 733 is similar to the front-stage circuit 333 in fig. 2A, so that the above description of fig. 2A can be referred to, and will not be repeated herein.

The first output stage 731 includes a switch circuit 731_1 and an output circuit 731_ 2. The output circuit 731_2 is similar to the output circuit 331_2 of fig. 2A, and therefore, reference can be made to the above description of fig. 2A, and further description thereof is omitted. In addition, compared to the switch circuit 331_1 of fig. 2A including the switches SW1A-SW5A, the switch circuit 731_1 includes only the switches SW1A, SW2A, SW4A and SW5A, wherein the coupling manner and operation of the switches SW1A, SW2A, SW4A and SW5A of fig. 4A are similar to the switches SW1A, SW2A, SW4A and SW5A of the switch circuit 331_1 of fig. 2A, so that the above-mentioned related description of fig. 2A can be referred to, and will not be repeated herein.

The second output stage 732 includes a switching circuit 732_1 and an output circuit 732_ 2. The output circuit 732_2 is similar to the output circuit 332_2 of fig. 2A, and therefore, reference may be made to the above description of fig. 2A, which is not repeated herein. In addition, compared to the switch circuit 332_1 in fig. 2A including the switches SW1B-SW5B, the switch circuit 732_1 includes only the switches SW1B, SW2B, SW4B and SW5B, wherein the coupling manners and operations of the switches SW1B, SW2B, SW4B and SW5B in fig. 4A are similar to those of the switches SW1B, SW2B, SW4B and SW5B in the switch circuit 332_1 in fig. 2A, so that the above-mentioned related description in fig. 2A can be referred to, and will not be repeated herein.

The feedback output stage 734 includes transistors P9 and N9. The first terminal of the transistor P9 is coupled to the positive voltage terminal PAVDD. The second terminal of the transistor P9 is coupled to the miller capacitors MCP and MCN and generates the third output signal as the feedback signal AVF 1. The control terminal of the transistor P9 receives the first sub-amplified signal SP. A first terminal of the transistor N9 is coupled to the miller capacitors MCP and MCN and generates a third output signal as the feedback signal AVF 1. The second terminal of the transistor N9 is coupled to the ground voltage terminal AGND. The control terminal of the transistor N9 receives the second sub-amplified signal SN.

Since the feedback signal AVF1 generated by the feedback output stage 734 in fig. 4A is provided to the control terminal of the transistor N1A of the first differential pair 211_1A and the control terminal of the transistor P1A of the second differential pair 211_1B to form a negative feedback loop, the operational amplifier 730 can still operate normally when the first output stage 731 and the second output stage 732 are both disabled. As a result, the first output stage 731 and the second output stage 732 can be disabled, such that the first output signal OUT1A and the second output signal OUT1B are both in a high impedance state, thereby providing a high impedance output.

Referring to fig. 4B, fig. 4B is a circuit diagram of the operational amplifier shown in fig. 3B according to an embodiment of the invention. The operational amplifier 830 includes a pre-stage 833, a first output stage 831, a second output stage 832, and a feedback output stage 834. The previous stage 833 is similar to the previous stage 433 of fig. 2B, so that the above description of fig. 2B can be referred to, and is not repeated herein.

The first output stage 831 includes a switch circuit 831_1 and an output circuit 831_ 2. The output circuit 831_2 is similar to the output circuit 431_2 of fig. 2B, and therefore, reference can be made to the above description of fig. 2B, and further description thereof is omitted. In addition, compared to the switch circuit 431_1 of fig. 2B including the switches SW1A-SW5A, the switch circuit 831_1 includes only the switches SW1A, SW2A, SW4A and SW5A, wherein the coupling manners and operations of the switches SW1A, SW2A, SW4A and SW5A of fig. 4B are similar to those of the switches SW1A, SW2A, SW4A and SW5A of the switch circuit 431_1 of fig. 2B, so that the above description of fig. 2B can be referred to, and will not be repeated herein.

The second output stage 832 includes a switch circuit 832_1 and an output circuit 832_ 2. The output circuit 832_2 is similar to the output circuit 432_2 of fig. 2B, and therefore, reference may be made to the above description of fig. 2B, which is not repeated herein. In addition, compared to the switch circuit 432_1 of fig. 2B including the switches SW1B-SW5B, the switch circuit 832_1 includes only the switches SW1B, SW2B, SW4B and SW5B, wherein the coupling manners and operations of the switches SW1B, SW2B, SW4B and SW5B of fig. 4B are similar to those of the switches SW1B, SW2B, SW4B and SW5B of the switch circuit 432_1 of fig. 2B, so that the above-mentioned related description of fig. 2B can be referred to, and will not be repeated herein.

Feedback output stage 834 includes transistors P9 and N9. The first terminal of the transistor P9 is coupled to the ground voltage terminal AGND. The second terminal of the transistor P9 is coupled to the miller capacitors MCP and MCN and generates the third output signal as the feedback signal AVF 2. The control terminal of the transistor P9 receives the first sub-amplified signal SP. A first terminal of the transistor N9 is coupled to the miller capacitors MCP and MCN and generates a third output signal as the feedback signal AVF 2. The second terminal of the transistor N9 is coupled to the negative voltage terminal NAVDD. The control terminal of the transistor N9 receives the second sub-amplified signal SN.

Since the feedback signal AVF2 generated by the feedback output stage 834 of fig. 4B is provided to the control terminal of the transistor N1A of the first differential pair 211_1A and the control terminal of the transistor P1A of the second differential pair 211_1B to form a negative feedback loop, the operational amplifier 830 can still operate normally when the first output stage 831 and the second output stage 832 are both disabled. In this way, the first output stage 831 and the second output stage 832 can be disabled, so that the first output signal OUT2A and the second output signal OUT2B are both in a high impedance state, thereby achieving the application of providing high impedance output.

In summary, in the buffer circuit provided in the embodiments of the present invention, the first output stage of the operational amplifier is only used for driving one load, and the second output stage of the operational amplifier is only used for driving another load, so that compared to the conventional buffer circuit in which the same output stage is used for alternately driving different loads by switching the transmission gates, the transmission gate for switching the polarity of the driving voltage can be omitted between the operational amplifier and the load in the embodiment, which not only reduces the circuit area of the buffer circuit, but also effectively increases the slew rate of the output signal of the buffer circuit, thereby increasing the driving capability of the buffer circuit.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A buffer circuit, comprising:

an operational amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the operational amplifier comprises:

a front stage circuit coupled to the first input terminal for receiving an input signal, coupled to the second input terminal for receiving a feedback signal, and generating an amplified signal;

the first output stage is coupled between the preceding stage circuit and the first output end and used for generating a first output signal according to the amplified signal so as to drive a first load; and

a second output stage coupled between the pre-stage circuit and the second output terminal for generating a second output signal according to the amplified signal to drive a second load, wherein the polarity of the second output signal is the same as the polarity of the first output signal;

a first switch circuit coupled between the first output terminal and the second input terminal for transmitting the first output signal to the second input terminal as the feedback signal when being turned on; and

a second switch circuit coupled between the second output terminal and the second input terminal for transmitting the second output signal to the second input terminal as the feedback signal when being turned on;

wherein when the first switch circuit is turned on and the first output stage generates the first output signal to drive the first load, the second switch circuit is turned off and the second output stage is disabled; and when the second switch circuit is turned on and the second output stage generates the second output signal to drive the second load, the first switch circuit is turned off and the first output stage is disabled, at least one of the two.

2. The buffer circuit of claim 1,

the first output stage includes:

a third switch circuit coupled to the preceding stage circuit and turning on or off the first signal transmission channel according to a first selection signal; and

a first output circuit coupled to the third switch circuit for receiving the amplified signal via the first signal transmission channel and generating the first output signal according to the amplified signal,

the second output stage includes:

a fourth switch circuit coupled to the pre-stage circuit and turning on or off the second signal transmission channel according to a second selection signal; and

and the second output circuit is coupled with the fourth switch circuit, receives the amplified signal through the second signal transmission channel and generates the second output signal according to the amplified signal.

3. The buffer circuit of claim 2, wherein the third switch circuit comprises:

the first switch receives a first sub-amplification signal in the amplification signals, is controlled by the first selection signal, and transmits the first sub-amplification signal to the first output circuit when the first switch is switched on;

the second switch receives a second sub-amplification signal in the amplification signals, is controlled by the first selection signal, and transmits the second sub-amplification signal to the first output circuit when the second switch is switched on; and

a third switch coupled between the output terminal of the first output circuit and the miller capacitance of the preceding stage circuit and turned on or off according to the first selection signal,

wherein the on-off states of the first switch, the second switch, and the third switch are the same.

4. The buffer circuit of claim 3, wherein the third switch circuit further comprises:

a fourth switch coupled between the first input terminal of the first output circuit and the first voltage terminal, and turned on or off according to the first selection signal; and

a fifth switch coupled between the second input terminal of the first output circuit and the second voltage terminal and turned on or off according to the first selection signal,

wherein the fourth switch has the same on-off state as the fifth switch, the fourth switch has the opposite on-off state as the first switch, and the fifth switch has the opposite on-off state as the second switch,

wherein the first voltage terminal is a positive voltage terminal and the second voltage terminal is a ground voltage terminal; alternatively, the first voltage terminal is a ground voltage terminal, and the second voltage terminal is a negative voltage terminal.

5. The buffer circuit of claim 2, wherein the fourth switching circuit comprises:

the first switch receives a first sub-amplification signal in the amplification signals, is controlled by the second selection signal, and transmits the first sub-amplification signal to the second output circuit when the first switch is switched on;

the second switch receives a second sub-amplification signal in the amplification signals, is controlled by the second selection signal, and transmits the second sub-amplification signal to the second output circuit when the second switch is switched on; and

a third switch coupled between the output terminal of the second output circuit and the miller capacitance of the preceding stage circuit and turned on or off according to the second selection signal,

wherein the first switch, the second switch and the third switch have the same on-off state.

6. The buffer circuit of claim 5, wherein the fourth switching circuit further comprises:

a fourth switch coupled between the first input terminal of the second output circuit and the first voltage terminal, and turned on or off according to the second selection signal; and

a fifth switch coupled between the second input terminal of the second output circuit and the second voltage terminal and turned on or off according to the second selection signal,

7. The buffer circuit of claim 2, wherein the operational amplifier further comprises:

the feedback output stage is coupled between the pre-stage circuit and the second input terminal, and is used for generating a third output signal as the feedback signal according to the amplified signal.

8. The buffer circuit of claim 7, wherein the feedback output stage comprises:

a first transistor, a first terminal of which is coupled to a first voltage terminal, a second terminal of which is coupled to the miller capacitor of the previous stage circuit and generates the third output signal, and a control terminal of which receives a first sub-amplified signal of the amplified signals; and

a second transistor, a first terminal of the second transistor being coupled to the miller capacitor and generating the third output signal, a second terminal of the second transistor being coupled to a second voltage terminal, and a control terminal of the second transistor receiving a second sub-amplified signal of the amplified signals,

9. The buffer circuit of claim 8, wherein the third switch circuit comprises:

the first switch receives the first sub-amplification signal, is controlled by the first selection signal, and transmits the first sub-amplification signal to the first output circuit when the first switch is switched on; and

the second switch receives a second sub-amplification signal in the amplification signals, is controlled by the first selection signal, and transmits the second sub-amplification signal to the first output circuit when the second switch is switched on;

wherein the first switch and the second switch have the same on-off state.

10. The buffer circuit of claim 9, wherein the third switch circuit further comprises:

a third switch coupled between the first input terminal of the first output circuit and the first voltage terminal, and turned on or off according to the first selection signal; and

a fourth switch coupled between the second input terminal of the first output circuit and the second voltage terminal and turned on or off according to the first selection signal,

wherein the third switch and the fourth switch have the same on-off state, the third switch has the opposite on-off state to that of the first switch, and the fourth switch has the opposite on-off state to that of the second switch.

11. The buffer circuit of claim 8, wherein the fourth switching circuit comprises:

the first switch receives the first sub-amplification signal, is controlled by the second selection signal, and transmits the first sub-amplification signal to the second output circuit when the first switch is switched on; and

a second switch for receiving the second sub-amplified signal, controlled by the second selection signal, and transmitting the second sub-amplified signal to the second output circuit when the second switch is turned on,

wherein the first switch and the second switch have the same on-off state.

12. The buffer circuit of claim 11, wherein the fourth switching circuit further comprises:

a third switch coupled between the first input terminal of the second output circuit and the first voltage terminal, and turned on or off according to the second selection signal; and

a fourth switch coupled between the second input terminal of the second output circuit and the second voltage terminal and turned on or off according to the second selection signal,

13. The buffer circuit of claim 1, further comprising:

a third switch circuit coupled between the first output terminal and the first load for transmitting the first output signal to the first load when the third switch circuit is turned on; and

a fourth switch circuit coupled between the second output terminal and the second load, for transmitting the second output signal to the second load when the fourth switch circuit is turned on.

14. The buffer circuit of claim 13,

the third switching circuit includes:

a first ground switch coupled between the first output terminal and a ground voltage terminal; and

a first transmission gate coupled between the first output terminal and the first load, wherein the first grounding switch and the first transmission gate are opposite in conduction and disconnection states,

the fourth switching circuit includes:

a second ground switch coupled between the second output terminal and the ground voltage terminal; and

a second transmission gate coupled between the second output terminal and the second load, wherein the second grounding switch and the second transmission gate have opposite conduction and disconnection states.

15. The buffer circuit of claim 14, wherein:

the first transmission gate includes:

a first P-type transistor, wherein a first terminal of the first P-type transistor is coupled to the first output terminal, a second terminal of the first P-type transistor is coupled to the first load, and a control terminal of the first P-type transistor is coupled to the ground voltage terminal; and

a first N-type transistor, a first end of the first N-type transistor being coupled to the first output end, a second end of the first N-type transistor being coupled to the first load, and a control end of the first N-type transistor receiving a control voltage,

the second transmission gate includes:

a second P-type transistor, wherein a first terminal of the second P-type transistor is coupled to the second output terminal, a second terminal of the second P-type transistor is coupled to the second load, and a control terminal of the second P-type transistor is coupled to the ground voltage terminal; and

a second N-type transistor, wherein a first end of the second N-type transistor is coupled to the second output terminal, a second end of the second N-type transistor is coupled to the second load, and a control terminal of the second N-type transistor receives the inverted control voltage.

16. The buffer circuit of claim 15, further comprising:

a substrate voltage switching circuit comprising:

a third P-type transistor, a first terminal of which is coupled to the positive voltage terminal, a control terminal of which receives the first switching signal, and a second terminal of which provides a substrate voltage of the first P-type transistor;

a third N-type transistor, wherein a first terminal of the third N-type transistor is coupled to the ground voltage terminal, a control terminal of the third N-type transistor receives a second switching signal, and a second terminal of the third N-type transistor provides the substrate voltage of the first P-type transistor;

a fourth P-type transistor, a first terminal of which is coupled to the ground voltage terminal, a control terminal of which receives a third switching signal, and a second terminal of which provides a substrate voltage of the first N-type transistor;

a fourth N-type transistor, wherein a first terminal of the fourth N-type transistor is coupled to the negative voltage terminal, a control terminal of the fourth N-type transistor receives a fourth switching signal, and a second terminal of the fourth N-type transistor provides the substrate voltage of the first N-type transistor;

a fifth P-type transistor, wherein a first terminal of the fifth P-type transistor is coupled to the positive voltage terminal, a control terminal of the fifth P-type transistor receives a fifth switching signal, and a second terminal of the fifth P-type transistor provides a substrate voltage of the second P-type transistor;

a fifth N-type transistor, wherein a first terminal of the fifth N-type transistor is coupled to the ground voltage terminal, a control terminal of the fifth N-type transistor receives a sixth switching signal, and a second terminal of the fifth N-type transistor provides the substrate voltage of the second P-type transistor;

a sixth P-type transistor, wherein a first terminal of the sixth P-type transistor is coupled to the ground voltage terminal, a control terminal of the sixth P-type transistor receives a seventh switching signal, and a second terminal of the sixth P-type transistor provides a substrate voltage of the second N-type transistor; and

a sixth N-type transistor, wherein a first terminal of the sixth N-type transistor is coupled to the negative voltage terminal, a control terminal of the sixth N-type transistor receives an eighth switching signal, and a second terminal of the sixth N-type transistor provides the substrate voltage of the second N-type transistor.