CN109858628A - Compile method, apparatus, equipment and the computer readable storage medium of quantum circuit - Google Patents
Compile method, apparatus, equipment and the computer readable storage medium of quantum circuit Download PDFInfo
- Publication number
- CN109858628A CN109858628A CN201910153013.5A CN201910153013A CN109858628A CN 109858628 A CN109858628 A CN 109858628A CN 201910153013 A CN201910153013 A CN 201910153013A CN 109858628 A CN109858628 A CN 109858628A
- Authority
- CN
- China
- Prior art keywords
- quantum
- bit
- circuit
- door
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Embodiment of the disclosure is related to compiling method, apparatus, equipment and the computer program product of quantum circuit.This method comprises: obtaining the logical order to be compiled for being used for quantum circuit, quantum circuit includes multiple quantum bits, logical order in multiple quantum bits the first quantum bit and the second quantum bit it is associated, dibit quantum door is able to use between at least part in the multiple quantum bit and is operated；The path between the first quantum bit and the second quantum bit is being determined in quantum circuit；And it is based on path, the bottom for the quantum circuit corresponding with logical order is generated by addition single-bit quantum door to be instructed.
Description
Technical field
Embodiment of the disclosure is related to quantum calculation, and more particularly relates to the method for compiling quantum circuit, sets
Standby and computer readable storage medium.
Background technique
Currently, the topology of most of Superconducting Quantum computer is non-strongly connected graph structure, which limits the use of hardware,
It is difficult or cannot reach Universal Quantum calculating.Universal Quantum calculating requires can be any (mutual between any two quantum bit
Phase) connection.In other words, it gives(the wherein space where Universal Quantum task used in U expression calculating, 2nIndicating should
The size in space, n are quantum bit number), it can be broken into single-bit U2With the group of the sequence of controlled not-gate (CNOT) door
It closes.Therefore, in addition to requiring each quantum bit to can carry out arbitrary U2In addition, also require any two quantum bit can be with
Execute CNOT operation.Therefore, to achieve the purpose that Universal Quantum calculates, any two quantum bit can be connected to, that is, entire
Quantum hardware circuit is needed with strongly connected graph topology.However, current manufacturing process, can not produce qualified (fidelity
It is higher) the quantum hardware of strongly connected graph topology is mostly the quantum hardware that topology is connected graph.
Summary of the invention
In accordance with an embodiment of the present disclosure, it provides a kind of for compiling the scheme of quantum circuit.
In the disclosure in a first aspect, providing a kind of method for compiling quantum circuit.It is used this method comprises: obtaining
In the logical order to be compiled of quantum circuit, quantum circuit includes multiple quantum bits, logical order and multiple quantum bits
In the first quantum bit and the second quantum bit it is associated, can make between at least part in the multiple quantum bit
It is operated with dibit quantum door；The path between the first quantum bit and the second quantum bit is being determined in quantum circuit；
And it is based on path, referred to by addition single-bit quantum door to generate the bottom for quantum circuit corresponding with logical order
It enables.
It in the second aspect of the disclosure, provides a kind of for compiling the device of quantum circuit, comprising: logical order obtains
Module is configured as obtaining the logical order to be compiled for being used for quantum circuit, and quantum circuit includes multiple quantum bits, logic
Instruct in multiple quantum bits the first quantum bit and the second quantum bit it is associated, in the multiple quantum bit extremely
Dibit quantum door is able to use between few a part to be operated；Path determination module is configured as in quantum circuit really
Path between fixed first quantum bit and the second quantum bit；And bottom directive generation module, it is configured as based on path,
The bottom for quantum circuit corresponding with logical order is generated by addition single-bit quantum door to instruct.
In the third aspect of the disclosure, a kind of electronic equipment is provided.The electronic equipment includes: one or more processing
Device；And memory, for storing one or more programs, when one or more programs are executed by one or more processors,
So that the method that electronic equipment realizes the first aspect according to the disclosure.
In the fourth aspect of the disclosure, a kind of computer-readable medium is provided, computer program is stored thereon with, the journey
The method of the first aspect according to the disclosure is realized when sequence is executed by processor.
There is provided Summary is their below specific in order to introduce the selection to concept in simplified form
It will be further described in embodiment.Summary be not intended to identify the disclosure key feature or main feature, also without
Meaning limits the scope of the present disclosure.
Detailed description of the invention
Disclosure exemplary embodiment is described in more detail in conjunction with the accompanying drawings, the disclosure above-mentioned and other
Purpose, feature and advantage will be apparent, wherein in disclosure exemplary embodiment, identical reference label is usual
Represent same parts.
Fig. 1 is shown can be in the schematic diagram for the example computing device for wherein realizing embodiment of the disclosure；
Fig. 2 shows the schematic diagrames according to the topological structure of the quantum circuits of some embodiments of the present disclosure；
Fig. 3 shows the flow chart of the method for compiling quantum circuit according to some embodiments of the present disclosure；
Fig. 4 shows the schematic diagram of the topological structure of the quantum circuit according to some embodiments of the present disclosure；
Fig. 5 shows the schematic diagram of the swap gate according to some embodiments of the present disclosure；
Fig. 6 shows the example implementation of the swap gate according to some embodiments of the present disclosure；
Fig. 7 shows the example implementation of the swap gate according to some embodiments of the present disclosure；
Fig. 8 shows the block diagram of the device for compiling quantum circuit according to some embodiments of the present disclosure；And
Fig. 9 shows the block diagram that can implement the electronic equipment of some embodiments of the present disclosure.
Specific embodiment
Preferred embodiment of the present disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Preferred embodiment, however, it is to be appreciated that may be realized in various forms the disclosure without that should be limited by embodiments set forth here
System.On the contrary, thesing embodiments are provided so that the disclosure is more thorough and complete, and can be complete by the scope of the present disclosure
Ground is communicated to those skilled in the art.
Terminology used in this article " comprising " and its deformation indicate that opening includes, i.e., " including but not limited to ".Unless
Especially statement, term "or" indicate "and/or".Term "based" indicates " being based at least partially on ".Term " implemented by an example
Example " and " one embodiment " expression " at least one example embodiment "." at least one is other for term " another embodiment " expression
Embodiment ".Term " first ", " second " etc. may refer to different or identical object.Hereafter it is also possible that other are bright
True and implicit definition.
Fig. 1 is shown can be in the schematic diagram for the example computing device 100 for wherein realizing embodiment of the disclosure.Such as Fig. 1
Shown, calculating environment 100 includes classic computer 102, for example, classic computer 102 can be realized by deterministic Turng machine
Calculating equipment.It will be appreciated, however, that classic computer 102 can also be with the calculating equipment of any other suitable type.
As shown in Figure 1, calculating environment 100 includes quantum circuit 106, it is referred to as quantum processor etc..For example, quantum
Circuit 106 can be Superconducting Quantum circuit, be also possible to nuclear magnetic resonance circuit, nuclear magnetic resonance circuit, ion sink circuit and silicon substrate
Semiconductor quantum circuit or the combination of wherein one or more etc..It should be appreciated that embodiment of the disclosure also can be applied to
The specific physics realization of any other existing or exploitation in the future suitable quantum circuit, the disclosure are unrestricted herein.
Quantum circuit 106 can have non-strong full-mesh topology, it is possible to have strong full-mesh topology.Classic computer
102 include compiler 104, for being compiled to quantum circuit 106.Logical order can be converted to bottom by compiler 104
Layer instruction, to be supplied to quantum processor.The bottom received can be instructed and be converted to Physical instruction by quantum processor, with behaviour
Vertical quantum circuit 106.
Fig. 1 is combined to describe example computing device 100 above, it being understood, however, that embodiment of the disclosure can also be
It is realized in other any suitable calculating environment 100.For example, embodiment of the disclosure can also be realized in scale sub-circuit.
As described above, current quantum circuit is difficult to realize strong continune topology.In quantum circuit, CNOT can be in conjunction with Kazakhstan
Da Mamen (HGate) overturns local connectivity structure.Select two quantum bits being connected to, with CNOT and HGate come
The full-mesh structure for constructing part, to complete target CNOT.However, this mode is all by manually choosing corresponding amount
Sub- bit executes turning operation.In addition, this mode is also unable to reach the minimum target of cost, preferable fidelity can not be obtained
Degree.For example, cost indicates the number of gate circuit.It is available can only to ensure part by artificial selection quantum bit, and can not carry out
Overall situation selection.In the slightly larger quantum circuit of scale (more than 3 quantum bits), it can not complete by hand substantially whole in real time
The mapping of body.
Fig. 2 shows the schematic diagrames according to the quantum circuits 200 of some embodiments of the present disclosure.In order to illustrate more clearly of
The above problem is described in detail below in conjunction with the quantum circuit 200 of Fig. 2.It should be appreciated that the topological structure only conduct of Fig. 2
Example provides, and the principle of the disclosure and design also can be applied to any other suitable quantum circuit or quantum processor, this
Tittle sub-processor can have more or less quantum bits, and can have entirely different topological structure.
Quantum circuit 200 includes five quantum bit q0-q4 and six double ratios that five quantum bits are coupled to each other
Special topological structure, dibit quantum door can only act on the quantum bit with dibit topological structure.For example, dibit amount
Cervical orifice of uterus can be CNOT.For simplicity, it is described below in conjunction with CNOT.It will be appreciated, however, that the principle of the disclosure and
Design also can be applied to any suitable dibit quantum door being currently known or developing in the future.
Quantum circuit 200 has non-strongly connected graph structure, wherein not being that any two quantum bit can be connected to.Example
Such as, quantum circuit 200 can be Superconducting Quantum circuit, nuclear magnetic resonance circuit, ion sink circuit and/or silicon-based semiconductor quantum electricity
Road etc..
As shown in Fig. 2, arrow indicates oriented interaction, wherein the direction of arrow indicates control direction, the head of arrow
Portion indicates target quantum bit, and the tail portion of arrow indicates control quantum bit.For example, q2 can control q1, and q1 can not
Control q2.Therefore, when realizing CNOT (q1, q2), ideal circuit can be compiled into corresponding real circuits, as shown in table 1.
Since Hadamard door can be used to overturn the direction of CNOT gate, real circuits shown in table 1 may be implemented CNOT (q1,
q2).In this way, CNOT can invert local connectivity structure in conjunction with Hadamard door, to construct local full-mesh
Structure.
Table 1
However, realizing ideal circuit without method well for slightly more complex Quantum Topological logic circuit
With the automatic mapping of real circuits, also general computational tasks can not be completed under the limitation of CNOT and single-bit quantum door.
For example, if necessary to realize CNOT (q0, q3), then mode shown in table 2 can be used in quantum circuit 200
To realize.As shown in table 2, q3 and q2 are swapped first, then, then the direction between q2 and q0 is overturn, to realize q0
Control to q3.
Table 2
However, the compiler cost with higher of Compilation Method shown in table 2, and need the corresponding quantum ratio of artificial selection
Spy executes turning operation.Based on this, embodiment of the disclosure, which provides, a kind of at least is partially solved above technical problem
Realize the Compilation Method of general-purpose computations.
Fig. 3 shows the flow chart of the method 300 for compiling quantum circuit according to some embodiments of the present disclosure.Example
Such as, it is realized at the example computing device 100 that method 300 can be shown in Fig. 1, especially compiler 104.It will be appreciated, however, that
Method 300 can also be realized in any other suitable calculates in environment.
In frame 302, the logical order to be compiled for being used for quantum circuit 106 or 200 is obtained.Quantum circuit includes multiple amounts
Sub- bit.Logical order in multiple quantum bits the first quantum bit and the second quantum bit it is associated.The multiple amount
Dibit quantum door is able to use between at least part in sub- bit to be operated.First quantum bit is referred to as controlling
Bit processed, and the second quantum bit is referred to as target bits.As described above, quantum circuit 200 can have non-Qiang Lian
Logical topology, it is possible to have strong continune topology, and for example can be Superconducting Quantum circuit, nuclear magnetic resonance circuit, ion trap electricity
Road and/or silicon-based semiconductor quantum circuit etc..
In some embodiments, dibit quantum door can be CNOT gate, and logical order may include by the first quantum ratio
The CNOT gate of spy's the second quantum bit of control.For example, logical order can be CNOT (q0, q3), wherein the first quantum bit is
Q0, the second quantum bit are q3.
It will be appreciated that though being described here mainly in combination with CNOT gate, dibit quantum door is also possible at present
Any other suitable dibit quantum door know or exploitation in the future, and can be uncontrolled type dibit quantum door.
In frame 304, the path between the first quantum bit and the second quantum bit is being determined in quantum circuit 106 or 200.
For example, the path can be the shortest path between two quantum bits, to provide better fidelity.It can be by current
Known or exploitation in the future any suitable algorithm calculates shortest path.For example, Di Jiesitela can be passed through
(Dijkstra) algorithm calculates shortest path.
In some embodiments, it can be indicated by the figure of quantum circuit 106 or 200 to determine between two quantum bits
Path.For example, the available figure for indicating quantum circuit 200.Node in figure indicates the quantum ratio in quantum circuit 200
Spy, and the side in figure indicates dibit quantum door.It is, for example, possible to use digraph as shown in Figure 2, the wherein direction table on side
Show the control direction of CNOT.Alternatively, non-directed graph also can be used.
For example, in figure shown in Fig. 2, can determine will indicate the first node of the first quantum bit (for example, q0) with
Indicate the side that the second node of the second quantum bit (for example, q3) links together.These sides correspond to two quantum bits it
Between path.For example, the path can be q0-> q2-> q3, q0-> q2-> q4-> q3 etc..
In some embodiments, the length in path can be indicated by the number on side, so that shortest path is with minimum
Side path.For example, path q0-> q2-> q3 is more shorter than path q0-> q2-> q4-> q3.
In other embodiments, the length in path also considers the direction on side.For example, if including in a path
At least one positive side, then can subtract one for the length in the path.For example, path q0-> q2-> q4-> q3 contains one
Positive side q2-> q4, so the length is 3-1=2, with path q0-> q2-> q3 length having the same.Table 3 and table 4 divide
The compiling result corresponding to the two paths is not shown.As can be seen that two paths have essentially identical cost, and phase
It is lower for compiling result cost shown in table 2.Due to not including positive side in path q0-> q2-> q3, need to exchange q0
To q3.Since path q0-> q2-> q4-> q3 includes positive side, then can exchange less primary.
Table 3
Table 4
In some embodiments, figure can be weighted graph, and wherein each side in weighted graph has corresponding weight.With this
Kind mode, can calculate the weight in path based on the weight on each side in path.For example, the number of edges for including by path multiplied by
The weight on each side calculates the weight in path.For example, since exchange (SWAP) door can be realized by 7 doors,
The weight on each side can be set to 7.The weight in one path can subtract 6 after the weight on each side and obtain.This
It is because the last one quantum bit does not need to exchange.The weight in path can indicate the path fidelity how.For example, such as
The weighted value in one path of fruit is excessively high, then illustrates that this path has excessively high cost, have lower fidelity.
For example, weighted graph can be constructed by way of table.For example, the weight between two quantum bits of connection can
To be arranged to 7, the weight between disconnected two quantum bits is set as infinitely great (inf).It has been shown in table 5 such as figure
The connection table of quantum circuit 200 shown in 2.
Table 5
| q0 | q1 | q2 | q3 | q4 | |
| q0 | inf | 7 | 7 | inf | inf |
| q1 | 7 | inf | 7 | inf | Inf |
| q2 | 7 | 7 | inf | 7 | 7 |
| q3 | inf | inf | 7 | inf | 7 |
| q4 | inf | inf | 7 | 7 | inf |
For example, can be determined by various suitable algorithms from the first quantum bit to the road the second quantum bit
Diameter, especially shortest path.It is, for example, possible to use dijkstra's algorithms to be calculated.In calculating process, it may be considered that example
Such as the weight in path as shown in table 5.
A path tree or shortest path tree can be generated by dijkstra's algorithm, path tree is calculating starting point to eventually
During stop shortest path, the shortest path of other all points is also calculated.For example, can be by these shortest paths
It saves in both the buffers.During compiling, shortest path can be determined by way of query caching.For example, if
Include corresponding path in buffer, then path can be directly read from buffer, without being computed repeatedly.If slow
Do not include corresponding path in storage, then calculates starting point to the shortest path between terminating point.Therefore, dijkstra's algorithm can
Greatly to compress the number computed repeatedly.
In frame 306, it is based on path, by addition single-bit quantum pupil at corresponding with logical order for quantum electricity
The bottom on road instructs.Bottom instruction can be used for controlling corresponding quantum circuit.Since single-bit quantum door is easy to accomplish, thus
Too many complexity is not will increase to quantum circuit.
It will be appreciated that though the disclosure is described in current quantum circuit compilation process based on non-strong full-mesh topology
Some technical problems, embodiment of the disclosure also can be applied to strong full-mesh topology.It applies in embodiment of the disclosure strong
When in full-mesh topology, the calculating of weight can be no longer carried out.
Fig. 4 is shown according to some embodiments of the present disclosure by adding to quantum circuit 200 by single-bit quantum door
(such as Hadamard door) and realize quantum circuit 400.In quantum circuit 400, due to being realized by adding Hadamard door
Swap gate, not only quantum bit q3 can control quantum bit q2, and quantum bit q2 also can control quantum bit q3.Scheming
In 4, these Reverse Turning Controls realized by supplementing Hadamard door are shown by a dotted line.
In some embodiments, swap gate corresponding with the path can be determined, so that by using in the path
One dibit quantum door operates the first quantum bit and the second quantum bit.For example, in compiling result as shown in table 3
In, q0 is exchanged to the position of q3, and q3 has been exchanged to the position of q2.Therefore, q0 can be controlled by a CNOT
q3。
Swap gate can be realized by dibit quantum door and single-bit quantum door.For example, swap gate can pass through
CNOT and Hadamard door are realized.For example, Fig. 5 shows the circuit structure of swap gate SWAP (a, b).SWAP (a, b) includes three
The control direction having the same a alternate CNOT, the CNOT of both ends of them, and there is opposite control with intermediate CNOT
Direction.Due to physically between two quantum bits only one direction CNOT, it is therefore desirable to by a CNOT by turning over
The mode turned is turned on another direction.
Fig. 6 shows the example implementation of the swap gate according to some embodiments of the present disclosure, wherein since there is only CNOT
(a, b), quantum bit a can control quantum bit b, and quantum bit b cannot control quantum bit a.Correspondingly, Fig. 7 is shown
According to the example implementation of the swap gate of some embodiments of the present disclosure, wherein since there is only CNOT, (b, a), quantum bit a is not
It can control quantum bit b, quantum bit b can control quantum bit a.
Hence, it can be determined that the sequence of dibit quantum door corresponding with swap gate and single-bit quantum door, and be based on
This sequence instructs to generate bottom corresponding with logical order.
Fig. 8 shows the block diagram of the device 500 for compiling quantum circuit according to some embodiments of the present disclosure.Example
Such as, device 500 can compiler 104 as shown in Figure 1 realize.For example, quantum circuit can have non-strong continune topology or
Person's strong continune topology, and may include Superconducting Quantum circuit, nuclear magnetic resonance circuit, ion sink circuit and/or silicon-based semiconductor
Quantum circuit etc..
As shown in figure 8, device 500 includes that logical order obtains module 502, it is configured as obtaining for the quantum electricity
The logical order to be compiled on road, quantum circuit include multiple quantum bits, and first in logical order and multiple quantum bits
Quantum bit and the second quantum bit are associated.Dibit is able to use between at least part in the multiple quantum bit
Quantum door is operated.
Device 500 further includes path determination module 504, be configured as in quantum circuit determine the first quantum bit and
Path between second quantum bit.
Device 500 further includes bottom directive generation module 506, is configured as based on path, by adding single-bit amount
Cervical orifice of uterus instructs to generate the bottom for quantum circuit corresponding with logical order.
In some embodiments, bottom directive generation module 506 includes: swap gate determining module, be configured to determine that with
The corresponding swap gate in path so that operated by using a dibit quantum door in the paths the first quantum bit and
Second quantum bit；Sequence determining module is configured to determine that dibit quantum door corresponding with swap gate and single-bit quantum
The sequence of door；And bottom instruction generates submodule, is configured as the sequence based on dibit quantum door and single-bit quantum door
To generate bottom instruction.
In some embodiments, path determination module 504 includes shortest path determining module, is configured to determine that first
Shortest path between quantum bit and the second quantum bit.
In some embodiments, shortest path determining module includes: shortest path read module, is configured to respond to really
Determine to include the shortest path tree using first quantum bit as starting point in buffer, reading is described most from the buffer
Short path.
In some embodiments, shortest path determining module includes: shortest path tree computing module, is configured to respond to
Determine do not include shortest path tree using first quantum bit as starting point in buffer, by dijkstra's algorithm come really
The fixed shortest path tree；Shortest path tree memory module is configured as saving the shortest path tree in both the buffers；With
And shortest path determines submodule, is configured as determining the shortest path based on the shortest path tree.
In some embodiments, dibit quantum door is CNOT gate, and single-bit quantum door is Hadamard door, and is patrolled
Collecting instruction includes the CNOT gate that the second quantum bit is controlled by the first quantum bit.
In some embodiments, device 500 further includes that figure obtains module, is configured as obtaining the figure for indicating quantum circuit,
Node in figure indicates the quantum bit in quantum circuit, and the side in figure indicates dibit quantum door.
In some embodiments, path determination module 504 includes: side determining module, and first will be indicated by being configured to determine that
The side that the second node of the second quantum bit of first node and expression of quantum bit links together.
In some embodiments, figure includes weighted graph, and the side in weighted graph has corresponding weight.
In some embodiments, device 500 further includes weight determination module, is configured as based on each side in path
Weight calculates the weight in path.
Fig. 9 shows the schematic block diagram that can be used to implement the equipment 600 of embodiment of the disclosure.Such as Fig. 1 institute
The classic computer 102 and device 500 as shown in Figure 8 shown can be realized by equipment 600.As shown in figure 9, equipment 600
It, can be according to the computer program instructions being stored in read-only memory (ROM) 602 including central processing unit (CPU) 601
Or the computer program instructions in random access storage device (RAM) 603 are loaded into from storage unit 608, it is various suitable to execute
When movement and processing.In RAM 603, it can also store equipment 600 and operate required various programs and data.CPU 601,
ROM 602 and RAM 603 is connected with each other by bus 604.Input/output (I/O) interface 605 is also connected to bus 604.
Multiple components in equipment 600 are connected to I/O interface 605, comprising: input unit 606, such as keyboard, mouse etc.；
Output unit 607, such as various types of displays, loudspeaker etc.；Storage unit 608, such as disk, CD etc.；And it is logical
Believe unit 609, such as network interface card, modem, wireless communication transceiver etc..Communication unit 609 allows equipment 600 by such as
The computer network of internet and/or various telecommunication networks exchange information/data with other equipment.
Each process as described above and processing, such as method 300 can be executed by processing unit 601.For example, one
In a little embodiments, method 300 can be implemented as computer software programs, be tangibly embodied in machine readable media, such as
Storage unit 608.In some embodiments, some or all of of computer program can be via ROM 602 and/or communication unit
Member 609 and be loaded into and/or be installed in equipment 600.When computer program is loaded into RAM 603 and is executed by CPU 601
When, the one or more steps of method as described above 300 can be executed.Alternatively, in other embodiments, CPU 601 can
By by other it is any it is appropriate in a manner of (for example, by means of firmware) be configured as execution method 300.
As described above, requirement of the buffer significant decrease to calculation amount can be used in combination in dijkstra's algorithm.Buffer
Can by be comprised in or directly using one in ROM602, RAM 603 or storage unit 608 as shown in Figure 9 or
Multiple to realize, the disclosure is unrestricted herein.
The disclosure can be method, equipment, system and/or computer program product.Computer program product may include
Computer readable storage medium, containing the computer-readable program instructions for executing various aspects of the disclosure.
Computer readable storage medium, which can be, can keep and store the tangible of the instruction used by instruction execution equipment
Equipment.Computer readable storage medium for example can be-- but it is not limited to-- storage device electric, magnetic storage apparatus, optical storage
Equipment, electric magnetic storage apparatus, semiconductor memory apparatus or above-mentioned any appropriate combination.Computer readable storage medium
More specific example (non exhaustive list) includes: portable computer diskette, hard disk, random access memory (RAM), read-only deposits
It is reservoir (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable
Compact disk read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical coding equipment, for example thereon
It is stored with punch card or groove internal projection structure and the above-mentioned any appropriate combination of instruction.Calculating used herein above
Machine readable storage medium storing program for executing is not interpreted that instantaneous signal itself, the electromagnetic wave of such as radio wave or other Free propagations lead to
It crosses the electromagnetic wave (for example, the light pulse for passing through fiber optic cables) of waveguide or the propagation of other transmission mediums or is transmitted by electric wire
Electric signal.
Computer-readable program instructions as described herein can be downloaded to from computer readable storage medium it is each calculate/
Processing equipment, or outer computer or outer is downloaded to by network, such as internet, local area network, wide area network and/or wireless network
Portion stores equipment.Network may include copper transmission cable, optical fiber transmission, wireless transmission, router, firewall, interchanger, gateway
Computer and/or Edge Server.Adapter or network interface in each calculating/processing equipment are received from network to be counted
Calculation machine readable program instructions, and the computer-readable program instructions are forwarded, for the meter being stored in each calculating/processing equipment
In calculation machine readable storage medium storing program for executing.
Computer program instructions for executing disclosure operation can be assembly instruction, instruction set architecture (ISA) instructs,
Machine instruction, machine-dependent instructions, microcode, firmware instructions, condition setup data or with one or more programming languages
The source code or object code that any combination is write, the programming language include the programming language-of object-oriented such as
Smalltalk, C++ etc., and conventional procedural programming languages-such as " C " language or similar programming language.Computer
Readable program instructions can be executed fully on the user computer, partly execute on the user computer, be only as one
Vertical software package executes, part executes on the remote computer or completely in remote computer on the user computer for part
Or it is executed on server.In situations involving remote computers, remote computer can pass through network-packet of any kind
It includes local area network (LAN) or wide area network (WAN)-is connected to subscriber computer, or, it may be connected to outer computer (such as benefit
It is connected with ISP by internet).In some embodiments, by utilizing computer-readable program instructions
Status information carry out personalized customization electronic circuit, such as programmable logic circuit, field programmable gate array (FPGA) or can
Programmed logic array (PLA) (PLA), the electronic circuit can execute computer-readable program instructions, to realize each side of the disclosure
Face.
Quantum program instruction for executing disclosure operation includes but is not limited to quantum assembly instruction (QASM) and its increases
Strong version and mutation (the quantum assembler language (f-QASM) with feedback regulation, expansible quantum assembler language (eQASM), band
Level and the quantum assembler language (QASM-HL) of circulation etc.), it should include also general making type language, for example, extensible markup
Language (XML) or JavaScript object numbered musical notation (JSON) and it is general do not have structural instruction method, such as simply
Configuration file or single execute instruction.
Referring herein to according to the flow chart of the method, apparatus (system) of the embodiment of the present disclosure and computer program product and/
Or block diagram describes various aspects of the disclosure.It should be appreciated that flowchart and or block diagram each box and flow chart and/
Or in block diagram each box combination, can be realized by computer-readable program instructions.
These computer-readable program instructions can be supplied to general purpose computer, special purpose computer or other programmable datas
The processing unit of processing unit, so that a kind of machine is produced, so that these instructions are passing through computer or other programmable numbers
When being executed according to the processing unit of processing unit, produces and provided in one or more boxes in implementation flow chart and/or block diagram
Function action device.These computer-readable program instructions can also be stored in a computer-readable storage medium, this
A little instructions so that computer, programmable data processing unit and/or other equipment work in a specific way, thus, be stored with finger
The computer-readable medium of order then includes a manufacture comprising the one or more side in implementation flow chart and/or block diagram
The instruction of the various aspects of function action specified in frame.
Computer-readable program instructions can also be loaded into computer, other programmable data processing units or other
In equipment, so that series of operation steps are executed in computer, other programmable data processing units or other equipment, to produce
Raw computer implemented process, so that executed in computer, other programmable data processing units or other equipment
Instruct function action specified in one or more boxes in implementation flow chart and/or block diagram.
The flow chart and block diagram in the drawings show system, method and the computer journeys according to multiple embodiments of the disclosure
The architecture, function and operation in the cards of sequence product.In this regard, each box in flowchart or block diagram can generation
One module of table, program segment or a part of instruction, the module, program segment or a part of instruction include one or more use
The executable instruction of the logic function as defined in realizing.In some implementations as replacements, function marked in the box
It can occur in a different order than that indicated in the drawings.For example, two continuous boxes can actually be held substantially in parallel
Row, they can also be executed in the opposite order sometimes, and this depends on the function involved.It is also noted that block diagram and/or
The combination of each box in flow chart and the box in block diagram and or flow chart, can the function as defined in executing or dynamic
The dedicated hardware based system made is realized, or can be realized using a combination of dedicated hardware and computer instructions.
The presently disclosed embodiments is described above, above description is exemplary, and non-exclusive, and
It is not limited to the disclosed embodiment.Without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes are obvious for the those of ordinary skill in art field.The selection of term used herein, purport
In the principle, practical application or improvement to the technology in market for best explaining each embodiment, or make the art
Other those of ordinary skill can understand various embodiments disclosed herein.
Claims (26)
1. a kind of method for compiling quantum circuit, comprising:
The logical order to be compiled for being used for the quantum circuit is obtained, the quantum circuit includes multiple quantum bits, described
Logical order in the multiple quantum bit the first quantum bit and the second quantum bit it is associated, the multiple quantum ratio
Dibit quantum door is able to use between at least part in spy to operate；
The path between first quantum bit and second quantum bit is being determined in the quantum circuit；And
Based on the path, generated by addition single-bit quantum door corresponding with the logical order for the quantum
The bottom of circuit instructs.
2. according to the method described in claim 1, wherein generating bottom instruction and including:
Swap gate corresponding with the path is determined, so that grasping by using a dibit quantum door in the path for which
Make first quantum bit and second quantum bit；
Determine the sequence of corresponding with the swap gate dibit quantum door and single-bit quantum door；And
The bottom instruction is generated based on the sequence of the dibit quantum door and single-bit quantum door.
3. according to the method described in claim 1, wherein determine the path include determine first quantum bit with it is described
Shortest path between second quantum bit.
4. according to the method described in claim 3, wherein determining that the shortest path includes:
In response to including the shortest path tree using first quantum bit as starting point in determining buffer, from the buffer
It is middle to read the shortest path.
5. according to the method described in claim 3, wherein determining that the shortest path includes:
In response to determining that in buffer do not include passing through using first quantum bit as the shortest path tree of starting point
Dijkstra's algorithm determines the shortest path tree；
The shortest path tree is saved in both the buffers；And
Based on the shortest path tree, the shortest path is determined.
6. according to the method described in claim 1, wherein the dibit quantum door is CNOT gate, and the single-bit quantum
Door is Hadamard door, and the logical order includes the CNOT that second quantum bit is controlled by first quantum bit
Door.
7. according to the method described in claim 1, further include:
The figure for indicating the quantum circuit is obtained, the node in the figure indicates the quantum bit in the quantum circuit, and
Side in the figure indicates the dibit quantum door.
8. according to the method described in claim 7, wherein determining that the path includes:
It determines and connect the first node for indicating first quantum bit with the second node for indicating second quantum bit
Side together.
9. the side in the weighted graph has corresponding according to the method described in claim 7, wherein the figure includes weighted graph
Weight.
10. according to the method described in claim 9, further include:
The weight in the path is calculated based on the weight on each side in the path.
11. according to the method described in claim 1, the quantum circuit has non-strong continune topology or strong continune topology.
12. according to the method described in claim 1, wherein the quantum circuit include Superconducting Quantum circuit, nuclear magnetic resonance circuit,
At least one of in ion sink circuit and silicon-based semiconductor quantum circuit.
13. a kind of for compiling the device of quantum circuit, comprising:
Logical order obtains module, is configured as obtaining the logical order to be compiled for being used for the quantum circuit, the quantum
Circuit includes multiple quantum bits, the first quantum bit and the second quantum in the logical order and the multiple quantum bit
Bit is associated, and dibit quantum door is able to use between at least part in the multiple quantum bit and is operated；
Path determination module is configured as determining first quantum bit and the second quantum ratio in the quantum circuit
Path between spy；And
Bottom directive generation module, is configured as based on the path, is patrolled to generate with described by addition single-bit quantum door
The corresponding bottom for the quantum circuit of instruction is collected to instruct.
14. device according to claim 13, wherein the bottom directive generation module includes:
Swap gate determining module is configured to determine that swap gate corresponding with the path, so that by using on the road
A dibit quantum door in diameter operates first quantum bit and second quantum bit；
Sequence determining module is configured to determine that the sequence of dibit quantum door corresponding with the swap gate and single-bit quantum door
Column；And
Bottom instruction generates submodule, is configured as generating based on the sequence of the dibit quantum door and single-bit quantum door
The bottom instruction.
15. device according to claim 13, wherein path determination module includes shortest path determining module, it is configured
For the shortest path between determination first quantum bit and second quantum bit.
16. device according to claim 15, wherein the shortest path determining module includes:
Shortest path read module is configured to respond to determine that in buffer include using first quantum bit as starting point
Shortest path tree, the shortest path is read from the buffer.
17. device according to claim 15, wherein the shortest path determining module includes:
Shortest path tree computing module, be configured to respond to determine buffer in do not include using first quantum bit as
The shortest path tree of starting point determines the shortest path tree by dijkstra's algorithm；
Shortest path tree memory module is configured as saving the shortest path tree in both the buffers；And
Shortest path determines submodule, is configured as determining the shortest path based on the shortest path tree.
18. device according to claim 13, wherein the dibit quantum door is CNOT gate, and the single-bit amount
Cervical orifice of uterus is Hadamard door, and the logical order includes controlling second quantum bit by first quantum bit
CNOT gate.
19. device according to claim 13, further includes:
Figure obtains module, is configured as obtaining the figure for indicating the quantum circuit, and the node in the figure indicates the quantum electricity
Quantum bit in road, and the side in the figure indicates the dibit quantum door.
20. device according to claim 19, wherein the path determination module includes:
Side determining module, the first node of first quantum bit will be indicated and indicates second quantum by being configured to determine that
The side that the second node of bit links together.
21. device according to claim 19, wherein the figure includes weighted graph, the side in the weighted graph has corresponding
Weight.
22. device according to claim 21, further includes:
Weight determination module is configured as calculating the weight in the path based on the weight on each side in the path.
23. device according to claim 13, the quantum circuit has non-strong continune topology or strong continune topology.
24. device according to claim 13, wherein the quantum circuit includes Superconducting Quantum circuit, nuclear magnetic resonance electricity
At least one of in road, ion sink circuit and silicon-based semiconductor quantum circuit.
25. a kind of electronic equipment, the electronic equipment include:
One or more processors；And
Memory, for storing one or more programs, when one or more of programs are by one or more of processors
When execution, so that the electronic equipment realizes method described in any one of -12 according to claim 1.
26. a kind of computer readable storage medium is stored thereon with computer program, realization when described program is executed by processor
Method described in any one of -12 according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910153013.5A CN109858628B (en) | 2019-02-28 | 2019-02-28 | Method, apparatus, device and computer readable storage medium for compiling quantum circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910153013.5A CN109858628B (en) | 2019-02-28 | 2019-02-28 | Method, apparatus, device and computer readable storage medium for compiling quantum circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109858628A true CN109858628A (en) | 2019-06-07 |
| CN109858628B CN109858628B (en) | 2021-04-27 |
Family
ID=66899555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910153013.5A Active CN109858628B (en) | 2019-02-28 | 2019-02-28 | Method, apparatus, device and computer readable storage medium for compiling quantum circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109858628B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110569979A (en) * | 2019-09-09 | 2019-12-13 | 中国科学技术大学 | Logical-physical bit remapping method for noisy medium-sized quantum equipment |
| CN110825375A (en) * | 2019-10-12 | 2020-02-21 | 合肥本源量子计算科技有限责任公司 | Quantum program conversion method and device, storage medium and electronic device |
| CN110889506A (en) * | 2019-10-29 | 2020-03-17 | 合肥本源量子计算科技有限责任公司 | Method, device and system for generating quantum instruction and electronic device |
| CN110942152A (en) * | 2019-10-29 | 2020-03-31 | 合肥本源量子计算科技有限责任公司 | Quantum chip system, quantum computing processing system and electronic equipment |
| CN111461334A (en) * | 2020-03-30 | 2020-07-28 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device and equipment |
| CN112668722A (en) * | 2020-12-31 | 2021-04-16 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device, equipment, storage medium and product |
| WO2021115411A1 (en) * | 2019-12-13 | 2021-06-17 | 华为技术有限公司 | Ion trap chip and system |
| CN113222156A (en) * | 2020-01-21 | 2021-08-06 | 合肥本源量子计算科技有限责任公司 | Quantum simulation method and device for operation to be executed |
| CN113379059A (en) * | 2021-06-10 | 2021-09-10 | 北京百度网讯科技有限公司 | Model training method for quantum data classification and quantum data classification method |
| CN113537502A (en) * | 2021-07-14 | 2021-10-22 | 北京百度网讯科技有限公司 | Quantum circuit processing method and device, electronic device and storage medium |
| CN114080614A (en) * | 2019-06-11 | 2022-02-22 | 微软技术许可有限责任公司 | Switching network for quantum computing |
| CN114841352A (en) * | 2022-05-11 | 2022-08-02 | 北京百度网讯科技有限公司 | Quantum calculation processing method and device and electronic equipment |
| WO2022206842A1 (en) * | 2021-03-31 | 2022-10-06 | 合肥本源量子计算科技有限责任公司 | Quantum circuit compilation method and device, compilation framework and quantum operating system |
| CN115293353A (en) * | 2021-04-15 | 2022-11-04 | 合肥本源量子计算科技有限责任公司 | Quantum computer, running method thereof and readable storage medium |
| CN115860128A (en) * | 2022-12-21 | 2023-03-28 | 北京百度网讯科技有限公司 | Quantum circuit operation method and device and electronic equipment |
| CN115952868A (en) * | 2022-12-29 | 2023-04-11 | 北京百度网讯科技有限公司 | Quantum circuit task processing method and device, electronic equipment and readable storage medium |
| CN116227607A (en) * | 2023-02-20 | 2023-06-06 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
| WO2023103705A1 (en) * | 2021-12-08 | 2023-06-15 | International Business Machines Corporation | Circuit serialization for parameterized circuit simulation |
| CN116579435A (en) * | 2023-05-22 | 2023-08-11 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150186587A1 (en) * | 2012-07-19 | 2015-07-02 | Microsoft Technology Licensing, Llc | Method and system for optimal decomposition of single-qubit quantum circuits using standard quantum gates |
| US20170193388A1 (en) * | 2015-12-31 | 2017-07-06 | International Business Machines Corporation | Multi-qubit tunable coupling architecture using fixed-frequency superconducting qubits |
| US20170300454A1 (en) * | 2004-12-23 | 2017-10-19 | D-Wave Systems Inc. | Analog processor comprising quantum devices |
| US20170357561A1 (en) * | 2016-06-09 | 2017-12-14 | Google Inc. | Automatic qubit calibration |
| US20180032893A1 (en) * | 2016-08-01 | 2018-02-01 | Northrop Grumman Systems Corporation | Quantum gates via multi-step adiabatic drag |
| CN107683460A (en) * | 2015-05-05 | 2018-02-09 | 凯恩迪股份有限公司 | The QUANTON that analog quantity increment calculates in conventional processors is represented |
| CN109063843A (en) * | 2018-07-12 | 2018-12-21 | 合肥本源量子计算科技有限责任公司 | A kind of quantum computer software architecture system |
| CN109063844A (en) * | 2018-07-13 | 2018-12-21 | 合肥本源量子计算科技有限责任公司 | A kind of data structure indicating quantum program |
| CN109165741A (en) * | 2018-08-02 | 2019-01-08 | 合肥本源量子计算科技有限责任公司 | Processing method, device, storage medium and the electronic device of quantum wire |
| CN109376867A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The processing method and processing device of two quantum bit logic gates |
| CN109376866A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The operation method and device of the recording method of metadata and device, quantum program |
-
2019
- 2019-02-28 CN CN201910153013.5A patent/CN109858628B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170300454A1 (en) * | 2004-12-23 | 2017-10-19 | D-Wave Systems Inc. | Analog processor comprising quantum devices |
| US20150186587A1 (en) * | 2012-07-19 | 2015-07-02 | Microsoft Technology Licensing, Llc | Method and system for optimal decomposition of single-qubit quantum circuits using standard quantum gates |
| CN107683460A (en) * | 2015-05-05 | 2018-02-09 | 凯恩迪股份有限公司 | The QUANTON that analog quantity increment calculates in conventional processors is represented |
| US20170193388A1 (en) * | 2015-12-31 | 2017-07-06 | International Business Machines Corporation | Multi-qubit tunable coupling architecture using fixed-frequency superconducting qubits |
| US20170357561A1 (en) * | 2016-06-09 | 2017-12-14 | Google Inc. | Automatic qubit calibration |
| US20180032893A1 (en) * | 2016-08-01 | 2018-02-01 | Northrop Grumman Systems Corporation | Quantum gates via multi-step adiabatic drag |
| CN109063843A (en) * | 2018-07-12 | 2018-12-21 | 合肥本源量子计算科技有限责任公司 | A kind of quantum computer software architecture system |
| CN109063844A (en) * | 2018-07-13 | 2018-12-21 | 合肥本源量子计算科技有限责任公司 | A kind of data structure indicating quantum program |
| CN109165741A (en) * | 2018-08-02 | 2019-01-08 | 合肥本源量子计算科技有限责任公司 | Processing method, device, storage medium and the electronic device of quantum wire |
| CN109376867A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The processing method and processing device of two quantum bit logic gates |
| CN109376866A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The operation method and device of the recording method of metadata and device, quantum program |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114080614A (en) * | 2019-06-11 | 2022-02-22 | 微软技术许可有限责任公司 | Switching network for quantum computing |
| CN110569979B (en) * | 2019-09-09 | 2022-09-06 | 中国科学技术大学 | Logical-physical bit remapping method for noisy medium-sized quantum equipment |
| CN110569979A (en) * | 2019-09-09 | 2019-12-13 | 中国科学技术大学 | Logical-physical bit remapping method for noisy medium-sized quantum equipment |
| CN110825375A (en) * | 2019-10-12 | 2020-02-21 | 合肥本源量子计算科技有限责任公司 | Quantum program conversion method and device, storage medium and electronic device |
| CN110942152B (en) * | 2019-10-29 | 2024-02-13 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip system, quantum computing processing system and electronic equipment |
| CN110889506A (en) * | 2019-10-29 | 2020-03-17 | 合肥本源量子计算科技有限责任公司 | Method, device and system for generating quantum instruction and electronic device |
| CN110942152A (en) * | 2019-10-29 | 2020-03-31 | 合肥本源量子计算科技有限责任公司 | Quantum chip system, quantum computing processing system and electronic equipment |
| WO2021115411A1 (en) * | 2019-12-13 | 2021-06-17 | 华为技术有限公司 | Ion trap chip and system |
| CN113222156A (en) * | 2020-01-21 | 2021-08-06 | 合肥本源量子计算科技有限责任公司 | Quantum simulation method and device for operation to be executed |
| CN113222156B (en) * | 2020-01-21 | 2023-08-08 | 本源量子计算科技（合肥）股份有限公司 | Quantum simulation method and device for operation to be executed |
| CN111461334A (en) * | 2020-03-30 | 2020-07-28 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device and equipment |
| CN112668722A (en) * | 2020-12-31 | 2021-04-16 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device, equipment, storage medium and product |
| WO2022206842A1 (en) * | 2021-03-31 | 2022-10-06 | 合肥本源量子计算科技有限责任公司 | Quantum circuit compilation method and device, compilation framework and quantum operating system |
| CN115293353A (en) * | 2021-04-15 | 2022-11-04 | 合肥本源量子计算科技有限责任公司 | Quantum computer, running method thereof and readable storage medium |
| CN113379059B (en) * | 2021-06-10 | 2022-09-23 | 北京百度网讯科技有限公司 | Model training method for quantum data classification and quantum data classification method |
| CN113379059A (en) * | 2021-06-10 | 2021-09-10 | 北京百度网讯科技有限公司 | Model training method for quantum data classification and quantum data classification method |
| CN113537502B (en) * | 2021-07-14 | 2022-04-12 | 北京百度网讯科技有限公司 | Quantum circuit processing method and device, electronic device and storage medium |
| CN113537502A (en) * | 2021-07-14 | 2021-10-22 | 北京百度网讯科技有限公司 | Quantum circuit processing method and device, electronic device and storage medium |
| WO2023103705A1 (en) * | 2021-12-08 | 2023-06-15 | International Business Machines Corporation | Circuit serialization for parameterized circuit simulation |
| CN114841352B (en) * | 2022-05-11 | 2023-03-10 | 北京百度网讯科技有限公司 | Quantum computing processing method and device and electronic equipment |
| CN114841352A (en) * | 2022-05-11 | 2022-08-02 | 北京百度网讯科技有限公司 | Quantum calculation processing method and device and electronic equipment |
| CN115860128A (en) * | 2022-12-21 | 2023-03-28 | 北京百度网讯科技有限公司 | Quantum circuit operation method and device and electronic equipment |
| CN115860128B (en) * | 2022-12-21 | 2023-08-15 | 北京百度网讯科技有限公司 | Quantum circuit operation method and device and electronic equipment |
| CN115952868B (en) * | 2022-12-29 | 2024-01-12 | 北京百度网讯科技有限公司 | Quantum circuit task processing method and device, electronic equipment and readable storage medium |
| CN115952868A (en) * | 2022-12-29 | 2023-04-11 | 北京百度网讯科技有限公司 | Quantum circuit task processing method and device, electronic equipment and readable storage medium |
| CN116227607A (en) * | 2023-02-20 | 2023-06-06 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
| CN116227607B (en) * | 2023-02-20 | 2023-09-26 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
| CN116579435A (en) * | 2023-05-22 | 2023-08-11 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
| CN116579435B (en) * | 2023-05-22 | 2023-12-05 | 北京百度网讯科技有限公司 | Quantum circuit classification method, quantum circuit classification device, electronic equipment, medium and product |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109858628B (en) | 2021-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109858628A (en) | Compile method, apparatus, equipment and the computer readable storage medium of quantum circuit | |
| US10963817B2 (en) | Training tree-based machine-learning modeling algorithms for predicting outputs and generating explanatory data | |
| Mao et al. | Routing or computing? The paradigm shift towards intelligent computer network packet transmission based on deep learning | |
| US20200005179A1 (en) | Cost function deformation in quantum approximate optimization | |
| Shang et al. | Quantum immune clonal coevolutionary algorithm for dynamic multiobjective optimization | |
| JP7350867B2 (en) | Quantum feature kernel alignment | |
| Daei et al. | Optimized quantum circuit partitioning | |
| US11010514B2 (en) | Grouping of Pauli strings using entangled measurements | |
| Kusyk et al. | Survey on quantum circuit compilation for noisy intermediate-scale quantum computers: Artificial intelligence to heuristics | |
| JP2021512387A (en) | Quantum computing device design | |
| WO2023082436A1 (en) | Quantum computing task processing method and system, and computer device | |
| CN110058937A (en) | For dispatching the method, equipment and computer program product of dedicated processes resource | |
| Bouzidi et al. | Dynamic clustering of software defined network switches and controller placement using deep reinforcement learning | |
| Skolik et al. | Robustness of quantum reinforcement learning under hardware errors | |
| JP2020027399A (en) | Computer system | |
| US20230099621A1 (en) | Determination of quantum circuit compilation passes and/or compilation parameters optimized for one or more performance metrics | |
| Li et al. | Quantum circuit compilation for nearest-neighbor architecture based on reinforcement learning | |
| WO2016174725A1 (en) | Computer, and calculation method using neural network | |
| US20200285985A1 (en) | Constant folding for compilation of quantum algorithms | |
| Chen | Optimization of zero-order TSK-type fuzzy system using enhanced particle swarm optimizer with dynamic mutation and special initialization | |
| Sambangi et al. | Application mapping onto manycore processor architectures using active search framework | |
| Chen et al. | Routing Strategy for Distributed Quantum Circuit based on Optimized Gate Transmission Direction | |
| Azad et al. | Circuit centric quantum architecture design | |
| CN115879562A (en) | Quantum program initial mapping determination method and device and quantum computer | |
| Bhuvana et al. | Stopping criteria for MAPLS-AW, a hybrid multi-objective evolutionary algorithm |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |