CN109858287B - Physical unclonable structure based on interconnection line and self-scrambling circuit structure - Google Patents
Physical unclonable structure based on interconnection line and self-scrambling circuit structure Download PDFInfo
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- CN109858287B CN109858287B CN201910079802.9A CN201910079802A CN109858287B CN 109858287 B CN109858287 B CN 109858287B CN 201910079802 A CN201910079802 A CN 201910079802A CN 109858287 B CN109858287 B CN 109858287B
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Abstract
The invention relates to a physical unclonable structure and a self-scrambling circuit structure based on an interconnection line, wherein the physical unclonable structure consists of a linear shift register, an interconnection line network, a load buffer array and a digital signature generator. The physical unclonable structure and the self-scrambling circuit structure based on the interconnection line further comprise a self-scrambling circuit structure on the basis of the structure, and the self-scrambling circuit structure is composed of a counter type mask generator, a nonvolatile memory and a circular scrambling circuit. The invention has the advantages that: the reliability is higher, and the iUF is not influenced by the aging effect of the transistor. The uniqueness of the digital signature generated by the iPUF is improved by the self-scrambling circuit structure, and the self-scrambling circuit can be applied to other timing PUFs. The rate of generating the digital signature by the iUF is high, and the area and power consumption overhead of the iUF are small. In addition, the interconnecting wire structure in the iUF can be used for placing an uncongested metal layer, and does not occupy an active device layer.
Description
Technical Field
The invention aims to provide a physical unclonable structure and a self-scrambling circuit structure based on interconnection lines, and particularly the physical unclonable structure utilizes the manufacturing uncertainty in the manufacturing process of an integrated circuit to generate a digital signature with uniqueness and randomness for each chip, and is an important primitive of the hardware security of the integrated circuit. The self-scrambling circuit may be used to promote uniqueness of digital signatures. Belongs to the technical field of microelectronics and integrated circuits.
Background
An integrated circuit (integrated circuit) is a type of microelectronic device or component. It is through the semiconductor manufacturing process such as oxidation, photoengraving, diffusion, epitaxy, evaporating aluminium, etc., semiconductor, resistance, electric capacity, etc. that the circuit that will form and have certain function and connecting wire among them are all integrated on a small silicon chip, then weld the electronic device encapsulated in a tube; all the elements are structurally integrated, so that the electronic elements are greatly miniaturized, low in power consumption, intelligent and high in reliability. The integrated circuit has the advantages of small volume, light weight, few lead wires and welding points, long service life, high reliability, good performance and the like, and is low in cost and convenient for large-scale production. Integrated circuits can be classified into three types, i.e., analog integrated circuits, digital integrated circuits, and digital/analog hybrid integrated circuits, according to their functions and structures.
Physically Unclonable Functions (PUFs) have become hardware primitives that secure integrated circuits. Unlike methods that store secure keys in non-volatile memory, the physically unclonable structure is able to generate a unique, unclonable, dynamic digital signature or key for each chip when an excitation signal is input. The physical unclonable structure exploits manufacturing uncertainties in the chip manufacturing process to generate a digital signature with sufficient uniqueness and stability. Based on the above properties, physical unclonable structures are widely used for low-cost authentication and key generation.
Most of the existing physical unclonable structures utilize the manufacturing uncertainty of active devices, so the digital signatures of the existing physical unclonable structures are influenced by working temperature, power supply noise and aging effect, and the stability is reduced. Furthermore, existing physical unclonable structures present potential security threats, such as modeling attacks. Therefore, a method for improving physical unclonable reliability and security is proposed.
After searching the prior art documents, Kan Xiao et al published "Bit selection algorithm for high-volume production of SRAM-PUF (method for stable Bit screening in large-scale SRAM-PUF)" in IEEE International Symposium on Hardware-organized Security and Trust (HOST) in 2014 by Kan Xiao et al in 2007, and proposed a method for stably ordering all bits of SRAM-PUF by spatial correlation of SRAM, however, the method cannot be applied to the traditional delay-based physically unclonable structure. Achiranshu Garg et al published in 2014 "Design of SRAM PUF with improved uniformity and stability of SRAM-PUF by using device aging effect" on IEEE International Symposium on Circuits and Systems (ISCAS) (International Circuit and System conference), and proposed a method for improving uniformity and stability of SRAM-PUF respectively by performing two-stage pressure aging on the device, however, the aging time and aging configuration required by different PUFs are different, and the testing cost of designers is increased to a great extent. Tauhidur Rahman et al in 2016 have published "An Aging-Resistant RO-PUF for reusable Key Generation" on IEEE Transactions on emitting Topics in Computing (journal of the New computer research topic), and have proposed that when a PUF does not work, the gate voltage of a PMOS therein is biased as a supply voltage to reduce the NBTI Aging effect to which the PUF is subjected, which improves the stability of the PUF, but requires a designer to perform layout design. In summary, although the improved method proposed above can solve the problem of the physical unclonable structure, the above lifting method has application limitation, and some methods greatly increase the processing and testing cost of the designer.
Disclosure of Invention
To address the deficiencies of the prior art, it is an object of the present invention to provide an interconnect-based physically unclonable structure (iPUF) that utilizes the uncertainty of crosstalk signals on interconnects due to interconnect manufacturing uncertainty to generate a unique digital signature for a chip. In the designed physical unclonable structure of the interconnection line, a linear shift register is used for generating an excitation vector, the excitation vector is input to an interconnection line network, and two paths of disturbed signals in the interconnection line network are connected with a digital signature generator. The digital signature generator is composed of basic digital devices and is used for comparing the speeds of the two paths of disturbed signals and generating a digital signature.
Further, it is another object of the present invention to provide a self-scrambling circuit structure to improve the uniqueness of the digital signature generated by the interconnect physical unclonable structure. The self-scrambling circuit structure carries out bitwise summation operation on the digital signature generated by each chip, and the result of the summation operation is used as a mask to carry out cyclic exclusive-OR operation on the original digital signature.
The invention relates to a physical unclonable structure based on an interconnection line, which consists of a linear shift register, an interconnection line network, a load buffer array and a digital signature generator. In addition, a control unit is provided for controlling the operation of the various modules. The working method and principle of its respective parts are as follows.
The linear shift register takes an input excitation signal as an initial value (seed) of the linear shift register, and returns the sum of the exclusive OR of different bit numbers in the linear shift register to an input end of the linear shift register, so that the value of the linear shift register changes in each clock cycle, and a generated number sequence has certain randomness. The lambda bit in the linear shift register will serve as the excitation vector for the interconnect network.
The interconnection network is composed of lambda long interconnection lines which are arranged in parallel, wherein two interconnection lines are disturbed lines, the rest lambda-2 interconnection lines are attack lines, and the two sides of each disturbed line share (lambda-2)/2 attack lines. The input end of the disturbed wire is connected with the system clock of the control unit, and the output end of the disturbed wire is connected with the digital signature generator. The input end of the attack line is connected with a lambda-2 bit output bit in the linear shift register, and the output of the linear shift register is used as an excitation vector of the interconnection line network. Due to the coupling capacitance and the coupling inductance existing between the interconnection lines, when an excitation vector propagates on the attack line, coupling current and voltage appear on the victim line, and finally the time of a clock signal propagating along the victim line reaching the digital signature generator is influenced. Due to the manufacturing uncertainty, the effect size of the attack line on the disturbed line in each chip is different, and the digital signature generator can generate different signals. And the response of the manufacturing uncertainty to each excitation vector is different, and by changing the value and the number of the excitation vectors, the iPUF can generate digital signatures with different lengths.
Preferably, in order to make the manufacturing uncertainty of the interconnection line become the main factor for determining the digital signature, the structure of the interconnection line network is improved to make the signals propagated on the interference lines located adjacent to the two disturbed lines identical, that is, the input ends of the interference lines on both sides of the two disturbed lines are respectively connected to make the interference lines have the same excitation signal. At this time, the excitation vectors of the two victim wires are the same, and the magnitude of the victim signal on the victim wire is mainly determined by the manufacturing uncertainty, i.e. the connection shown by the bold line in fig. 3.
The load buffer array is connected with the attack lines in the interconnection line network, so that the attack lines have the same load on one hand, and the interference of signals transmitted by the attack lines on other signals in the circuit is reduced on the other hand.
And the digital signature generator consists of two NAND gates. The outputs of the two-input NAND gates are respectively connected with the input of the other NAND gate, and the other input ends of the two NAND gates are connected with the two disturbed wires in the interconnection line network. When the clock signals are propagated to the digital signature generator along the two disturbed wires, the time for the two clock signals to reach the digital signature generator is different due to the crosstalk signals of the interconnection wire network. When iPUF is not working, the digital signature generator output remains a constant '1'. If the rising edge of the victim line 1 is earlier than the rising edge of the victim line 2, the digital signature generator outputs '0', otherwise, the output is '1'. On the falling edge of the clock, the digital signature generator is reset to the initial state '1'.
Preferably, the interconnection line-based physically unclonable structure and the self-scrambling circuit structure are based on the interconnection line-based physically unclonable structure, and further comprise a self-scrambling circuit structure, wherein the self-scrambling circuit structure is composed of a counter type mask generator, a non-volatile memory (a structure already existing in a chip and used for storing a mask generated by each chip), and a circular scrambling circuit.
And the input end of the counter type mask generator is the output of the physical unclonable structure (iUF) based on the interconnection line, the counter type mask generator performs summation operation on the original output of the iUF, and the operation result is stored in the nonvolatile memory.
The nonvolatile memory is an existing storage structure in the circuit and is used for storing the mask generated by the counting type mask generator. When the iUF works, the nonvolatile memory sends the mask to the circular scrambling circuit.
The circular scrambling circuit is formed by circularly connecting m registers, and a two-input selector is arranged in front of each register and used for selecting a data source. Before each iUF is output, the value of a register in the cyclic scrambling circuit is configured to be a mask value stored in a nonvolatile memory, when the iUF is output, each bit cycle in the cyclic scrambling circuit is subjected to exclusive OR with an original digital signature generated by the iUF, and the exclusive OR value serves as a scrambled digital signature and is output.
Preferably, the present invention further comprises a control unit controlling the operation of the iPUF, generating an enable signal for the counter type mask generator, and controlling an output process of the counter type mask generator, generating a control signal of the nonvolatile memory, and controlling a data source of the loop scrambling circuit.
A physical unclonable structure based on interconnection lines and a working process of a self-scrambling circuit are disclosed: when the iUF works for the first time, an excitation signal is input from the outside and is used as a seed of the linear shift register, the linear shift register runs for n clock cycles and generates n excitation vectors for the interconnection line network, and the digital signature generator generates n-bit original digital signatures. A counter type mask generator sums the n-bit original digital signatures to generate a unique mask for each chip, the mask value being stored in non-volatile memory. When the iUF works, a user gives different excitation signals to the iUF, the iUF generates a corresponding original digital signature, the cyclic scrambling circuit carries out bit-wise cyclic exclusive OR on the original digital signature and the mask, and the iUF finally outputs the scrambled digital signature. The scrambled digital signature may serve as a key in cryptography.
The invention relates to a physical unclonable structure based on an interconnection line and a self-scrambling circuit, wherein the manufacturing method comprises the following steps:
the method comprises the steps of designing and integrating circuits of an iPFF circuit, a self-scrambling circuit and a control unit. Initial circuit design, synthesis and netlist generation. The design, synthesis and netlist generation process of the initial integrated circuit is not influenced by iPFF;
and step two, laying out and wiring the iPFF circuit and the self-scrambling circuit. The placement and routing requirements of the iPUF circuit are as follows: the interconnect lines in the interconnect network should be placed side by side and require the pitch of the different interconnect lines to be as small as possible to increase the coupling between the interconnect lines. The load buffer arrays are approximately the same distance from the terminals of the different interconnect lines so that they have the same load. Two NAND gates in the digital signature generator are symmetrically placed, so that the distances between the NAND gates and two disturbed lines are the same, and the influence of the line length on signal time delay is reduced;
and step three, performing incremental layout and wiring on the initial integrated circuit. The additional area overhead occupied by the number of iUF devices is small, and the influence on the layout and wiring of an initial circuit is small.
And step four, flow sheet. The test structure designed by the invention is composed of digital devices, and the tape-out process of the test structure is consistent with the tape-out process of a common integrated circuit;
and step five, testing. And carrying out structural and functional tests on the chip of the chip. Ensuring that it is free of manufacturing defects.
And step six, initializing the iUF. And completing the initial configuration of the iPUF, and generating a mask for improving the output uniqueness of the iPUF. And collecting response signals of all chips iUF under different excitation signals.
Step seven, authentication is performed in use. During the use process of the integrated circuit, a designer inputs test stimulus to the iUF, and compares whether the output response signal exists in the response signal collected in the step six, if so, the chip is proved to be a credible chip designed by the designer.
The physical unclonable structure and the self-scrambling circuit based on the interconnection line have the advantages that:
compared with the traditional PUF structure formed by active devices, the iUF utilizes the manufacturing uncertainty of passive devices (interconnection lines), and therefore has higher reliability. iPUF is not affected by transistor aging effects such as negative bias temperature instability, hot carrier injection effects, and time dependent insulator breakdown effects. Although the interconnect lines may be affected by electromigration effects, because the iPUF runs much less long than the integrated circuit system, it ages much less than normal circuits.
The uniqueness of the digital signature generated by the iPFF is effectively improved by the self-scrambling circuit structure, and the self-scrambling circuit can be applied to other timing PUFs.
The rate of generating the digital signature by the iUF is high (1 bit per clock cycle), the area and power consumption overhead of the iUF are small, and if a linear shift register in the iUF is of a K order, the iUF can generate a length less than 2K-a digital signature of any length of 1. Furthermore, the interconnect structure in iPUF can place uncongested metal layers without occupying the active device layer.
Drawings
Figure 1 is a circuit diagram of an interconnect physical unclonable structure of example 1 of the present invention.
Figure 2 is a circuit diagram of an interconnect physical unclonable structure of example 2 of the present invention.
Fig. 3 is a configuration diagram of a self-scrambling circuit according to embodiment 3 of the present invention.
Fig. 4 is an explanatory diagram of the structure of the physically unclonable and self-scrambling circuit of the interconnect line in embodiment 3 of the present invention.
Fig. 5 is a schematic diagram of the uniqueness promotion of a self-scrambling circuit on a digital signature.
Fig. 6 shows that the same excitation signal is input to 500iPUF sample circuits generated in the simulation process.
Fig. 7 is a flow chart for iPUF and self-scrambling circuit fabrication.
Fig. 8 is a hamming distance distribution diagram of an iPUF-generated original digital signature and a scrambled digital signature.
Fig. 9 shows the stability of iPUF digital signatures when temperature and supply voltage are varied.
Figure 10 is the stability of iPUF digital signatures after one year of stress aging.
The symbols in the figures are as follows:
normal min maxVDD chip Normal supply Voltage(ii) a VDD is the minimum power supply voltage value in the chip test; VDD: chip testing
pnormal pminA maximum supply voltage value in the test; t: critical path delay under normal supply voltage; t: critical path at maximum supply voltage
pmaxDelay of the path; t: the critical path time delay is carried out under the minimum power supply voltage; alpha is a process correlation constant; gamma-critical path delay dependent power supply
TE0A rate of change of voltage; v is the equivalent initial threshold voltage of the circuit to be tested.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
In the following embodiments of the present invention, software simulation for integrated circuit chips employs HSPICE 2014 and IC Compiler software. HSPICE is a commercial general-purpose circuit simulation program developed by Synop corporation for simulation analysis of circuit performance, such as steady-state analysis, transient analysis, and frequency-domain analysis, in integrated circuit design. On the basis of SPICE (produced in 1972) of Berkeley, PSPICE (produced in 1984) of MicroSim company and other circuit analysis software, some new functions are added, and accurate simulation, analysis and optimization of the circuit in the microwave frequency range from direct current to over 100GHz can be completed through continuous improvement. In practical applications, HSPICE can provide critical circuit simulation and design solutions. IC Compiler is a Synopsys next generation place and route system that guarantees excellent quality and shortens design time by extending physical synthesis to the entire place and route process and signoff driven design convergence. Previous generation solutions have their limitations due to the independent operation of the layout, clock tree and wiring. The extended physical synthesis (XPS) technology of IC Compiler breaks this limitation, extending physical synthesis to the entire place and route process. IC Compiler employs a unified TCL-based architecture, which is innovative and utilizes several of the most excellent core technologies of Synopsys. As a complete set of layout and wiring design system, the system comprises all functions necessary for realizing the next generation design, such as physical synthesis, layout, wiring, time sequence, Signal Integrity (SI) optimization, low power consumption, design for test (DFT) and yield optimization.
Example 1
As shown in FIG. 1, the physical unclonable structure (iUF) for interconnection lines designed by the invention is composed of a linear shift register, an interconnection line network, a load buffer array and a digital signature generator.
The linear shift register takes an input excitation signal as an initial value (seed) of the linear shift register, and returns the sum of the XOR of different bit numbers in the linear shift register to the input end of the linear shift register, so that the value of the linear shift register in each clock cycle is changed, and a generated number sequence has certain randomness; the lambda bit in the linear shift register will serve as the excitation vector for the interconnect network.
The linear shift register is a general circuit structure, and when different seeds are input into the linear shift register, the linear shift register can generate different excitation vectors with the bit width of lambda-2 in each clock cycle. λ is the number of interconnect lines in the interconnect network. In the simulation, a 23-bit linear shift register is used, whose characteristic polynomial is f (x) x23+x22+x21+x20+x19+x7In addition, any linear shift register that can generate a quasi-random sequence with a bit width of λ -2 can generate an excitation vector for iPUF. The designer can control the length of the excitation vector and the characteristics of the linear shift register. In addition, for a general integrated circuit, linear shift registers are integrated in most chips, and the existing linear shift registers in the circuit can be multiplexed under the condition that the safety of the linear shift registers is ensured so as to further reduce the area and power consumption overhead of iUF.
The iPU generates a digital signature for each chip by using the uncertainty of crosstalk signals caused by the uncertainty of the manufacturing of the interconnection lines; the purpose of the interconnect network is to maximize the uncertainty of the crosstalk signal between the interconnect lines. The interconnection network is composed of lambda long interconnection lines which are arranged in parallel, wherein two interconnection lines are disturbed lines, the rest lambda-2 interconnection lines are attack lines, and the two sides of each disturbed line share (lambda-2)/2 attack lines. The input end of the disturbed wire is connected with the system clock of the control unit, and the output end of the disturbed wire is connected with the digital signature generator. The input end of the attack line is connected with a lambda-2 bit output bit in the linear shift register, and the output of the linear shift register is used as an excitation vector of the interconnection line network. Due to the coupling capacitance and the coupling inductance existing between the interconnection lines, when an excitation vector propagates on the attack line, coupling current and voltage appear on the victim line, and finally the time of a clock signal propagating along the victim line reaching the digital signature generator is influenced. Due to the manufacturing uncertainty, the effect size of the attack line on the disturbed line in each chip is different, and the digital signature generator can generate different signals. And the response of the manufacturing uncertainty to each excitation vector is different, and by changing the value and the number of the excitation vectors, the iPUF can generate digital signatures with different lengths. Two victim lines are driven by a clock and the remaining aggressor lines are driven by a linear shift register. In order to reduce the influence of the load on the crosstalk signals, the terminals of the two victim wires are connected to a digital signature generator with symmetrical structure. And the end of the attack line is connected to the buffer array. Therefore, the magnitude of the crosstalk signals on the two victim wires will be mainly determined by the excitation vectors and the manufacturing uncertainty of the interconnect wires. In addition, a particular input vector should produce enough crosstalk signal uncertainty between the two victim wires of different chips to make the iPUF generated digital signature sufficiently unique and to distinguish between all chips.
The load buffer array is connected with the attack line terminal in the interconnection line network, so that the attack lines have the same load on one hand, and the interference of signals transmitted by the attack lines on other signals in the circuit is reduced on the other hand.
And the digital signature generator is a NAND gate-based latch and consists of two NAND gates. The digital signature generator is used as a speed comparison circuit and can compare the speed of clock signals transmitted along two disturbed wires reaching the digital signature generator. The outputs of the two-input NAND gates are respectively connected with the input of the other NAND gate, and the other input ends of the two NAND gates are interfered with two paths in the interconnection networkThe wires are connected. When the clock signals are propagated to the digital signature generator along the two disturbed wires, the time for the two clock signals to reach the digital signature generator is different due to the crosstalk signals of the interconnection wire network. When iPUF is not working, the digital signature generator output remains a constant '1'. If the rising edge of the victim line 1 is earlier than the rising edge of the victim line 2, the digital signature generator outputs '0', otherwise, the output is '1'. On the falling edge of the clock, the digital signature generator is reset to the initial state '1'. This reset operation ensures that there is no relationship between two adjacent outputs. If the linear shift register in the iPUF is K-th order, the linear shift register can generate any length less than 2 for a given input signalK-1 excitation vector, and the digital signature generator can generate an arbitrary length less than 2K-a digital signature of 1.
Example 2
In the structure of example 1 (fig. 1), the interconnect line fabrication uncertainty is not a determining factor of the digital signature. The magnitude of the crosstalk signal is also influenced by factors such as signal rising delay, signal falling delay, leakage path charging and discharging and the like, so that the crosstalk signal is difficult to predict or clone, and the physical unclonable structure can prevent modeling attack. However, because adjacent interconnection lines in the interconnection line network have a shielding effect on the victim line, the crosstalk signal generated by the adjacent interconnection lines on the victim signal is much larger than the crosstalk signal generated by the aggressor line spaced farther from the victim line.
In order to make the manufacturing uncertainty of the interconnection line become the main factor for determining the digital signature, the structure of the interconnection line network in embodiment 1 is improved to make the signals propagated on the interference lines located adjacent to the two disturbed lines identical, that is, the input ends of the interference lines on both sides of the two disturbed lines are respectively connected to make the interference lines have the same excitation signal. At this time, the excitation vectors of the two victim wires are the same, and the magnitude of the victim signal on the victim wire is mainly determined by the manufacturing uncertainty, i.e., the connection shown by the bold line in fig. 2.
Example 3
In order to improve the uniqueness of the digital signature generated by the interconnection line physical unclonable structure, the invention provides an interconnection line-based physical unclonable structure and a self-scrambling circuit structure, wherein a self-scrambling circuit structure is further added on the basis of the interconnection line-based physical unclonable structure, as shown in fig. 3, the self-scrambling circuit structure performs bitwise summation operation on the digital signature generated by each chip, and the result of the summation operation is used as a mask to perform cyclic exclusive or operation on the original digital signature. The self-scrambling circuit is composed of a counter type mask generator, a non-volatile memory (a structure already existing in a chip for storing a mask generated by each chip), and a cyclic scrambling circuit.
The input end of the counter type mask generator is the output of the physical unclonable structure (iUF) based on the interconnection line, the counter type mask generator performs summation operation on the original output of the iUF, and the operation result is stored in the nonvolatile memory.
The nonvolatile memory is an existing storage structure in the circuit and is used for storing the mask generated by the counting type mask generator. When the iUF works, the nonvolatile memory sends the mask to the circular scrambling circuit.
The circular scrambling circuit is formed by circularly connecting m registers, and a two-input selector is arranged in front of each register and used for selecting a data source. Before each iUF is output, the value of a register in the cyclic scrambling circuit is configured to be a mask value stored in a nonvolatile memory, when the iUF is output, each bit cycle in the cyclic scrambling circuit is subjected to exclusive OR with an original digital signature generated by the iUF, and the exclusive OR value serves as a scrambled digital signature and is output. The cyclic scrambling circuit is composed of m triggers connected end to end, the m triggers store the mask code of each chip, the mask code moves to the right in each clock period, each bit is subjected to exclusive OR operation with the corresponding bit in the original digital signature in sequence, the operation result is equivalent to the exclusive OR of each m-bit original digital signature and the m-bit mask code, and the output is used as the scrambled digital signature. In the use process of the iUF, the control unit loads a mask in a nonvolatile memory into a loop scrambling circuit firstly, wherein when the iUF generates a digital signature, the loop scrambling circuit carries out exclusive OR operation on the Raney digital signature. The operation can improve the uniqueness of the digital signatures generated by different chips iUF so as to distinguish all the chips.
Further, in the iPUF configuration stage, the control unit outputs the gated clock to control the operation of the iPUF after receiving the external iPUF enable signal, and simultaneously generates an enable signal for the counter type mask generator and controls the counter type mask generator to generate the mask, and then the control unit generates the access address and the write enable signal of the nonvolatile memory and stores the mask in the nonvolatile memory. In the phase of iUF authentication, a control unit generates an access address and a read enable signal of a nonvolatile memory, a mask is loaded into a circular scrambling circuit by using a mask selection signal, then the iUF is started, and the circular scrambling circuit performs exclusive OR operation on an original digital signature and the mask generated by the iUF by using the mask selection signal.
Referring to fig. 4, the present embodiment is an interconnect-based physically unclonable structure (iPUF) and self-scrambling circuit, in which the nonvolatile memory is an existing structure in the circuit, and the remaining six parts can be embedded in an existing integrated circuit chip.
Referring to fig. 4, in the iPUF operation, a user inputs an excitation signal as a seed of the linear shift register, and the linear shift register outputs an excitation vector sequence as an input of the interconnection network. The excitation vector propagates along λ -2 attack lines in a network of interconnect lines (which is made up of λ parallel interconnect lines). The signal propagating on the aggressor wire will generate a crosstalk signal on the 2 victim wires, and the magnitude of the crosstalk signal is affected by the excitation vector and interconnect line manufacturing uncertainty. The digital signature generator may compare the times of arrival of the two signals (and the magnitude of the crosstalk signal) propagating along the victim wire and generate a '0/1' sequence. The counter type mask generator generates a unique mask for each chip according to the original digital signature generated by each chip, and the cyclic scrambling circuit performs exclusive-OR operation on the original digital signature generated by each chip by using the mask unique to each chip so as to improve the uniqueness of the digital signatures of different chips.
As shown in fig. 5, the principle of the cyclic scrambling circuit to promote the uniqueness of the digital signature is as follows: suppose that p bits are different in the masks with the bit width of m of the two chips, q bits are different in the original digital signatures with the bit width of n of the two chips, and the n-q bits are the same. In the original digital signature by XOR-ing the original digital signature with a mask
The bit output will be affected, among these affected output bits, wherein
The bits will have the same value flipped to a different value, resulting in increased uniqueness of the iPUF. On the other hand, in the affected bits, there will be
Flipping the bits from the originally different values to the same values reduces the uniqueness of the iPUF. Therefore, the result of the uniqueness boost is shown in equation (1).
It can be seen from equation (1) that the cyclic scrambling circuit has an improved effect on the uniqueness for the case where the different bits q/n are < 0.5 in both digital signatures. For iPUF, the uniqueness of its digital signature is mostly less than 50%. In addition, the smaller the uniqueness of the original digital signature is, the more obvious the improvement effect of the cyclic scrambling circuit on the uniqueness is. It is worth mentioning that an unstable bit drop in the mask causes a 1/m bit error rate to occur in the scrambled output, which finally causes a reduction in stability of iPUF. For this reason, the value of the mask needs to be saved in non-volatile memory or in an off-chip authentication system.
The physical unclonable structure based on interconnection lines and the self-scrambling circuit designed by the invention are simulated and tested as follows:
testing was performed using HSPICE 2014 software, using a 28nm process library for simulation, and using a VCS for functional simulation of the test system. The testing accuracy of the testing circuit under the manufacturing uncertainty is verified by using a Monte Carlo simulation method in Hspice, and the standard configuration and the manufacturing uncertainty of the interconnection line in the test are shown in Table 1. From the uncertainties shown in table 1, 500iPUF samples were generated, with an iPUF operating frequency of 125 MHz. The model of the device used by the digital signature generator is NAND2X4_ LVT. In the simulation, the same excitation signal was input to the linear shift register of 500iPUF samples, as shown in fig. 6. The power supply voltage of iUF is 1.05V, the working temperature is 25 ℃, and the length of the digital signature is 1024. Wherein W is the gate width, L is the gate length, VThIs the threshold voltage of the MOS transistor.
iPUF standard design criteria and manufacturing uncertainty:
TABLE 1
The physical unclonable structure based on interconnection lines and the self-scrambling circuit designed by the invention are inserted into some standard test circuits (ITC benchmark) and 64-bit floating point and graphic units from an open source SPARC processor (OpenSPARC 2 SPARC core).
Firstly, the EDA software is used for RTL design and synthesis of a circuit inserted with iUF. And laying out and wiring the iUF by applying IC Compiler software, carrying out incremental laying out and wiring on an original circuit, and finally generating a layout of the circuit. The physical unclonable structure based on the interconnection line and the total area and power consumption overhead occupied by the self-scrambling circuit after being inserted into the reference circuit are obtained, as shown in table 2. Because the network of interconnect lines in the iPUF can be placed in uncongested metal layers, the major area overhead of iPUF comes from the area of the linear shift register and self-scrambling circuitry. In the experiment, the bit width of the linear shift register in iPUF is 23, and the bit width of the mask is 10 (corresponding to the number of flip-flops in the self-scrambling circuit being 10). As can be seen in table 2, the iPUF area overhead ranges from 0.08% to 1.86%.
The overhead ratio of the on-chip critical path time delay measurement system to the total circuit area is as follows:
| standard test circuit | b19 | FGU | Leon3s | S35932 | VGA-LCD |
| Area overhead (%) | 0.19 | 0.08 | 0.15 | 1.86 | 0.16 |
TABLE 2
Next, the uniqueness analysis was performed on the 500iPUF generated digital signatures. The uniqueness of the digital signature is calculated by inputting the same excitation signal to all ipufs and generating the average value of hamming distances between the digital signatures by all ipufs. Fig. 8 is a distribution diagram of the uniqueness of the original digital signature generated by iPUF and the digital signature after scrambling, and the uniqueness of the digital signature generated by iPUF is improved to 48.63% by using a self-scrambling circuit. Fig. 9 shows that when the temperature and the supply voltage were changed, the stability of iPUF generated the digital signature was 99.06% and 96.09%, respectively. Fig. 10 shows the stability of iPUF after one year of stress aging, and the proportion of bits in the digital signature that flip was 0.36%.
As shown in fig. 7, the method for manufacturing the interconnection-line-based physically unclonable structure and self-scrambling circuit of the present invention includes the following steps:
the method comprises the steps of designing and integrating circuits of an iPFF circuit, a self-scrambling circuit and a control unit. Initial circuit design, synthesis and netlist generation. The design, synthesis and netlist generation process of the initial integrated circuit is not influenced by iPFF;
and step two, laying out and wiring the iPFF circuit and the self-scrambling circuit. The placement and routing requirements of the iPUF circuit are as follows: the interconnect lines in the interconnect network should be placed side by side and require the pitch of the different interconnect lines to be as small as possible to increase the coupling between the interconnect lines. The load buffer arrays are approximately the same distance from the terminals of the different interconnect lines so that they have the same load. Two NAND gates in the digital signature generator are symmetrically placed, so that the distances between the NAND gates and two disturbed lines are the same, and the influence of the line length on signal time delay is reduced;
and step three, performing incremental layout and wiring on the initial integrated circuit. The additional area overhead occupied by the number of iUF devices is small, and the influence on the layout and wiring of an initial circuit is small.
And step four, flow sheet. The test structure designed by the invention is composed of digital devices, and the tape-out process of the test structure is consistent with the tape-out process of a common integrated circuit;
and step five, testing. And carrying out structural and functional tests on the chip of the chip. Ensuring that it is free of manufacturing defects.
And step six, initializing the iUF. And completing the initial configuration of the iPUF, and generating a mask for improving the output uniqueness of the iPUF. And collecting response signals of all chips iUF under different excitation signals.
Step seven, authentication is performed in use. During the use process of the integrated circuit, a designer inputs test stimulus to the iUF, and compares whether the output response signal exists in the response signal collected in the step six, if so, the chip is proved to be a credible chip designed by the designer.
Claims (2)
1. A physical unclonable structure iUF based on interconnection line, characterized by: the structure consists of a linear shift register, an interconnection network, a load buffer array and a digital signature generator;
the linear shift register takes an input excitation signal as an initial value of the linear shift register, and returns the sum of the XOR of different bit numbers in the linear shift register to an input end of the linear shift register, so that the value of the linear shift register is changed in each clock period, and a generated number sequence has certain randomness; the lambda bit in the linear shift register will be used as the excitation vector of the interconnection network;
when different seeds are input into the linear shift register, the linear shift register generates different excitation vectors with the bit width of lambda-2 in each clock cycle; λ is the number of interconnect lines in the interconnect network; in the simulation, a 23-bit linear shift register is used, whose characteristic polynomial is f (x) x23+x22+x21+x20+x19+x7In addition, linear shift registers which can arbitrarily generate quasi-random sequences with the bit width of lambda-2 are all used for generating excitation vectors by iUF; controlling the length of the excitation vector and the characteristics of the linear shift register;
the iPU generates a digital signature for each chip by using the uncertainty of crosstalk signals caused by the uncertainty of the manufacturing of the interconnection lines; the role of the interconnection network is to maximize the uncertainty of crosstalk signals between interconnection lines; the interconnection network is composed of lambda long interconnection lines which are arranged in parallel, wherein two interconnection lines are disturbed lines, the rest lambda-2 interconnection lines are attack lines, and the two sides of each disturbed line share (lambda-2)/2 attack lines; the input end of the disturbed wire is connected with the system clock of the control unit, and the output end of the disturbed wire is connected with the digital signature generator; the input end of the attack line is connected with a lambda-2 bit output bit in the linear shift register, and the output of the linear shift register is used as an excitation vector of the interconnection line network; due to the fact that coupling capacitors and coupling inductors exist among the interconnection lines, when an excitation vector is transmitted on the attack line, coupling current and coupling voltage appear on the disturbed line, and finally the time of a clock signal transmitted along the disturbed line reaching the digital signature generator is influenced; due to the existence of manufacturing uncertainty, the action size of an attack line on a disturbed line in each chip is different, and the digital signature generator can generate different signals; the response of the manufacturing uncertainty to each excitation vector is different, and the iUF generates digital signatures with different lengths by changing the value and the number of the excitation vectors; two disturbed wires are driven by a clock, and the other attacked wires are driven by a linear shift register; in order to reduce the influence of the load on crosstalk signals, the terminals of the two disturbed wires are connected to a digital signature generator with a symmetrical structure; the terminal of the attack line is connected with the buffer array; therefore, the size of the crosstalk signals on the two disturbed wires is determined by the manufacturing uncertainty of the excitation vectors and the interconnection wires; in addition, a particular input vector should produce enough crosstalk signal uncertainty between the two victim wires of different chips to make the iPUF generated digital signature sufficiently unique and to distinguish between all chips;
the load buffer array is connected with an attack line terminal in the interconnection line network, so that the attack lines have the same load on one hand, and the interference of signals transmitted by the attack lines on other signals in the circuit is reduced on the other hand;
the digital signature generator is a latch based on a NAND gate and consists of two NAND gates; the digital signature generator is used as a speed comparison circuit for comparing the speed of clock signals transmitted along two disturbed wires reaching the digital signature generator; the outputs of the two-input NAND gates are respectively connected with the input of the other NAND gate, and the other input ends of the two NAND gates are connected with the two disturbed wires in the interconnection line network; when the clock signals are transmitted to the digital signature generator along the two disturbed wires, the time for the two clock signals to reach the digital signature generator is different due to the crosstalk signals of the interconnection wire network; when iPUF is not working, the digital signature generator output remains constant '1'; if the rising edge of the victim wire 1 is earlier than that of the victim wire 2, the output of the digital signature generator is '0', otherwise, the output is '1'; on the falling edge of the clock, digital signature generationThe device is reset to an initial state '1'; this reset operation ensures that there is no relationship between two adjacent outputs; if the linear shift register in the iPUF is K-th order, for a given input signal, the linear shift register generates an arbitrary length less than 2K-1 excitation vector, digital signature generator generating an arbitrary length less than 2K-a digital signature of 1;
interconnect manufacturing uncertainty is not a determining factor for digital signatures; the size of the crosstalk signal is also influenced by the rising delay, the falling delay and the charge and discharge factors of a leakage path of the signal, so that the crosstalk signal is difficult to predict or clone, and the physical unclonable structure prevents modeling attack; however, because the adjacent interconnection lines in the interconnection line network have a shielding effect on the victim line, the crosstalk signals generated by the adjacent interconnection lines on the victim line are far larger than the crosstalk signals generated by the attack lines which are spaced farther from the victim line;
in order to make the manufacturing uncertainty of the interconnection line become the main factor for determining the digital signature, the structure of the interconnection line network is improved, so that the signals transmitted on the interference lines positioned at the adjacent positions of the two disturbed lines are the same, namely the input ends of the interference lines at the two sides of the two disturbed lines are respectively connected, and the interference lines have the same excitation signal; at the moment, the excitation vectors of the two disturbed wires are the same, and the magnitude of the disturbed signal on the disturbed wire is mainly determined by the manufacturing uncertainty;
the self-scrambling circuit structure carries out bitwise summation operation on the digital signature generated by each chip, and the result of the summation operation is used as a mask to carry out cyclic exclusive-or operation on the original digital signature; the self-scrambling circuit consists of a counter type mask generator, a nonvolatile memory and a cyclic scrambling circuit;
the input end of the counter type mask generator is the output of the physical unclonable structure iUF based on the interconnection line, the counter type mask generator carries out summation operation on the original output of the iUF, and the operation result is stored in a nonvolatile memory;
the nonvolatile memory is an existing storage structure in the circuit and is used for storing the mask generated by the counting type mask generator; when the iUF works, the nonvolatile memory sends the mask code to the circular scrambling circuit;
the circular scrambling circuit is formed by circularly connecting m registers, and a two-input selector is arranged in front of each register and used for selecting a data source; before each iUF is output, the value of a register in the cyclic scrambling circuit is configured to be a mask value stored in a nonvolatile memory, when the iUF is output, each bit cycle in the cyclic scrambling circuit is subjected to exclusive OR with an original digital signature generated by the iUF, and the exclusive OR value is used as a scrambled digital signature and output; the cyclic scrambling circuit is composed of m triggers connected end to end, the m triggers store the mask code of each chip, the mask code moves to the right in each clock period, each bit is subjected to XOR operation with the corresponding bit in the original digital signature in sequence, the operation result is equivalent to the one-to-one XOR of each m-bit original digital signature and the m-bit mask code, and the output is used as the scrambled digital signature; in the use process of iUF, a control unit loads a mask in a nonvolatile memory into a loop scrambling circuit, wherein when the iUF generates a digital signature, the loop scrambling circuit carries out exclusive OR operation on a Raney digital signature; the operation improves the uniqueness of digital signatures generated by different chips iUF so as to distinguish all the chips;
in an iUF configuration stage, a control unit receives an external iUF enable signal and then outputs a gated clock to control the work of the iUF, and meanwhile, an enable signal is generated for a counter type mask generator to control the counter type mask generator to generate a mask, and then the control unit generates an access address and a write enable signal of a nonvolatile memory and stores the mask in the nonvolatile memory; in the iPFF authentication stage, a control unit generates an access address and a read enable signal of a nonvolatile memory, a mask is loaded into a circular scrambling circuit by using a mask selection signal, then the iPFF is started, and the circular scrambling circuit carries out exclusive OR operation on an original digital signature and the mask generated by the iUFF by using the mask selection signal;
in the working process of iUF, a user inputs an excitation signal as a seed of a linear shift register, and the linear shift register outputs an excitation vector sequence as the input of an interconnection line network; the excitation vector is propagated along lambda-2 attack lines in the interconnection network; signals propagating on the attack line generate crosstalk signals on 2 victim lines, and the size of the crosstalk signals is influenced by excitation vectors and manufacturing uncertainty of interconnection lines; the digital signature generator compares the arrival time of two paths of signals propagating along a disturbed line and generates an '0/1' sequence; the counter type mask generator generates a unique mask for each chip according to the original digital signature generated by each chip, and the cyclic scrambling circuit performs exclusive-OR operation on the original digital signature generated by each chip by using the unique mask of each chip so as to improve the uniqueness of the digital signatures of different chips;
setting p bits in masks with the bit width of m of the two chips to be different, setting q bits in original digital signatures with the bit width of n of the two chips to be different, and setting n-q bits to be the same; in the original digital signature by XOR-ing the original digital signature with a mask
The bit output will be affected, among these affected output bits, wherein
The bits will have the same value flipped to a different value, resulting in improved uniqueness of the iPUF; on the other hand, in the affected bits, there will be
The bit is turned from the original different value to the same value, so that the uniqueness of the iUF is reduced; therefore, the result of the uniqueness boost is shown in equation (1);
the formula (1) shows that the cyclic scrambling circuit has the function of improving the uniqueness under the condition that different bits q/n in all two digital signatures are less than 0.5; for iPUF, the uniqueness of its digital signature is mostly less than 50%; an unstable bit drop in the mask causes a 1/m bit error rate of the scrambled output, and finally causes the stability of iUF to be reduced; for this reason, the value of the mask needs to be saved in non-volatile memory or an off-chip authentication system;
testing by adopting HSPICE 2014 software, wherein a 28nm process library is used for simulation in the testing, and a VCS is used for performing functional simulation on a testing system; verifying the test precision of the test circuit under the manufacturing uncertainty by using a Monte Carlo simulation method in Hspice to generate a 500 iUF sample, wherein the working frequency of iUF is 125 MHz; the model of a device used by the digital signature generator is NAND2X4_ LVT; in the simulation process, the same excitation signal is input to the linear shift registers in 500 iUF samples; the power supply voltage of the iPFA is 1.05V, the working temperature is 25 ℃, and the length of the digital signature is 1024;
inserting a physical unclonable structure and a self-scrambling circuit based on interconnection lines into a standard test circuit ITC benchmark and a 64-bit floating point and graphic unit in a kernel of an OpenSPARCT2 SPARCT core from an open source SPARC processor;
firstly, RTL design and synthesis are carried out on a circuit inserted with iUF by EDA software; laying out and wiring iUF by applying IC Compiler software, carrying out incremental laying out and wiring on an original circuit, and finally generating a circuit layout; obtaining the total area occupied by the physical unclonable structure based on the interconnection line and the self-scrambling circuit after the physical unclonable structure and the self-scrambling circuit are inserted into the reference circuit and the ratio of the on-chip key path time delay measurement system to the total area of the circuit:
next, performing uniqueness analysis on the digital signatures generated by 500 ipufs; the uniqueness of the digital signature is calculated by inputting the same excitation signal to all ipufs and generating the average value of hamming distances between the digital signatures by all ipufs.
2. A physical unclonable structure iUF and a self-scrambling circuit based on an interconnection line are disclosed, and the manufacturing method comprises the following steps:
designing and integrating circuits of an iPF circuit, a self-scrambling circuit and a control unit; initial circuit design, synthesis and netlist generation; the design, synthesis and netlist generation process of the initial integrated circuit is not influenced by iPFF;
laying out and wiring an iPFF circuit and a self-scrambling circuit; the placement and routing requirements of the iPUF circuit are as follows: the interconnection lines in the interconnection line network are arranged in parallel, and the spacing between different interconnection lines is required to be as small as possible so as to increase the coupling effect among the interconnection lines; the distances from the load buffer arrays to different interconnection line terminals are approximately the same, so that the load buffer arrays have the same load; two NAND gates in the digital signature generator are symmetrically placed, so that the distances between the NAND gates and two disturbed lines are the same, and the influence of the line length on signal time delay is reduced;
step three, performing incremental layout and wiring on the initial integrated circuit; the extra area occupied by the number of iUF devices is small, and the influence on the layout and wiring of an initial circuit is small;
step four, flow sheet; the designed test structure is composed of digital devices, and the tape-out process of the test structure is consistent with the tape-out process of a common integrated circuit;
step five, testing; carrying out structural and functional tests on the chip of the tape-out sheet; ensuring that it is free of manufacturing defects;
initializing iUF; completing initial configuration of the iPUF, and generating a mask for improving the output uniqueness of the iPUF; collecting response signals of all chips iUF under different excitation signals;
step seven, authentication is performed in use; and during the use of the integrated circuit, inputting test excitation to the iUF, and contrasting whether the response signal output by the iUF exists in the response signal collected in the step six, if so, proving that the chip is a designed credible chip.
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