CN109840241B - Inter-core communication circuit of heterogeneous dual-core processor - Google Patents

Abstract

The invention belongs to the technical field of computer hardware, and relates to an inter-core communication circuit of a heterogeneous dual-core processor. The circuit comprises a control processor, an operation processor, a dual-core mailbox communication processing module and a shared storage area. The inter-core communication circuit of the heterogeneous dual-core processor is high in efficiency and simple in structure.

Description

Inter-core communication circuit of heterogeneous dual-core processor

Technical Field

The invention belongs to the technical field of computer hardware, and relates to an inter-core communication circuit of a heterogeneous dual-core processor.

Background

Compared with the isomorphic structure, the heterogeneous dual-core processor has the advantages that the internal structure of the processor is optimized by organizing cores with different characteristics, so that the optimization of the performance of the processor is realized. The prior art is mainly based on bus shared Cache architectures, i.e. shared Cache architectures, and on-chip interconnect architectures. The shared Cache architecture refers to each processor core for shared secondary, tertiary caches, or external memory. The processor cores with the structure are not independent in work, and the independent resource sharing of key data calculation cannot be guaranteed. The interconnection structure based on the chip is connected together through a cross switch or a network-on-chip mode, and message communication is carried out among the processor cores. The structure has a complex hardware structure and excessive design cost.

Disclosure of Invention

The purpose of the invention is that: the inter-core communication circuit of the heterogeneous dual-core processor is efficient and simple in structure.

The technical scheme of the invention is as follows: an inter-core communication circuit of a heterogeneous dual-core processor is characterized in that: the circuit comprises a control processor, an operation processor, a dual-core mailbox communication processing module and a shared storage area;

the control processor stores the data to be operated into the shared storage area, and simultaneously sends key information of the data to be operated to the dual-core mailbox communication processing module, wherein the key information comprises a storage address, a length and an operation instruction of the operation data; the dual-core mailbox communication processing module interrupts the operation processor after receiving the key information, the operation processor acquires the key information from the mailbox communication processing module, acquires data to be processed from the shared storage area according to instructions in the key information, transmits an operation result back to the shared storage area after the operation is completed, and simultaneously transmits storage position information of the operation result to the dual-core mailbox communication processing module, the dual-core mailbox communication processing module interrupts the control processor, and the control processor reads the storage position information of the operation result from the dual-core mailbox communication processing module and acquires the operation result from the shared storage area according to the position information.

Preferably, the shared memory area comprises two processor interface units, a semaphore unit and a memory unit;

the two processor interface units are respectively used for providing interfaces for controlling the processor and the operation processor to access the storage unit and the semaphore unit; the semaphore unit is used for indicating whether the processor is accessing the storage unit; the storage unit is used for storing data to be operated and operation results.

Preferably, the dual-core mailbox communication processing module comprises two sets of processor interface units, a FIFO control and status register unit and a FIFO unit; one processor core uses the set of units described above.

The processor interface unit provides interfaces of the processor write FIFO unit, the read FIFO unit, the interrupt processor and the access FIFO control and status register unit; the FIFO control and status register unit is used for reporting a 'pre-full' state when setting how many data are stored in the FIFO, and storing the 'empty', 'full', 'pre-full' state comprising the FIFO; the FIFO unit is used for storing the data information written by the processor and is read by another processor.

The invention has the beneficial effects that: the patent provides a heterogeneous dual-core processor inter-core communication circuit, which provides an information interaction circuit support between a control processor responsible for managing on-chip equipment and a data resolving operation processor. The circuit structure has definite dual-core function division, ensures the independent resource sharing of data calculation, has quick and effective inter-core communication circuit, and meets the requirements of high efficiency and simple structure of heterogeneous dual-core processors.

Drawings

FIG. 1 is a block diagram showing the communication circuit between cores of a heterogeneous dual-core processor

FIG. 2 is a block diagram of a shared memory module circuit configuration

FIG. 3 is a block diagram showing a dual inter-core mailbox communication processing module

Detailed Description

The technical scheme of the invention is clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, and that all other embodiments obtained by a person skilled in the art without making creative efforts based on the embodiments in the present invention are within the protection scope of the present invention.

Taking a heterogeneous dual-core processor inter-core communication circuit as an example, referring to an example of a drawing, the heterogeneous dual-core processor inter-core communication circuit comprises a PowerPC460 processor, a C6713 processor, an on-chip SRAM controller module, a dual-core mailbox communication processing module, a PLB cross bar arbiter module, a shared storage area and PLB slave equipment.

The PowerPC460 processor is required to inquire the signal quantity information of the shared memory area, when the signal quantity information indicates that the shared memory area is not occupied by the C6713 processor, the data to be operated is stored in the shared memory area, and meanwhile, key information of the data to be operated is sent to the dual-core mailbox communication processing module, and the key information comprises a storage address, a length and an operation instruction of the operation data; the storage position information of the operation result can be read from the dual-core mailbox communication processing module, and the operation result is obtained from the shared storage area according to the position information;

the C6713 processor acquires key information from the mailbox communication processing module, acquires data to be processed from the shared storage area according to instructions in the key information, inquires signal quantity information of the shared storage area after operation is completed, sends an operation result back to the shared storage area when the signal quantity information indicates that the shared storage area is not occupied by the PowerPC460 processor, and simultaneously transmits storage position information of the operation result to the dual-core mailbox communication processing module;

the dual inter-core mailbox communication processing module is used for interrupting the C6713 processor after receiving the key information from the PowerPC460 processor, receiving the storage position information of the operation result after the calculation of the C6713 processor is completed, and interrupting the PowerPC460 processor; the system comprises a processor interface 1 unit, a processor interface 2 unit, a FIFO control and status register 1 unit, a FIFO control and status register 2 unit, a FIFO_1 unit and a FIFO_2 unit;

the processor interface 1 unit provides the interface of the PowerPC460 processor write FIFO_1 unit, the read FIFO_2 unit, the interrupt PowerPC460 processor and the access FIFO control and status register 1 unit; the processor interface 2 unit provides a C6713 processor write FIFO_2 unit, a read FIFO_1 unit, interrupts the C6713 processor and accesses the interface of the FIFO control and status register 2 unit; the FIFO control and status register 1 unit and the FIFO control and status register 2 unit are respectively used for reporting a pre-full state when setting how many data are stored in the FIFO_1 unit and the FIFO_2 unit, and respectively storing the empty, full and pre-full states comprising the FIFO_1 unit and the FIFO_2 unit; the FIFO_1 unit is used for storing the data information written by the PowerPC460 processor and reading the data information by the C6713 processor; the FIFO_2 unit is used for storing the data information written by the C6713 processor and reading the data information by the PowerPC460 processor;

the shared memory area comprises two processor interface units, a semaphore unit and a storage unit, wherein the two processor interface units are respectively used for providing interfaces of the PowerPC460 processor and the C6713 processor for accessing the storage unit and the semaphore unit; the semaphore unit is used for indicating whether the current processor is accessing the storage unit; the storage unit is realized by adopting a dual-port memory and is used for storing data to be operated and operation results.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present invention, and not limiting thereof; although the invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (1)

1. An inter-core communication circuit of a heterogeneous dual-core processor is characterized in that: the circuit comprises a control processor, an operation processor, a dual-core mailbox communication processing module and a shared storage area;

the control processor stores the data to be operated into the shared storage area, and simultaneously sends key information of the data to be operated to the dual-core mailbox communication processing module, wherein the key information comprises a storage address, a length and an operation instruction of the operation data; the dual-core mailbox communication processing module interrupts the operation processor after receiving the key information, the operation processor acquires the key information from the mailbox communication processing module, acquires data to be processed from the shared storage area according to instructions in the key information, transmits an operation result back to the shared storage area after the operation is finished, and simultaneously transmits storage position information of the operation result to the dual-core mailbox communication processing module, the dual-core mailbox communication processing module interrupts the control processor, and the control processor reads the storage position information of the operation result from the dual-core mailbox communication processing module and acquires the operation result from the shared storage area according to the position information;

the shared memory area comprises two processor interface units, a semaphore unit and a memory unit;

the two processor interface units are respectively used for providing interfaces for controlling the processor and the operation processor to access the storage unit and the semaphore unit; the semaphore unit is used for indicating whether the processor is accessing the storage unit; the storage unit is used for storing data to be operated and operation results;

the dual-core mailbox communication processing module comprises two sets of processor interface units, a FIFO control and status register unit and a FIFO unit; a processor core using the set of units;

the processor interface unit provides interfaces of the processor write FIFO unit, the read FIFO unit, the interrupt processor and the access FIFO control and status register unit; the FIFO control and status register unit is used for reporting a 'pre-full' state when setting how many data are stored in the FIFO, and storing the 'empty', 'full', 'pre-full' state comprising the FIFO; the FIFO unit is used for storing the data information written by the processor and is read by another processor.

Images