CN109818620B - Reconfigurable Sigma-Delta modulator - Google Patents
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- CN109818620B CN109818620B CN201910066483.8A CN201910066483A CN109818620B CN 109818620 B CN109818620 B CN 109818620B CN 201910066483 A CN201910066483 A CN 201910066483A CN 109818620 B CN109818620 B CN 109818620B
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Abstract
The embodiment of the invention discloses a reconfigurable Sigma-Delta modulator, which comprises: the SAR ADC circuit comprises an input resistor, a feedforward path, a loop filter comprising a multistage operational amplifier connected in series, a 5-bit quantizer with an SAR ADC structure and a feedback loop consisting of a plurality of DACs; the input resistor is a resistance value adjustable resistor, one end of the input resistor is connected with an input signal, and the other end of the input resistor is connected with the input end of the loop filter; the feedforward path is bridged with the output section of the first-stage operational amplifier of the loop filter and the input end of the last-stage operational amplifier of the loop filter; the input end of the quantizer is connected with the output end of the last operational amplifier of the loop filter, and a digital signal is output through the output end; the number of the DACs in the feedback loop corresponds to the number of the operational amplifiers in the loop filter, the input end of each DAC in the feedback loop is connected with the output end of the quantizer, and the output end of each DAC in the feedback loop is connected with the input end of the corresponding operational amplifier in the loop filter.
Description
Technical Field
The invention relates to a wireless communication technology, in particular to a reconfigurable Sigma-Delta modulator.
Background
With the development of wireless communication technology, the requirements on the integration level, power consumption and cost of a chip are higher and higher. For the rf receiver in the wireless communication system architecture, there are several trends in the related art development of the wireless receiver with respect to the aspects of improving the integration level, reducing the power consumption and the design cost: firstly, a large number of signal processing functions are implemented in a digital circuit; secondly, in order to reduce hardware cost and power consumption, an analog circuit is integrated, and multiple functions are realized in a single circuit as much as possible; finally, for a multi-mode communication system, the reconfigurable design of the circuit is a scheme for saving hardware overhead and optimizing energy efficiency, and in order to meet different application scenarios, the reconfigurable design of each module is increasingly required.
Aiming at the technical development, in the wireless communication technology, the continuous-time sigma-delta modulator has a good anti-aliasing effect, and a front-end anti-aliasing filter can be saved; in addition, the continuous time sigma-delta modulator can reduce the requirement of a system on the operational amplifier speed in the integrator, has obvious power consumption and speed advantages, and is suitable for broadband application occasions. Therefore, more and more radio frequency receivers are used to realize the analog-to-digital conversion function, but the related art does not fully utilize the architectural advantages of the continuous time sigma-delta modulator circuit, and cannot further improve the integration level, reduce the hardware cost and reduce the power consumption.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention desirably provide a reconfigurable Sigma-Delta modulator, which is compatible with functions of an analog filter and a programmable gain amplifier VGA in a radio frequency receiver channel, and further omits two circuits related to the filter and the VGA in the radio frequency receiver; and the continuous time sigma-delta modulator is subjected to reconfigurable design, so that different bandwidths can be configured through software in different application occasions. Therefore, the method can not only meet various application scenes, but also improve the system integration level of the radio frequency receiver and reduce the hardware cost and the power consumption.
The technical scheme of the invention is realized as follows:
the embodiment of the invention provides a reconfigurable Sigma-Delta modulator, which is characterized by comprising the following components: the system comprises an input resistor, a feedforward path, a loop filter comprising a multistage operational amplifier connected in series, a 5-bit quantizer with a successive approximation register type analog-to-digital converter (SAR ADC) structure and a feedback loop consisting of a plurality of digital-to-analog converters (DACs);
the input resistor is a resistor with an adjustable resistance value, one end of the input resistor is connected with an input signal, and the other end of the input resistor is connected with the input end of the loop filter;
the feed-forward path is connected across the output section of the first-stage operational amplifier of the loop filter and the input end of the last-stage operational amplifier of the loop filter, and is used for adjusting the signal transmission function of the Sigma-Delta modulator;
the input end of the quantizer is connected with the output end of the last operational amplifier of the loop filter, and a digital signal is output through the output end;
the number of the DACs in the feedback loop corresponds to the number of the operational amplifiers in the loop filter, the input end of each DAC in the feedback loop is connected with the output end of the quantizer, and the output end of each DAC in the feedback loop is connected with the input end of the corresponding operational amplifier in the loop filter.
The embodiment of the invention provides a reconfigurable Sigma-Delta modulator; by arranging the adjustable input resistor and the adjustable capacitor, the filter is compatible with the functions of an analog filter and a VGA (programmable gain amplifier) in a radio frequency receiver channel, and two circuits of the filter and the VGA in the radio frequency receiver are omitted; the continuous time sigma-delta modulator can be subjected to reconfigurable design, so that different bandwidths can be configured through software in different application occasions. Therefore, the method can not only meet various application scenes, but also improve the system integration level of the radio frequency receiver and reduce the hardware cost and the power consumption.
Drawings
Fig. 1 is a schematic diagram of a general architecture of a radio frequency receiver according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a reconfigurable Sigma-Delta modulator according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another reconfigurable Sigma-Delta modulator according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a quantizer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an adjustable resistor according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an adjustable capacitor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a signal transfer function according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a noise transfer function according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Referring to fig. 1, a general architecture of a radio frequency receiver, which can be universally applied to a radio frequency receiver device, according to an embodiment of the present invention is shown, and the architecture may include a plurality of components disposed between a radio frequency input RF _ in and a baseband output, which in turn include a Low Noise Amplifier (LNA), a mixer, an Analog filter, a programmable Variable Gain Amplifier (VGA), an Analog-to-Digital Converter (ADC), and a Digital filter. Among these components, the mixer may shift the rf signal amplified by the lna according to the frequency of a Local Oscillator (LO). Generally, the frequency of the output signal of the mixer is higher than that of the rf signal, and the mixer is called an up-conversion mixer; the frequency of the output signal of the mixer is lower than the frequency of the rf signal, and the mixer is called a down-conversion mixer. In a common radio frequency receiver architecture, the mixer is typically a down-conversion mixer.
The analog filter can eliminate high-frequency noise and interference in a signal path before ADC conversion, and avoid aliasing noise from polluting signals; in addition, the influence of an overdrive signal outside the bandwidth of the filter on a signal path can be eliminated, and the phenomenon of modulator saturation of an ADC (analog to digital converter) is avoided; and when input overvoltage occurs, the analog filter can limit input current and attenuate input voltage.
The digital Filter is arranged behind the ADC, and can remove digital noise injected during the analog-to-digital conversion process, and generally, the digital Filter may be a bandpass Filter formed by a Low Pass digital Filter (LPF) and a High Pass digital Filter (HPF) connected in series.
For the general architecture shown in fig. 1, the analog-to-digital conversion function can be implemented by a continuous-time sigma-delta modulator. The continuous time sigma-delta modulator is based on the over-sampling and noise shaping theory, removes the quantization noise in the frequency band to the outside of the frequency band through a loop filter, and eliminates the quantization noise through a digital decimation filter. However, the related art can only replace the ADC with the analog-to-digital conversion function of the continuous-time sigma-delta modulator, but does not deeply utilize the structural features of the continuous-time sigma-delta modulator. Based on this, referring to fig. 2, an embodiment of the present invention provides a reconfigurable structure of a Sigma-Delta modulator 2, where the Sigma-Delta modulator 2 not only can implement analog-to-digital conversion functions, but also can implement VGA and analog filter functions, and the Sigma-Delta modulator 2 may include: an input resistor 21, a feedforward path 22, a loop filter 23 including a multistage operational amplifier 231 connected in series, a 5-bit quantizer 24 of a Successive AppRoximation register Analog-to-Digital Converter (SAR ADC) structure, and a feedback loop 25 composed of a plurality of Digital-to-Analog converters (DACs) 251;
the input resistor 21 is a resistance value adjustable resistor, one end of the input resistor 21 is connected to an input signal, and the other end of the input resistor 21 is connected to the input end of the loop filter 23;
the feedforward path 22 is connected across the output section of the first stage operational amplifier of the loop filter 23 and the input end of the last stage operational amplifier of the loop filter 23, and the feedforward path 22 is used for adjusting the signal transfer function of the Sigma-Delta modulator 2;
the input end of the quantizer 24 is connected to the output end of the last operational amplifier of the loop filter 23, and outputs a digital signal through the output end;
the number of DACs in the feedback loop 25 corresponds to the number of operational amplifiers in the loop filter 23, the input terminal of each DAC 251 in the feedback loop 25 is connected to the output terminal of the quantizer 24, and the output terminal of each DAC 251 in the feedback loop 25 is connected to the input terminal of the corresponding operational amplifier 231 in the loop filter 23.
For the technical solution shown in fig. 2, since the input resistor 21 is adjustable, different resistance values can be selected for the input resistor 21, so as to realize gain adjustment corresponding to each resistance value, thereby realizing VGA function in the Sigma-Delta modulator 2, and not changing ADC signal transfer function and noise transfer function, therefore, in the general architecture of the radio frequency receiver shown in fig. 1, if the Sigma-Delta modulator 2 shown in fig. 2 is used to realize analog-to-digital conversion, the VGA circuit can be omitted in the architecture of the radio frequency receiver. Furthermore, since the feed-forward path 22 can change the signal transfer function of the modulator, a notch (null) can be created out of band, thereby increasing the rejection of out-of-band interfering signals; by adjusting the feed-forward path 22, null can be changed to selectively suppress the interference signal in a certain frequency band, that is, to implement the function of the analog filter, so that in the radio frequency receiver architecture shown in fig. 1, the analog filter can be eliminated or the requirement for the analog filter can be reduced. Compared with the quantizer of the flash ADC commonly used at present, the 5-bit quantizer 24 of the SAR ADC structure has obvious advantages in power consumption and area, and can compensate Excessive Loop Delay (ELD) according to requirements, so that a DAC circuit is further saved, and the area and the power consumption can be further reduced.
For the Sigma-Delta modulator 2 shown in fig. 2, in one possible implementation, the loop filter 23 is preferably a third-order active RC structure, and specifically, the loop filter 23 includes a three-stage operational amplifier, three pairs of capacitors, and three pairs of adjustable resistors; each pair of adjustable capacitors corresponds to one operational amplifier, and each pair of adjustable capacitors is bridged with the input end and the output end of the corresponding operational amplifier; in the three pairs of resistors, a first resistor pair is connected across the output end of the first operational amplifier and the input end of the second operational amplifier, a second resistor pair is connected across the output end of the second operational amplifier and the input end of the third operational amplifier, and a third resistor pair is connected across the input end of the second operational amplifier and the output end of the third operational amplifier.
Based on the above implementation, the operational amplifier in the loop filter 23 may preferably be a two-input and two-output operational amplifier. In correspondence to the operational amplifier with two-way input and two-way output, referring to fig. 3, the input resistor 21 preferably includes a pair of input resistors R1, wherein one end of one input resistor R1 is connected to the first input signal VIN _ P, and the other end is connected to the positive input end of the first operational amplifier OP1 of the loop filter 23; one end of the other input resistor R1 is connected to the second input signal VIN _ N, and the other end is connected to the negative input end of the first operational amplifier OP1 of the loop filter 23.
In correspondence to the dual-input dual-output operational amplifier, referring to fig. 3, the feed-forward path 22 includes an adjustable capacitor pair C4, wherein one adjustable capacitor C4 is connected across the negative output terminal of the first operational amplifier OP1 of the loop filter 23 and the negative output terminal of the third operational amplifier OP3 of the loop filter 23, and the other adjustable capacitor C4 is connected across the positive output terminal of the first operational amplifier OP1 of the loop filter 23 and the positive output terminal of the third operational amplifier OP3 of the loop filter 23.
For each adjustable capacitor pair of the loop filter 23, corresponding to the operational amplifier with dual input and dual output, one of the adjustable capacitors is connected across the positive input end and the negative output end of the corresponding operational amplifier, and the other adjustable capacitor is connected across the negative input end and the positive output end of the corresponding operational amplifier; referring to fig. 3, one adjustable capacitor C1 of the first adjustable capacitor pair C1 is connected across the positive input terminal and the negative output terminal of the first operational amplifier OP1, and the other adjustable capacitor C1 is connected across the negative input terminal and the positive output terminal of the first operational amplifier OP 1; one adjustable capacitor C2 of the second adjustable capacitor pair C2 is bridged at the positive input end and the negative output end of the second operational amplifier OP2, and the other adjustable capacitor C2 is bridged at the negative input end and the positive output end of the second operational amplifier OP 2; one adjustable capacitor C3 of the third adjustable capacitor pair C3 is bridged over the positive input end and the negative output end of the third operational amplifier OP3, and the other adjustable capacitor C3 is bridged over the negative input end and the positive output end of the third operational amplifier OP 3; it can be understood that, due to the adoption of the adjustable capacitor, the capacitance value of the adjustable capacitor can be configured according to the bandwidth, so that the reconfiguration of the communication mode is realized.
For the three pairs of resistors of the loop filter 23, referring to fig. 3, one resistor R2 of the first resistor pair R2 is connected across the negative output terminal of the first operational amplifier OP1 and the positive input terminal of the second operational amplifier OP2, and the other resistor R2 of the first resistor pair R2 is connected across the positive output terminal of the first operational amplifier OP1 and the negative input terminal of the second operational amplifier OP 2;
one resistor R3 of the second resistor pair R3 is bridged between the negative output end of the second operational amplifier OP2 and the positive input end of the third operational amplifier OP3, and the other resistor R3 of the second resistor pair R3 is bridged between the positive output end of the second operational amplifier OP2 and the negative input end of the third operational amplifier OP 3;
one resistor R4 of the third resistor pair R4 is connected across the positive input terminal of the second operational amplifier OP2 and the positive output terminal of the third operational amplifier OP3, and the other resistor R4 of the third resistor pair R4 is connected across the negative input terminal of the second operational amplifier OP2 and the negative output terminal of the third operational amplifier OP 3.
Corresponding to the operational amplifier with dual input and dual output, referring to fig. 3, the number of DACs in the feedback loop 25 is 3, the positive output terminal of the first DAC (DAC 1) is connected to the negative input terminal of the first operational amplifier OP1, and the negative output terminal of the first DAC (DAC 1) is connected to the positive input terminal of the first operational amplifier OP 1; the positive output end of the second DAC (DAC 2) is connected with the positive input end of the second operational amplifier OP2, and the negative output end of the second DAC (DAC 2) is connected with the negative input end of the second operational amplifier OP 2; the positive output terminal of the third DAC (DAC 3) is connected to the negative input terminal of the third operational amplifier OP3, and the negative output terminal of the third DAC (DAC 3) is connected to the positive input terminal of the third operational amplifier OP 3.
In response to the dual input and dual output operational amplifier, referring to fig. 3, the positive input terminal of the quantizer 24 is connected to the negative output terminal of the third operational amplifier OP3 of the loop filter 23; a negative input terminal of the quantizer 24 is connected to a positive output terminal of the third operational amplifier OP3 of the loop filter 23.
For the Sigma-Delta modulator 2 shown in fig. 2, in one possible implementation, see fig. 4, the quantizer 24 comprises: a Switched Capacitor digital-to-analog converter (SC-DAC), a dual-input dual-output comparator (Comp), a SAR Logic, a reference voltage buffer (REF BUF), and a delay unit (Z) -1 And a Binary to Thermometer code circuit (B2T); the SC-DAC receives an input signal Vin and a reference voltage transmitted by a REF BUF, transmits an output analog signal to Comp, and transmits the output to SAR Logic by Comp; SARLogic feeds back the output SAC Code to SC-DAC, and SAR Logic feeds back the output digital signal D through a time delay Z -1 Compensating the ELD coding Code obtained after time delay to the SC-DAC; the SAR Logic also converts the output signal D into a time sequence signal T through B2T, and then data output Dataout is carried out.
For the above technical solution, preferably, the adjustable resistor and the adjustable capacitor are both devices that are adjusted based on a digital control word. Referring to fig. 5 for a representative embodiment of the adjustable resistor, taking the input resistor pair R1 as an example, the resistors R101 to R110 can be selectively added in series to the fixed resistor R _ fix by opening the associated bypass switches sw <1> to sw <10 >; selectively removing resistors R101 through R110 from the input resistor R1 by closing the associated bypass switch; and R101 is connected with a switch sw <0> in series, so that the access of the whole resistor string is controlled. As described above, the resistors R101-R110 may be binary weighted, with the switches being controlled by binary values. It will be appreciated by those skilled in the art that digitally controlled adjustable resistors may be implemented in other ways.
Referring to one representative embodiment described with respect to tunable capacitance in fig. 6, the capacitance values of 6 capacitors are increased in a binary manner, with the capacitances selected by applying a binary code to the bit switches corresponding to each capacitance.
By means of the technical solution, the Sigma-Delta modulator 2 shown in fig. 2 and fig. 3 has the following advantages in implementation:
first, the resistance of the input resistor R1 is adjustable, and referring to one embodiment of the adjustable resistor shown in fig. 5, by selecting different values, gain adjustment of 0dB to 10dB, for example, 2dB per step, can be achieved. Due to the fact that adjustability of the input resistor R1 is added, the Sigma-Delta modulator 2 has the VGA function and does not change the ADC signal transfer function and the noise transfer function, and therefore a VGA circuit can be omitted in the radio frequency receiver.
Secondly, the feedforward path C4 is added, and the use of the feedforward path C4 can change the signal transmission function of the Sigma-Delta modulator 2, so that a notch (null) can be generated out of band to increase the suppression of an out-of-band interference signal; by adjusting the size of C4 in the embodiment shown in fig. 6, the null position can be changed, and thus, the interference signal in a certain frequency band can be selectively suppressed, so that the function of the filter is realized, and the analog filter is removed from the radio frequency receiver or the requirement for the analog filter is reduced.
And then, a 5-bit SAR ADC is used as a quantizer, compared with a flash ADC used in a conventional scheme as the quantizer, the SAR ADC has obvious advantages in power consumption and area when being used as the quantizer, ELD compensation can be integrated, a DAC circuit can be saved, and the area and the power consumption are further reduced.
Finally, configuring the capacitance value through software to realize the reconfiguration of the mode, for example, setting the minimum bandwidth of the Sigma-Delta modulator 2 to be 10MHz, and the maximum bandwidth to be 20MHz, and as explained with the embodiment shown in fig. 6, in each bandwidth mode, the calibration bit of the capacitance is 5 bits, and assuming that the calibration value of the capacitance is 10000, when the bandwidth is 20MHz mode, the clock frequency is 320mhz, dout is 5 > =010000; when the bandwidth is 10M Hz mode, the clock frequency is 160MHz, dout & lt 5 & gt =100000; when the bandwidth is between 10M Hz and 20MHz, only the clock frequency needs to be changed in equal proportion, and the capacitance control word dout <5:0> needs to be scaled in equal proportion.
The following description will be made with reference to a Signal Transfer Function (STF) of the Sigma-Delta modulator 2 shown in fig. 7 and a Noise Transfer Function (NTF) diagram shown in fig. 8.
In fig. 7, the solid line is the STF with gain =0dB, the dashed line is the STF with gain =20dB, and as can be seen from fig. 7 and fig. 8, taking the bandwidth of 10MHZ as an example, the signal gain range is 0dB to 20dB, and the change in gain does not affect the noise transfer function and the STF; under the condition that the in-band attenuation is not more than 0.5dB, the attenuation effect of 9dB is obtained at the position of 2 times of signal bandwidth, and the inhibition effect brought by the out-of-band null is more obvious.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A reconfigurable Sigma-Delta modulator, comprising:
the system comprises an input resistor, a feedforward path, a loop filter comprising a multistage operational amplifier connected in series, a 5-bit quantizer with a successive approximation register type analog-to-digital converter (SAR ADC) structure and a feedback loop consisting of a plurality of digital-to-analog converters (DAC);
the input resistor is a resistor with an adjustable resistance value, one end of the input resistor is connected with an input signal, and the other end of the input resistor is connected with the input end of the loop filter;
the feedforward path is connected with the output end of the first-stage operational amplifier of the loop filter and the input end of the last-stage operational amplifier of the loop filter in a cross mode, and the feedforward path is used for adjusting the signal transmission function of the Sigma-Delta modulator;
the input end of the quantizer is connected with the output end of the last operational amplifier of the loop filter, and a digital signal is output through the output end;
the number of the DACs in the feedback loop corresponds to the number of the operational amplifiers in the loop filter, the input end of each DAC in the feedback loop is connected with the output end of the quantizer, and the output end of each DAC in the feedback loop is connected with the input end of the corresponding operational amplifier in the loop filter;
the quantizer includes: the circuit comprises a switched capacitor digital-to-analog converter SC-DAC, a double-input double-output comparator Comp, a SAR Logic, a reference voltage buffer REF BUF and a delayer Z -1 And a binary code to thermometer code circuit B2T; the SC-DAC receives an input signal Vin and a reference voltage transmitted by a REF BUF, transmits an output analog signal to a Comp, and transmits an output to the SAR Logic; the SAR Logic feeds back the output SAC Code to the SC-DAC, and the SAR Logic outputs the output digital signal D through a time delay device Z -1 Compensating the excessive loop delay ELD coding Code obtained after delaying to the SC-DAC; the SAR Logic also converts the output signal D into a time sequence signal T through B2T and then outputs data out.
2. The Sigma-Delta modulator of claim 1, wherein the loop filter comprises a three-stage operational amplifier, three pairs of capacitors, and three pairs of adjustable resistors; each pair of adjustable capacitors corresponds to one operational amplifier, and each pair of adjustable capacitors is bridged with the input end and the output end of the corresponding operational amplifier; in the three pairs of resistors, a first resistor pair is connected across the output end of the first operational amplifier and the input end of the second operational amplifier, a second resistor pair is connected across the output end of the second operational amplifier and the input end of the third operational amplifier, and a third resistor pair is connected across the input end of the second operational amplifier and the output end of the third operational amplifier.
3. The Sigma-Delta modulator of claim 2, wherein the input resistor comprises a pair of input resistors corresponding to the operational amplifier being a two-input two-output operational amplifier, one of the input resistors being connected to the first input signal at one end and to the forward input of the first operational amplifier of the loop filter at the other end; one end of the other input resistor is connected with a second input signal, and the other end of the other input resistor is connected with the negative input end of the first operational amplifier of the loop filter.
4. The Sigma-Delta modulator of claim 2, wherein the feed-forward path comprises a pair of adjustable capacitors, one of the adjustable capacitors coupled across the negative output terminal of the first operational amplifier of the loop filter and the negative input terminal of the third operational amplifier of the loop filter, and the other adjustable capacitor coupled across the positive output terminal of the first operational amplifier of the loop filter and the positive input terminal of the third operational amplifier of the loop filter, corresponding to the operational amplifier being a two-input two-output operational amplifier.
5. The Sigma-Delta modulator of claim 2, wherein for each adjustable capacitance pair of the loop filter corresponding to the operational amplifier being a two-input two-output operational amplifier, one of the adjustable capacitances is connected across the positive input terminal and the negative output terminal of the corresponding operational amplifier, and the other adjustable capacitance is connected across the negative input terminal and the positive output terminal of the corresponding operational amplifier.
6. The Sigma-Delta modulator of claim 2, wherein for three pairs of resistors of the loop filter, corresponding to the operational amplifier being a two input, two output operational amplifier: one resistor in the first resistor pair is bridged between the negative output end of the first operational amplifier and the positive input end of the second operational amplifier, and the other resistor in the first resistor pair is bridged between the positive output end of the first operational amplifier and the negative input end of the second operational amplifier;
one resistor of the second resistor pair is in bridge connection with the negative output end of the second operational amplifier and the positive input end of the third operational amplifier, and the other resistor of the second resistor pair is in bridge connection with the positive output end of the second operational amplifier and the negative input end of the third operational amplifier;
one resistor of the third resistor pair is connected across the positive input end of the second operational amplifier and the positive output end of the third operational amplifier, and the other resistor of the third resistor pair is connected across the negative input end of the second operational amplifier and the negative output end of the third operational amplifier.
7. The Sigma-Delta modulator of claim 2, wherein the number of DACs in the feedback loop is 3 corresponding to the operational amplifier being a dual input, dual output operational amplifier, wherein the positive output terminal of the first DAC is connected to the negative input terminal of the first operational amplifier and the negative output terminal of the first DAC is connected to the positive input terminal of the first operational amplifier; the positive output end of the second DAC is connected with the positive input end of the second operational amplifier, and the negative output end of the second DAC is connected with the negative input end of the second operational amplifier; and the positive output end of the third DAC is connected with the negative input end of the third operational amplifier, and the negative output end of the third DAC is connected with the positive input end of the third operational amplifier.
8. The Sigma-Delta modulator of claim 2, wherein the quantizer has a positive input coupled to the negative output of the third operational amplifier of the loop filter in response to the operational amplifier being a two input, two output operational amplifier; and the negative input end of the quantizer is connected with the positive output end of the third operational amplifier of the loop filter.
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| CN110995272A (en) * | 2019-12-25 | 2020-04-10 | 重庆大学 | Switched capacitor resistance feedback continuous time modulator based on variable resistor |
| US11626885B1 (en) | 2021-11-30 | 2023-04-11 | Analog Devices, Inc. | Gain programmability techniques for delta-sigma analog-to-digital converter |
| CN114200995A (en) * | 2021-12-10 | 2022-03-18 | 上海富芮坤微电子有限公司 | Reference voltage generating circuit and Sigma Delta modulator |
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| US9537497B2 (en) * | 2015-05-14 | 2017-01-03 | Mediatek Inc. | Continuous time delta sigma modulator, analog to digital converter and associated compensation method |
| WO2017037744A2 (en) * | 2015-09-03 | 2017-03-09 | Indian Institute Of Technology Madras | A delta sigma modulator with noise attenuating feedback filters |
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