CN109815605A

CN109815605A - A kind of circuit system construction method for single particle effect emulation

Info

Publication number: CN109815605A
Application number: CN201910091118.2A
Authority: CN
Inventors: 刘毅; 吴汉鹏; 徐长卿; 杨帆; 杨银堂
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2019-01-30
Filing date: 2019-01-30
Publication date: 2019-05-28
Anticipated expiration: 2039-01-30
Also published as: CN109815605B

Abstract

The present invention provides a kind of circuit system construction method for single particle effect emulation, method includes the following steps: step 1: determining the module that circuit system is included；Step 2: the different levels functional mode of all functional modules is established；Step 3: the interface between different levels functional mode is write；Step 4: determining the module for needing to carry out single-particle direct fault location, and configure and obtain circuit system mixed model under this condition, carries out single-particle direct fault location so as to treat injection module, and carry out simulation analysis to whole system.The present invention, which realizes circuit system simulation model, can carry out single-particle direct fault location to particular module therein again while executing program, significant to the single particle effect emulation of research system.

Description

A kind of circuit system construction method for single particle effect emulation

Technical field

The invention belongs to single particle effect research fields, are related to a kind of circuit system establishment for single particle effect emulation Method is particularly suitable for the simulation study that related researcher carries out single particle effect to circuit system.

Background technique

Single particle effect is a key factor for influencing aerospace applications IC reliability, some aerospace applications systems If spaceborne computer SiP (System-in-Package) is due to encapsulation characteristic, it is unable to complete radiation effect ground simulation test, It needs to radiate emulation in the preceding single particle effect that carries out it of SiP sky day application, to assess its anti-list for whether meeting aerospace applications Particle effect index.

Device level and circuit-level are mainly also rested on to the research of single particle effect emulation at present.Device level single particle effect The mechanism of action of the main research single-particle of emulation in the devices, the single particle effect emulation of circuit-level is only for small scale in circuitry Such as the SPICE netlist circuit of logic gate, it is unable to satisfy the demand emulated to large scale integrated circuit system single particle effect. Currently, there is not yet can carry out setting up to realize single-particle direct fault location and system emulation for circuit system mixed model Method.

Summary of the invention

The present invention provides a kind of circuit system construction method for single particle effect emulation, can be directed to circuit to realize Different modules carries out single-particle direct fault location in system, and carries out simulation analysis to system.

This is used for circuit system construction method that single particle effect emulates

Step 1: circuit system to be emulated is divided by function as multiple modules；

Step 2: it is directed to each module, establishes its different levels functional mode, including RTL model and SPICE mould respectively Type obtains corresponding model file；

Step 3: for all possible connection between modules, connecing between different levels functional mode is write Mouthful, including between RTL model and RTL model functionally signal connection, mapping example of the SPICE model in RTL model with And signal connection functionally, every kind of connection relationship form an interface code file；

Step 4: it determines the module for needing to carry out single-particle direct fault location, and is configured by script, call corresponding model File and interface code file obtain circuit system top-level module file；In the top-level module file, module to be implanted is matched It is set to SPICE model, other modules are each configured to RTL model, and are configured with correct interface, to complete to be used for single-particle The circuit system of effect emulation is set up.

It based on this, treats injection module and carries out single-particle direct fault location, and simulation analysis is carried out to whole system.Utilize Circuit-level single particle effect single-particle fault filling method, the SPICE model for treating injection module enter single-particle direct fault location. It is emulated to containing by the system of single-particle direct fault location module, the single-particle direct fault location in analysis module is to system It influences.

Further, in step 1, circuit system to be emulated can be divided into processor, ahb bus and memory.Institute Different types of memory, including Flash and SRAM can be also further divided into according to concrete function by stating memory.

Further, in step 2, for processor and bus, its RTL model is initially set up, obtains gate leve mould after comprehensive Type is further converted to SPICE pipe grade model；For memory, its RTL model is initially set up, and provide by technique manufacturer File and tool, obtain its SPICE pipe grade model.

Further, in step 3, in order to realize the connection of ahb bus Yu FLASH, ahb bus and SRAM, increase by one Memory management module, slave of the memory management module as ahb bus, connect with FLASH and SRAM.

Further, for step 4 is using SRAM as module to be implanted, then the model file that selects are as follows: processor RTL model file, the RTL model file of bus, the RTL model file of Flash and SRAM SPICE model file；Interface Code file are as follows: processor to bus is the interface code file of RTL to RTL, and bus to Flash is the interface generation of RTL to RTL Code file, bus to SRAM are the interface code file of RTL to SPICE.

The invention has the following advantages:

Circuit system construction method proposed by the present invention can according to need adjustment at any time and select module to be implanted, thus Single-particle direct fault location can be carried out to the disparate modules in system, and the single particle effect in simulation study modules is to whole The influence of a system.

The present invention realizes circuit system simulation model and can carry out again to particular module therein while executing program Single-particle direct fault location, it is significant to the single particle effect emulation of research system.

Detailed description of the invention

Fig. 1 is configurable system module circuit composition.

Fig. 2 is that the circuit system model using SRAM as module to be implanted forms.

Fig. 3 is the circuit system simulation model comprising single-particle direct fault location.

Fig. 4 is the circuit system mixed model simulation flow comprising single-particle direct fault location.

Specific embodiment

Below in conjunction with attached drawing, the circuit system construction method for single particle effect emulation of the invention is made further detailed It states.

Step 1: the module that circuit system is included is determined.As shown in Figure 1, the circuit system include processor, bus, Flash,SRAM.Wherein processor is the 32 bit processor leon based on SPRAC V8 framework, and bus is to meet what AMBA was standardized Bus, Flash size are 512x16bit, and SRAM size is 512x16bit.

Step 2: the different levels functional mode of all modules is established.As shown in Figure 1, being established for processor and bus Its RTL model obtains gate-level model after comprehensive, is further converted to SPICE pipe grade model.For Flash and SRAM, build respectively Its RTL model, and the file and tool provided by technique manufacturer are provided, its SPICE pipe grade model is obtained.The file finally obtained is such as Shown in table 1:

1 circuit system model file of table composition

Step 3: writing the interface between different levels functional mode, including functionally connection and digital and analogue signals Conversion.Wherein, the connection of connection predominantly functionally between RTL and RTL；And the connection between RTL to SPICE first has to reality The conversion of existing signal, the specifically grammar request based on AMSD hybrid simulation tool, are mapped as RTL model for SPICE model, then The RTL model that mapping obtains is connect with the RTL model of other modules.Such as to realize bus RTL model (VHDL description) with The connection of SRAM SPICE model, the method is as follows:

The SPICE model of SRAM is described as follows:

.SUBCKT S013HD1P_X256Y4D32WEN Q[31]Q[30]Q[29]Q[28]Q[27]Q[26]Q[25]Q [24]Q[23]

+Q[22]Q[21]Q[20]Q[19]Q[18]Q[17]Q[16]Q[15]Q[14]Q[13]

+Q[12]Q[11]Q[10]Q[9]Q[8]Q[7]Q[6]Q[5]Q[4]Q[3]

+Q[2]Q[1]Q[0]D[31]D[30]D[29]D[28]D[27]D[26]D[25]

+D[24]D[23]D[22]D[21]D[20]D[19]D[18]D[17]D[16]D[15]

+D[14]D[13]D[12]D[11]D[10]D[9]D[8]D[7]D[6]D[5]

+D[4]D[3]D[2]D[1]D[0]CLK CEN A[9]A[8]A[7]

+A[6]A[5]A[4]A[3]A[2]A[1]A[0]

…

.ENDS

Establish its RTL mapping model (VHDL description):

Establish the amscf.scs file for RTL model and SPICE model hybrid simulation, content are as follows:

The amscf.scs file realizes SPICE model and the signal of RTL model (VHDL description) is converted.Utilize the party Method can in bus VHDL code direct example SRAM VHDL model, and realize functionally signal connection.

According to all possible connection between processor and bus, bus and multiple memories, different layers are established respectively Interface between secondary model, the example of the mapping model including SPICE model to RTL model and the connection of signal.For reality The connection of existing bus and FLASH, bus and SRAM, increases a memory management module, slave of the module as ahb bus, It is connect with FLASH and SRAM.Every kind of connection relationship forms an interface code file, as shown in table 2:

2 system module circuit interface code file of table

	Processor is to bus	Bus is to Flash	Bus is to SRAM
				The interface of RTL to RTL	√	√	√
The interface of RTL to SPICE	√		√
				The interface of SPICE to RTL	√	√	√
The interface of SPICE to SPICE	√		√

Step 4: it determines the module for needing to carry out single-particle direct fault location, and is configured by script, call corresponding model File and interface code file obtain circuit system top-level module file under this condition.It is to be implanted in the top-level module Module is SPICE model, and other modules are RTL model, and are configured with correct interface.It is using SRAM as injection module Example, the model file of selection are as follows: the RTL model file of processor, the RTL model file of bus, Flash RTL model file And the SPICE model file of SRAM, interface code file are as follows: processor to bus is the interface document of RTL to RTL, bus The interface document for being RTL to RTL to Flash, bus to SRAM are the interface document of RTL to SPICE.The electricity obtained under this condition Road system model is as shown in Figure 2:

Step 5: it treats injection module and carries out single-particle direct fault location, and simulation analysis is carried out to whole system.For example, Using SRAM as module to be implanted.Single-particle direct fault location is for simulating influence of the single particle effect to SRAM.First with Perl script extracts the sensitive nodes of peripheral circuit and storage unit in the SPICE netlist of SRAM, generates sensitive nodes list. One of sensitive nodes are randomly selected with perl script, VerilgoA current source model is called to carry out the injection of random time, It include to be obtained into the SPICE netlist of SRAM by the single-particle direct fault location file of generation and at raw single-particle direct fault location file To the SPICE netlist model of the SRAM comprising single-particle direct fault location.Entire simulation model is as shown in Figure 3.

It is emulated to containing by the system of single-particle direct fault location module, simulation flow is as shown in figure 4, first need to The initialization program and operation program for wanting processor to execute are compiled as assembler language by C language, and further compilation is machine code Instruction.By in the machine code instruction deposit FLASH of initialization program, it will run the machine code instruction deposit SRAM's of program In SPICE netlist.Then, respectively in RTL model, it is inserted into data recordin module, records the letter for needing to monitor in simulation process Number value.In SPICE model, voltage measurement sentence is added, records SRAM memory cell and peripheral circuit in simulation process Voltage value.Emulation command is executed, document data record is generated.After emulation, handled with script through single-particle direct fault location It emulates data and does not carry out the emulation data of single-particle direct fault location, shadow of the single-particle direct fault location in analysis module to system It rings.

Claims

1. a kind of circuit system construction method for single particle effect emulation, which comprises the following steps:

Step 2: being directed to each module, establish its different levels functional mode, including RTL model and SPICE model respectively, Obtain corresponding model file；

Step 3: for all possible connection between modules, writing the interface between different levels functional mode, packet Include between RTL model and RTL model signal connection functionally, mapping example and function of the SPICE model in RTL model On signal connection, every kind of connection relationship forms an interface code file；

Step 4: it determines the module for needing to carry out single-particle direct fault location, and is configured by script, call corresponding model file And interface code file, obtain circuit system top-level module file；In the top-level module file, module to be implanted is configured to SPICE model, other modules are each configured to RTL model, and are configured with correct interface, to complete to be used for single particle effect The circuit system of emulation is set up.

2. the circuit system construction method for single particle effect emulation as described in claim 1, it is characterised in that: step 1 In, it is that the circuit system to be emulated is divided into processor, ahb bus and memory.

3. the circuit system construction method for single particle effect emulation as claimed in claim 2, it is characterised in that: step 2 In, for processor and bus, its RTL model is initially set up, obtains gate-level model after comprehensive, is further converted to SPICE pipe Grade model；For memory, its RTL model, and the file and tool provided by technique manufacturer are be provided, it is obtained SPICE pipe grade model.

4. the circuit system construction method for single particle effect emulation as claimed in claim 2, it is characterised in that: described to deposit Reservoir is further divided into different types of memory, including Flash and SRAM according to concrete function.

5. the circuit system construction method for single particle effect emulation as claimed in claim 4, it is characterised in that: step 3 In, in order to realize the connection of ahb bus Yu FLASH, ahb bus and SRAM, increase a memory management module, the storage management Slave of the module as ahb bus, connect with FLASH and SRAM.

6. the circuit system construction method for single particle effect emulation as claimed in claim 4, it is characterised in that: step 4 For using SRAM as module to be implanted, then the model file that selects are as follows: the RTL model of the RTL model file of processor, bus The SPICE model file of file, the RTL model file of Flash and SRAM；Interface code file are as follows: processor is to bus The interface code file of RTL to RTL, bus to Flash are the interface code file of RTL to RTL, and bus to SRAM arrives for RTL The interface code file of SPICE.