CN109814367B - Time-to-digital converter with gating enabling function - Google Patents
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- CN109814367B CN109814367B CN201811639048.1A CN201811639048A CN109814367B CN 109814367 B CN109814367 B CN 109814367B CN 201811639048 A CN201811639048 A CN 201811639048A CN 109814367 B CN109814367 B CN 109814367B
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Abstract
The invention relates to a time-to-digital converter with gating enabling function, comprising: the circuit comprises a ring oscillator circuit, a low-order decoding circuit, a high-order counter circuit, a gating signal generating circuit, a monostable pulse generating circuit, a register array circuit and a serial data output circuit. The time-to-digital converter with the gating enabling function, provided by the invention, is used as a core part of a high-precision time measurement technology, and is widely applied to the fields of laser ranging, biomedical treatment, topographic mapping, aerospace and the like. In recent years, unmanned technology has been developed rapidly, and the key technology applied to the unmanned technology is lidar. The embodiment of the invention can be applied to the laser radar technology and used as a time-to-digital conversion circuit in a large-scale SPAD pixel array to realize high-precision and wide-range measurement of time intervals.
Description
Technical Field
The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a time-to-digital converter with a gating enabling function.
Background
The time-to-digital converter is mainly used for measuring time intervals, converting input analog time interval quantity signals into output digital signals and further realizing digitization of the time intervals.
In recent years, Time of Flight (TOF) distance measurement has been used in three-dimensional imaging, unmanned driving, biomedical, topographic mapping, aerospace and other military and civilian applications. In the TOF ranging method, a Time-to-Digital Converter (TDC) circuit is mainly used to perform quantization conversion of a Time interval signal. Since the advanced level of these technical fields is closely related to the time interval measurement accuracy, the requirements on the measurement dynamic range and measurement resolution of the TDC are also increasing.
At present, the traditional time-to-digital converter mainly has a one-stage structure and a two-stage structure; the resolution of the counter structure and the delay chain structure in the one-stage TDC is limited by the minimum delay of the delay unit in the structure of the TDC, and the requirement of high precision cannot be met; the two-stage TDC is divided into a coarse quantization stage and a fine quantization stage, so that the time measurement precision and the measurement dynamic range are improved, but the occupied area and the power consumption of the structure of the TDC are increased along with the increase of the input dynamic range, and the TDC does not accord with the development trend of low voltage and low power consumption of an integrated circuit.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a time-to-digital converter having a gating enable function. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a time-to-digital converter with a gating enabling function, which comprises: the circuit comprises a ring oscillator circuit, a low-order decoding circuit, a high-order counter circuit, a gate control signal generating circuit, a monostable pulse generating circuit, a register array circuit and a serial data output circuit; wherein the content of the first and second substances,
the ring oscillator circuit is used for outputting a phase node state according to a gating signal and resetting according to an RST signal;
the low bit decoding circuit is used for outputting low bit data according to the state of the phase node;
the high-order counter circuit is used for outputting high-order data according to the state of the phase node and is also used for clearing according to the RST signal;
the gating signal generating circuit is used for generating the gating signal according to the SATRT signal and the STOP signal;
the monostable pulse generating circuit is used for generating the RST signal according to the STOP signal;
the register array circuit is used for storing the high-order data and the low-order data according to the STOP signal and is also used for outputting the high-order data and the low-order data according to the START signal;
the serial data output circuit is used for serially outputting the high-order data and the low-order data which are generated in parallel.
In one embodiment of the invention, the ring oscillator circuit comprises: the device comprises a plurality of inverters I, a plurality of transmission gates TG and a plurality of NAND gates U; wherein the content of the first and second substances,
the phase inverter IjIs passed through the transmission gate TGjThen are respectively connected to the NAND gates UjInput terminal of, said inverter I1jInput terminal of, said inverter Ij+1J is an integer greater than or equal to 1 and less than or equal to 7;
the phase inverter I8Is passed through the transmission gate TG8Then are respectively connected to the NAND gates U8Input terminal of, said inverter I18Input terminal of, said inverter I1An input terminal of (1);
the phase inverter I8Is passed through a transmission gate TG8Is connected to an inverter I1The input of (1);
the NAND gate UkAnother output terminal of the NAND gate U is connected with a power supply voltage VDD, and the NAND gate UmIs connected with the RST signal, k is an integer which is more than or equal to 1 and less than or equal to 4, and m is an integer which is more than or equal to 5 and less than or equal to 8;
the NAND gate UkIs connected to the inverter I1(k+4)An input terminal of (1);
the NAND gate UmIs connected to the inverter I1(m-4)An input terminal of (1);
the transmission gate TGjAnd the transmission gate TG8The control end of the controller inputs the gating signal;
the phase inverter I1jAnd the inverter I18The output of which outputs the phase node state.
In one embodiment of the present invention, the lower decoding circuit includes: inverter I21An inverter I22XOR gate I23XOR gate I24XOR gate I25And an exclusive or gate I26(ii) a Wherein the content of the first and second substances,
the phase inverter I21Is connected with the phase inverter I22An input terminal of (1);
the exclusive-OR gate I24And said I25Is connected with the exclusive-or gate I26An input terminal of (1);
the phase inverter I21Input terminal of, said exclusive or gate I23Input terminal of, said exclusive or gate I24And said exclusive or gate I25The input terminal of (a) inputs the phase node state;
the phase inverter I22Output terminal of, said exclusive or gateI23And said exclusive or gate I26The output terminal of (b) outputs the low bit data.
In one embodiment of the present invention, the high counter circuit includes: a plurality of flip-flops A; wherein the content of the first and second substances,
the trigger A1The C L K input of (a) inputs the phase node state;
the trigger AnIs/are as follows
The output end is connected with the trigger AnD input terminal of and said flip-flop a(n+1)N is an integer of 1 to 11 inclusive.
The trigger A12Is/are as follows
The output end is connected with the trigger A12A D input terminal of (1);
RST input ends of the plurality of flip-flops A are used for inputting RST signals;
and the Q output ends of the flip-flops A are used for outputting the high-order data.
In one embodiment of the present invention, the flip-flop D includes: a plurality of MOS tubes; wherein the content of the first and second substances,
the source electrode of the MOS transistor M1, the source electrode of the MOS transistor M11, the source electrode of the MOS transistor M4, the source electrode of the MOS transistor M7, the source electrode of the MOS transistor M10, the source electrode of the MOS transistor M14 and a power supply voltage VDD are connected;
the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M12 are connected with the D input end
The drain electrode of the MOS transistor M1 and the source electrode of the MOS transistor M2 are connected;
the drain electrode of the MOS transistor M2, the drain electrode of the MOS transistor M3, the drain electrode of the MOS transistor M11 and the gate electrode of the MOS transistor M5 are connected;
the drain electrode of the MOS transistor M4, the drain electrode of the MOS transistor M5, the gate electrode of the MOS transistor M7 and the gate electrode of the MOS transistor M13 are connected;
the source electrode of the MOS transistor M5 and the drain electrode of the MOS transistor M6 are connected;
the drain electrode of the MOS transistor M7, the drain electrode of the MOS transistor M8, the drain electrode of the MOS transistor M10, the gate electrode of the MOS transistor M14 and the gate electrode of the MOS transistor M15 are connected with the output
A terminal;
the drain electrode of the MOS tube M14 and the drain electrode of the MOS tube M15 are connected with the output Q end;
the source electrode of the MOS transistor M8 and the drain electrode of the MOS transistor M9 are connected;
the source electrode of the MOS transistor M9 and the drain electrode of the MOS transistor M13 are connected;
the gate of the MOS transistor M2, the gate of the MOS transistor M4, the gate of the MOS transistor M6 and the gate of the MOS transistor M9 are connected with the C L K input end;
the grid electrode of the MOS tube M3, the grid electrode of the MOS tube M11, the grid electrode of the MOS tube M8 and the grid electrode of the MOS tube M10 are connected with the RST input end;
the source electrode of the MOS transistor M6, the source electrode of the MOS transistor M12, the source electrode of the MOS transistor M13, and the source electrode of the MOS transistor M15 are connected to a ground terminal GND.
In an embodiment of the present invention, the MOS transistor M1, the MOS transistor M2, the MOS transistor M4, the MOS transistor M7, the MOS transistor M10, and the MOS transistor M11 are PMOS transistors;
the MOS transistor M3, the MOS transistor M5, the MOS transistor M6, the MOS transistor M8, the MOS transistor M9, the MOS transistor M12, the MOS transistor M13 and the MOS transistor M15 are NMOS transistors.
In one embodiment of the present invention, the gate signal generating circuit includes a flip-flop B; wherein the content of the first and second substances,
the D input end of the trigger B is used for inputting and connecting a power supply voltage VDD;
the C L K input end of the flip-flop B is used for inputting the START signal;
the RST input end of the flip-flop B is used for inputting the STOP signal;
and the Q output end of the trigger B is used for outputting the gating signal.
In one embodiment of the present invention, the monostable pulse generating circuit includes: delay unit 1, delay unit 2 and inverter I31And NAND gate U31(ii) a Wherein the content of the first and second substances,
the output end of the delay unit 1 is connected with the input end of the delay unit 2 and the register array circuit;
the output end of the delay unit 2 is connected with the phase inverter I31And said nand gate U31An input terminal of;
the phase inverter I31Output end of the NAND gate is connected with the NAND gate U31The other input terminal of (a);
the NAND gate U31Is used for outputting the RST signal.
In one embodiment of the invention, a register array circuit includes: a plurality of flip-flops C; wherein the content of the first and second substances,
the input ends of C L K of the plurality of flip-flops C are connected with the output end of the delay unit 1;
d input ends of the plurality of flip-flops C are connected with the high-order counter circuit and the low-order decoding circuit;
the Q output ends of the flip-flops C are connected with the serial data output circuit.
Compared with the prior art, the invention has the beneficial effects that:
(1) the ring oscillator circuit of the time-to-digital converter with the gating enabling function is an even-order ring oscillator circuit, the output phase difference of each stage of the ring oscillator circuit is stable and uniform, the low-bit data information of the time-to-digital converter can reach the resolution of the sub-gate level, and the accuracy is stable;
(2) the time-to-digital converter provided by the invention resets the state of the ring oscillator before the time measurement period starts each time, so that the measurement error caused by uncertain initial state can be eliminated;
(3) the D trigger in the high-order counter circuit of the time-to-digital converter adopts an improved true single-phase clock logic structure design, has simple structure and higher speed, is driven by only a single-phase clock, has better phase noise characteristic and certain power consumption advantage, and eliminates very large reset current possibly caused by the traditional structure during reset through improvement;
(4) the ring oscillator circuit of the time-to-digital converter has a gating function, is simple in overall structure, does not need to be filled with an external clock, is small in area and low in power consumption, can meet the high integration requirement of an SPAD (single photon avalanche diode) array, can guarantee the requirements of TOF (time of flight) ranging on measurement accuracy and measurement range, and can be applied to a read-out circuit of a large-scale SPAD pixel array.
Drawings
Fig. 1 is a schematic structural diagram of a time-to-digital converter with a gating enable function according to the present invention;
FIG. 2 is a schematic diagram of a ring oscillator circuit of the time-to-digital converter according to the present invention;
FIG. 3 is a schematic diagram of a low-level decoding circuit of the time-to-digital converter according to the present invention;
FIG. 4 is a schematic diagram of a high counter circuit of the time-to-digital converter according to the present invention;
FIG. 5 is a schematic diagram of a flip-flop A of the time-to-digital converter according to the present invention;
FIG. 6 is a waveform diagram of the output state of the ring oscillator circuit of the time-to-digital converter provided by the present invention;
fig. 7 is a timing chart of the operation of the time-to-digital converter provided by the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 to 7, the present invention provides a time-to-digital converter with gating enable function, as shown in fig. 1, including: the circuit comprises a ring oscillator circuit, a low-order decoding circuit, a high-order counter circuit, a gate control signal generating circuit, a monostable pulse generating circuit, a register array circuit and a serial data output circuit; wherein the content of the first and second substances,
the ring oscillator circuit is used for outputting a phase node state according to a gate control signal (EN signal) and resetting according to an RST signal;
the low bit decoding circuit is used for outputting low bit data according to the state of the phase node;
the high-order counter circuit is used for outputting high-order data according to the state of the phase node and is also used for clearing according to the RST signal;
the gate signal generation circuit is used for generating the gate signal (EN signal) according to the SATRT signal and the STOP signal;
the monostable pulse generating circuit is used for generating the RST signal according to the STOP signal;
the register array circuit is used for storing the high-order data and the low-order data according to the STOP signal and is also used for outputting the high-order data and the low-order data according to the START signal;
the serial data output circuit is used for serially outputting the high-order data and the low-order data which are generated in parallel.
Specifically, the time-to-digital converter with the gating enable function provided by the invention is used for measuring the time interval of the input START signal and the STOP signal, and realizes high-precision and wide-range measurement of the time interval.
Specifically, the ring oscillator circuit starts operating when the input EN signal is active, outputs eight phase node states (eight bit binary state codes), and stops operating when the input EN signal is inactive. When the RST signal is input, the ring oscillator circuit is reset (each output node is restored to the initial phase state).
Specifically, the ring oscillator circuit is composed of a plurality of inverters, a plurality of NAND gates, a plurality of transmission gates and the like, is a four-stage differential output structure based on the inverters, and has a reset function and a gating function. The ring oscillator circuit is provided with a transmission gate structure between the phase inverter units, so that the ring oscillator structure has a gate control function, the phase difference between the signals of the in-phase input end and the in-phase output end of each stage is fixed to be 45 degrees, and two cross-coupled two-input NAND gates are arranged between the signals of the two differential output ends of each stage, so that the phase difference of the differential output signals of each stage is locked at 180 degrees and the ring oscillator circuit has a reset function.
Specifically, the input of the lower decoding circuit is the phase node state (OUT0, OUT1, OUT2, OUT3) of the ring oscillator circuit output, and decodes it, outputting lower data information (lower three-bit count state).
Specifically, the high counter circuit is formed by cascading flip-flops with a reset function, the input of the high counter circuit is a phase state (OUT7) of a certain output node of the ring oscillator circuit, and high data information (high 12-bit counting state) of the time-to-digital converter is output. When the RST signal is input, the high counter circuit is reset (reset before each time interval measurement). The high counter circuit is used to record the number of ringing cycles in the interval between the START and STOP signals.
Specifically, the gate signal generation circuit is mainly used to generate a gate signal, and outputs an EN signal to be active when it inputs a START signal and to be inactive when it inputs a STOP signal.
Specifically, the monostable pulse generating circuit: the RST signal (reset pulse signal) is generated, and the RST signal is generated when the STOP signal is input thereto.
Specifically, the register array circuit stores the lower-order data information outputted from the lower-order decoding circuit and the higher-order data information outputted from the higher-order counter circuit when the sampling signal C L K _ SAMP L E is inputted (the STOP signal generates the sampling signal C L K _ SAMP L E via the delay unit 1), and outputs it to the serial data output circuit when the START signal of the next measurement cycle comes
Specifically, the serial data output circuit is used for serially outputting the high-order data and the low-order data output by the register array circuit to the outside for data processing.
Specifically, when a START signal arrives, the TDC provided by the invention STARTs to work by the ring oscillator, and when a STOP signal arrives, the ring oscillator STOPs working; the low-order decoding circuit decodes the output phase node state of the ring oscillator to obtain the low-order data information of the TDC; the high-order counter circuit is formed by cascading D flip-flops, takes the phase state of a ring oscillation output node OUT7 as a counting clock of the counter, so that the resolution is the ring oscillation period, the number of the ring oscillation periods in the interval of the START signal and the STOP signal can be recorded, and the TDC high-order data information is output. The gate control signal generating circuit sets a gate control EN signal to be effective when the START signal arrives, so that the ring oscillator STARTs to work, and sets the EN signal to be ineffective when the STOP signal arrives, so that the ring oscillator STOPs working. The register array circuit stores low-order data and high-order data in a register array formed by D flip-flops after a STOP signal arrives, and outputs the START signal of the next measurement period to the outside through the serial data output circuit for data processing when the START signal arrives. The monostable pulse generating circuit outputs a reset pulse RST signal after the register array samples counting information, restores each output node of the ring oscillation reset to an initial phase state, and clears the high-order counting circuit to measure the next time interval.
Further, as shown in fig. 2, the ring oscillator circuit includes: the device comprises a plurality of inverters I, a plurality of transmission gates TG and a plurality of NAND gates U; wherein the content of the first and second substances,
the phase inverter IjIs passed through the transmission gate TGjThen are respectively connected to the NAND gates UjInput terminal of, said inverter I1jInput terminal of, said inverter Ij+1J is an integer greater than or equal to 1 and less than or equal to 7;
the phase inverter I8Is passed through the transmission gate TG8Then are respectively connected to the NAND gates U8Input terminal of, said inverter I18Input terminal of, said inverter I1An input terminal of (1);
the phase inverter I8Is passed through a transmission gate TG8Is connected to an inverter I1The input of (1);
the NAND gate UkAnother output terminal of the NAND gate U is connected with a power supply voltage VDD, and the NAND gate UmIs connected with the RST signal, k is an integer which is more than or equal to 1 and less than or equal to 4, and m is an integer which is more than or equal to 5 and less than or equal to 8;
the NAND gate UkIs connected to the inverter I1(k+4)An input terminal of (1);
the NAND gate UmIs connected to the inverter I1(m-4)An input terminal of (1);
the transmission gate TGjAnd the transmission gate TG8The control end of the controller inputs the gating signal;
the phase inverter I1jAnd the inverter I18The output of which outputs the phase node state.
Specifically, the ring oscillator circuit (ring oscillator) realizes an oscillation function, and simultaneously avoids the problem that the conventional even-order ring oscillator cannot oscillate due to level locking in a direct current state. Each stage of inverter I ((inverter I) of bar oscillator circuit1-inverter I8) A transmission gate TG is inserted between them to make the oscillator circuit have a gate control function.
Specifically, the transmission gate TG is configured as an analog switch for transmitting signals, and is formed by connecting a PMOS transistor and an NMOS transistor in parallel, and input control signals EN on the gates of the two transistors are complementary, that is, when the gate of the PMOS transistor is at a high level, the gate of the NMOS transistor is at a low level, and when the gate of the PMOS transistor is at a low level, the gate of the NMOS transistor is at a high level, and there is no threshold voltage loss in transmitting voltages. Preferably, when the gate control signal EN is at a high level, the transmission gate TG is turned on, the ring oscillator starts to operate, and the ring oscillator enters an oscillation state; when the gate control signal EN is at a low level, the transmission gate TG is closed, no signal path exists between each level of inverter I, the output voltage is kept unchanged due to the existence of the capacitor in each node inverter I, and the ring oscillator stops working.
Specifically, the specific phase states of the output of the ring oscillator circuit are: inverter I11The output is OUT<4>An inverter I12The output is OUT<1>An inverter I13The output is OUT<6>An inverter I14The output is OUT<3>An inverter I15The output is OUT<0>An inverter I16The output is OUT<5>An inverter I17The output is OUT<2>An inverter I18The output is OUT<7>。
Further, each output terminal inside the ring oscillator is connected with an inverter I (inverter I) with large size and strong driving capability11-inverter I18) Connected to output the phase state of each node as an output driver to the outside. Two cross-coupled two-input nand gates are arranged between two differential output signals of each stage, so that the differential output signals of each stage are locked at a phase difference of 180 degrees. The inputs of the two cross-coupled NAND gates between the outputs of each stage have the function of resetting the ring oscillator besides the function of completing level locking.
Specifically, when one input of the nand gate U is at a high level, the output is the inverse of the other input; when one of the inputs of the NAND gate U is at low level, the output is at high level. Therefore, when the reset RST signal is in a high level, the cross-coupled NAND gate acts as an inverter which is equivalent to cross coupling, so that the phase of each stage of differential output signals is fixed at 180 degrees; when the reset RST signal is at low level, the output of the NAND gate U is at high level, and as can be seen from FIG. 2, when the reset RST signal is active, OUT <7>, OUT <6>, OUT <5>, OUT <4> are reset to high level, OUT <3>, OUT <2>, OUT <1>, OUT <0> are reset to low level, i.e. the set ring oscillation initial state.
Further, as shown in fig. 3, the lower decoding circuit includes: inverter I21An inverter I22XOR gate I23XOR gate I24XOR gate I25And an exclusive or gate I26(ii) a Wherein the content of the first and second substances,
the phase inverter I21Is connected with the phase inverter I22An input terminal of (1); preferably, an inverter I21Inverter and inverter I22As a buffer.
The exclusive-OR gate I24And said I25Is connected with the exclusive-or gate I26An input terminal of (1);
the phase inverter I21Input terminal of, said exclusive or gate I23Input terminal of, said exclusive or gate I24And said exclusive or gate I25The input terminal of (a) inputs the phase node state;
the phase inverter I22Of the exclusive or gate I23And said exclusive or gate I26The output terminal of (b) outputs the low bit data.
In particular, inverter I21Is input as OUT<3>XOR gate I23Is OUT<3>And OUT<1>XOR gate I24Is OUT<2>And OUT<3>XOR gate I25Is OUT<0>And OUT<1>An inverter I22Has an output of S<2>XOR gate I23Has an output of S<1>XOR gate I26Has an output of S<0>。
Specifically, the low-order decoding circuit is composed of logic gates, detects the output signal of each stage of ring oscillator circuit, takes the eight phase node states (eight-bit binary state code) as input codes, and outputs low-order data (low three-bit counting state). The relationship between the preset phase node state and the corresponding low-order data is shown in the following table:
| OUT<7:0> | low bit data S<2:0> |
| 11110000 | 000 |
| 11100001 | 001 |
| 11000011 | 010 |
| 10000111 | 011 |
| 00001111 | 100 |
| 00011110 | 101 |
| 00111100 | 110 |
| 01111000 | 111 |
It can be seen from the table that since the ring oscillator output node state is a differential signal, the lower three-bit decoding S <0:2> can be obtained by detecting the high four-bit or low four-bit node state, and the embodiment adopts the detection of the low four-bit node state. Preferably, the following logical relationship is obtained by simplifying the calculation:
S＜2＞＝OUT＜3＞
wherein the content of the first and second substances,
is an exclusive or operation.
Specifically, as shown in fig. 4, the high counter circuit includes: a plurality of flip-flops A; wherein the content of the first and second substances,
the trigger A1The C L K input of (a) inputs the phase node state;
the trigger AnIs/are as follows
The output end is connected with the trigger AnD input terminal of and said flip-flop a(n+1)N is an integer of 1 to 11 inclusive.
The trigger A12Is/are as follows
The output end is connected with the trigger A12A D input terminal of (1);
RST input ends of the plurality of flip-flops A are used for inputting RST signals;
and the Q output ends of the flip-flops A are used for outputting the high-order data.
Further, as shown in fig. 5, the flip-flop a includes: a plurality of MOS tubes; wherein the content of the first and second substances,
the source electrode of the MOS transistor M1, the source electrode of the MOS transistor M11, the source electrode of the MOS transistor M4, the source electrode of the MOS transistor M7, the source electrode of the MOS transistor M10, the source electrode of the MOS transistor M14 and a power supply voltage VDD are connected;
the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M12 are connected with the D input end
The drain electrode of the MOS transistor M1 and the source electrode of the MOS transistor M2 are connected;
the drain electrode of the MOS transistor M2, the drain electrode of the MOS transistor M3, the drain electrode of the MOS transistor M11 and the gate electrode of the MOS transistor M5 are connected;
the drain electrode of the MOS transistor M4, the drain electrode of the MOS transistor M5, the gate electrode of the MOS transistor M7 and the gate electrode of the MOS transistor M13 are connected;
the source electrode of the MOS transistor M5 and the drain electrode of the MOS transistor M6 are connected;
the drain electrode of the MOS transistor M7, the drain electrode of the MOS transistor M8, the drain electrode of the MOS transistor M10, the gate electrode of the MOS transistor M14 and the gate electrode of the MOS transistor M15 are connected with the output
A terminal;
the drain electrode of the MOS tube M14 and the drain electrode of the MOS tube M15 are connected with the output Q end;
the source electrode of the MOS transistor M8 and the drain electrode of the MOS transistor M9 are connected;
the source electrode of the MOS transistor M9 and the drain electrode of the MOS transistor M13 are connected;
the gate of the MOS transistor M2, the gate of the MOS transistor M4, the gate of the MOS transistor M6 and the gate of the MOS transistor M9 are connected with the C L K input end;
the grid electrode of the MOS tube M3, the grid electrode of the MOS tube M11, the grid electrode of the MOS tube M8 and the grid electrode of the MOS tube M10 are connected with the RST input end;
the source electrode of the MOS transistor M6, the source electrode of the MOS transistor M12, the source electrode of the MOS transistor M13, and the source electrode of the MOS transistor M15 are connected to a ground terminal GND.
Further, the MOS transistor M1, the MOS transistor M2, the MOS transistor M4, the MOS transistor M7, the MOS transistor M10, and the MOS transistor M11 are PMOS transistors;
the MOS transistor M3, the MOS transistor M5, the MOS transistor M6, the MOS transistor M8, the MOS transistor M9, the MOS transistor M12, the MOS transistor M13 and the MOS transistor M15 are NMOS transistors.
Specifically, as shown in fig. 4, the high counter circuit is formed by cascading flip-flops a, preferably D, which output node state OUT in a ring oscillation<7>As a counting clock of the counter, the resolution is the ringing period, the number of ringing periods in the interval between the START signal and the STOP signal can be recorded, and the high-order data of the TDC can be output. The high-order counter circuit is formed by cascading 12D triggers with asynchronous reset function and outputs the TDC high 12-order data S<3:14>. Wherein the D input end of each stage of D flip-flop is connected with
With outputs connected to, and of preceding stage
The output end is connected with the C L K input end (clock input end) of the next stage, and the D flip-flop (flip-flop A) of the first stage1) Clock input ofIs OUT<7>。
Specifically, as shown in fig. 5, the D flip-flop (flip-flop a) of the high counter circuit provided in this embodiment adopts a True Single Phase Clock (TSPC) structure, and is composed of NMOS transistors (MOS transistor M3, MOS transistor M5, MOS transistor M6, MOS transistor M8, MOS transistor M9, MOS transistor M12, MOS transistor M13, and MOS transistor M15) and PMOS transistors (MOS transistor M1, MOS transistor M2, MOS transistor M4, MOS transistor M7, MOS transistor M10, and MOS transistor M11). The middle node X is labeled as the drain of M2, the middle node Y is the drain of M5, and the phase is reversed
The output terminal is the drain of M8, and the in-phase Q output terminal is the drain of M15. Besides, the substrate electrodes of all the PMOS tubes are connected to a power supply end VDD, and the substrate electrodes of all the NMOS tubes are connected to a ground end GND.
Specifically, the TSPC flip-flop (flip-flop A) with the reset function works on the principle that when an input clock (a C L K signal) is at a low level, a MOS tube M2 is conducted, an input signal is transmitted to an intermediate node X in an inverted phase through the action of a D input end MOS tube M1 and a MOS tube M3, and meanwhile, the MOS tube M4 is conducted to pre-charge a Y node to a high level, the MOS tube M is turned off, so that an output end of a Q output node of a same-phase output node and an inverted output node of the Q output node are enabled to be connected with each
When the input clock (C L K signal) changes from low level to high level, MOS tube M2 and M4 are turned off, MOS tube M6 is turned on, if X node is high level, Y node discharges to low level through MOS tube M5 and M6, if X node is low level, MOS tube M5 is turned off, node Y keeps high level in pre-charging, MOS tube M8 is turned on, Y node voltage is transmitted to Q output end of in-phase output node and reverse phase output node
And (4) an output end. The asynchronous reset function is mainly realized by a MOS transistor M3, a MOS transistor M8, a MOS transistor M10 and a MOS transistor M11. When the reset RST signal is at low level, the MOS transistor M10 and the MOS transistor M11 are conducted, and the output node is connected
The output terminal is charged to a high level, the output node Q output terminal is reset to a low level, and the X node is charged to a high level. Because two paths from a power supply end VDD to a ground end GND through an output node Q output end M10 tube or an output node Q output end M11 tube may appear in all D flip-flops in the counter when a reset RST signal arrives, a large current of milliampere magnitude is caused at the moment of resetting, and the chip is easily damaged, therefore, a MOS tube M3 and a MOS tube M8 are added, and because the reset RST signal is effective at low level, when the reset RST signal arrives, the MOS tube M3 and the MOS tube M8 are turned off, so that the two paths from the power supply end VDD to the ground end GND are disconnected, and the large current which may be generated during resetting is further avoided. The MOS transistor M11 is added here, and the X node is charged at the time of reset because the previous stage in the application is at this position
The output end is connected with the input end of a clock C L K of the subsequent stage, and the previous stage is used for resetting
The output end is set to high level, namely the input end of the rear-stage C L K is set to high level, the rear-stage MOS tube M9 is reset and then conducted, when the reset RST signal is changed to high level (invalid), the voltage of the Y node can be transmitted to the Y node in an inverted way
And (4) nodes. Because the voltage of the Y node is unknown, if the voltage of the Y node is high, the Q output end immediately becomes high level after the reset RST signal is invalid, the time sequence of the counter is disordered, and therefore the X node needs to be charged to high level at the same time during resetting, so that the voltage of the Y node is low level, and the normal resetting of each stage of D triggers in the counter and the zero clearing function of the counter can be guaranteed.
Further, as shown in fig. 1, the gate signal generating circuit includes a flip-flop B; wherein the content of the first and second substances,
the D input end of the trigger B is used for inputting and connecting a power supply voltage VDD;
the C L K input end of the flip-flop B is used for inputting the START signal;
the RST input end of the flip-flop B is used for inputting the STOP signal;
and the Q output end of the trigger B is used for outputting the gating signal.
Specifically, the gate signal generating circuit generates a gate signal by setting the gate signal (EN signal) to a high level when the SATRT signal arrives, the ring oscillator STARTs operating, the gate signal (EN signal) is set to a low level when the STOP signal arrives, the ring oscillator STOPs operating, and the register array samples a low-order data output from the low-order decoding circuit and a high-order data output from the high-order counter circuit, the D input terminal of the flip-flop B (D flip-flop) is connected to the power supply voltage VDD, the C L K input terminal is a START signal, the RST input terminal is a STOP signal, and the gate signal (EN signal) is output.
Further, the monostable pulse generating circuit includes: delay unit 1, delay unit 2 and inverter I31And NAND gate U31(ii) a Wherein the content of the first and second substances,
the output end of the delay unit 1 is connected with the input end of the delay unit 2 and the register array circuit;
the output end of the delay unit 2 is connected with the phase inverter I31And said nand gate U31An input terminal of;
the phase inverter I31Output end of the NAND gate is connected with the NAND gate U31The other input terminal of (a);
the NAND gate U31Is used for outputting the RST signal.
Specifically, the monostable pulse generating circuit is used to generate a reset pulse signal (RST signal) after the STOP signal arrives, and the STOP signal is delayed as shown in FIG. 1Generating a sampling signal (C L K _ SAMP L E signal) after the time unit 1, and respectively entering an inverter I after the sampling signal passes through a time delay unit 231And NAND gate U31And then generating a pulse reset RST signal. The state of the ring oscillator and the high counter circuit may be reset by the RST signal. Therefore, the measurement error caused by the uncertain initial state of the ring oscillation can be eliminated so as to carry out the measurement of the next time interval.
Further, as shown in fig. 1, the register array circuit includes: a plurality of flip-flops C; wherein the content of the first and second substances,
the input ends of C L K of the plurality of flip-flops C are connected with the output end of the delay unit 1;
d input ends of the plurality of flip-flops C are connected with the high-order counter circuit and the low-order decoding circuit;
the Q output ends of the flip-flops C are connected with the serial data output circuit.
Preferably, the flip-flops C are D flip-flops, the register array circuit includes 15 flip-flops C, and the C L K input end of these flip-flops C inputs a C L K _ SAMP L E signal (the STOP signal generates a sampling signal after passing through the delay unit 1).
Specifically, as shown in fig. 6, the four-stage differential output ring oscillator STARTs to operate when a START signal arrives, the signal phase difference between the input end and the in-phase output end of each stage is 45 degrees, and the signal phase difference between the output end of each stage is 180 degrees, so that the four-stage differential output of the structure divides the whole ring oscillation period into eight parts, and outputs eight ring oscillation phase node states, so that the TDC resolution is at least one eighth of the ring oscillation period.
The TDC provided by the embodiment of the present invention is further explained by the operation timing, as shown in FIG. 7, when the rising edge of the START signal comes, the trigger gate signal (EN signal) becomes high level, the ring oscillator STARTs to operate, the TDC STARTs to time, when the rising edge of the STOP signal comes, the trigger gate signal (EN signal) becomes low level, the ring oscillator STOPs operating, the STOP signal pulse is the C L K _ SAMP L E signal after passing through the time delay unit, the signal makes the register array sample and store the output value of the low and high counting circuits at this time, and the DATA [0] is used to represent the information stored in the first period, then, the C L K _ SAMP L E signal passes through the time delay unit and is sent to the monostable flip-flop circuit, the RST signal is output, the ring oscillator is reset to the set initial state and the counter is cleared to perform the next time interval measurement, the DATA [0] previously stored in the register array is converted by the serial DATA converting circuit to output the DATA, and the DATA [1] represents the second operation period, and the measurement of the TDC is performed after the next time interval measurement.
The time-to-digital converter with the gating enabling function can be applied to the laser radar technology and used as a time-to-digital conversion circuit inside a large-scale SPAD pixel array to realize high-precision and wide-range measurement of time intervals. The D trigger in the high-order counter circuit adopts an improved true single-phase clock logic structure design, has simple structure and higher speed, is driven by only a single-phase clock, has better phase noise characteristic and certain power consumption advantage, and eliminates very large reset current possibly caused by the traditional structure during reset through improvement; and the whole structure is simple, and an external clock is not required to be injected, so that the area is small, the power consumption is low, the high integration requirement of an SPAD (single photon avalanche diode) array can be met, and the TOF ranging can be ensured for the measurement precision and the measurement range.
The time-to-digital converter with the gating enabling function, provided by the invention, is used as a core part of a high-precision time measurement technology, and is widely applied to the fields of laser ranging, biomedical treatment, topographic mapping, aerospace and the like. In recent years, unmanned technology has been developed rapidly, and the key technology applied to the unmanned technology is lidar. The embodiment of the invention can be applied to the laser radar technology and used as a time-to-digital conversion circuit in a large-scale SPAD pixel array to realize high-precision and wide-range measurement of time intervals.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A time-to-digital converter with gating enable, comprising: the circuit comprises a ring oscillator circuit, a low-order decoding circuit, a high-order counter circuit, a gate control signal generating circuit, a monostable pulse generating circuit, a register array circuit and a serial data output circuit; wherein the content of the first and second substances,
the ring oscillator circuit is used for outputting a phase node state according to a gating signal and resetting according to an RST signal;
the low bit decoding circuit is used for outputting low bit data according to the state of the phase node;
the high-order counter circuit is used for outputting high-order data according to the state of the phase node and is also used for clearing according to the RST signal;
the gating signal generating circuit is used for generating the gating signal according to the SATRT signal and the STOP signal;
the monostable pulse generating circuit is used for generating the RST signal according to the STOP signal;
the register array circuit is used for storing the high-order data and the low-order data according to the STOP signal and is also used for outputting the high-order data and the low-order data according to the START signal;
the serial data output circuit is used for serially outputting the high-order data and the low-order data which are generated in parallel.
2. The time-to-digital converter of claim 1, wherein the ring oscillator circuit comprises: the device comprises a plurality of inverters I, a plurality of transmission gates TG and a plurality of NAND gates U; wherein the content of the first and second substances,
the phase inverter IjIs passed through the transmission gate TGjThen are respectively connected to the NAND gates UjInput terminal of, said inverter I1jInput terminal of, said inverter Ij+1J is an integer greater than or equal to 1 and less than or equal to 7;
the phase inverter I8Is passed through the transmission gate TG8Then are respectively connected to the NAND gates U8Input terminal of, said inverter I18Input terminal of, said inverter I1An input terminal of (1);
the phase inverter I8Is passed through a transmission gate TG8Is connected to an inverter I1The input of (1);
the NAND gate UkAnother output terminal of the NAND gate U is connected with a power supply voltage VDD, and the NAND gate UmIs connected with the RST signal, k is an integer which is more than or equal to 1 and less than or equal to 4, and m is an integer which is more than or equal to 5 and less than or equal to 8;
the NAND gate UkIs connected to the inverter I1(k+4)An input terminal of (1);
the NAND gate UmIs connected to the inverter I1(m-4)An input terminal of (1);
the transmission gate TGjAnd the transmission gate TG8The control end of the controller inputs the gating signal;
the phase inverter I1jAnd the inverter I18The output of which outputs the phase node state.
3. The time-to-digital converter of claim 1, wherein the lower decoding circuit comprises: inverter I21An inverter I22XOR gate I23XOR gate I24XOR gate I25And an exclusive or gate I26(ii) a Wherein the content of the first and second substances,
the phase inverter I21Is connected to the phase inverterI22An input terminal of (1);
the exclusive-OR gate I24And said I25Is connected with the exclusive-or gate I26An input terminal of (1);
the phase inverter I21Input terminal of, said exclusive or gate I23Input terminal of, said exclusive or gate I24And said exclusive or gate I25The input terminal of (a) inputs the phase node state;
the phase inverter I22Of the exclusive or gate I23And said exclusive or gate I26The output terminal of (b) outputs the low bit data.
4. The time-to-digital converter of claim 1, wherein the high counter circuit comprises: a plurality of flip-flops A; wherein the content of the first and second substances,
flip-flop A1The C L K input of (a) inputs the phase node state;
flip-flop AnIs/are as follows
The output end is connected with the trigger AnD input terminal of and flip-flop a(n+1)N is an integer greater than or equal to 1 and less than or equal to 11;
flip-flop A12Is/are as follows
The output end is connected with the trigger A12A D input terminal of (1);
RST input ends of the plurality of flip-flops A are used for inputting RST signals;
and the Q output ends of the flip-flops A are used for outputting the high-order data.
5. The time-to-digital converter according to claim 4, wherein said flip-flop D comprises: a plurality of MOS tubes; wherein the content of the first and second substances,
a source electrode of a MOS tube M1, a source electrode of a MOS tube M11, a source electrode of a MOS tube M4, a source electrode of a MOS tube M7, a source electrode of a MOS tube M10, a source electrode of a MOS tube M14 and a connection power supply voltage VDD;
the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M12 are connected with the D input end
The drain electrode of the MOS transistor M1 is connected with the source electrode of the MOS transistor M2;
the drain electrode of the MOS tube M2, the drain electrode of the MOS tube M3, the drain electrode of the MOS tube M11 and the gate electrode of the MOS tube M5 are connected;
the drain electrode of the MOS transistor M4, the drain electrode of the MOS transistor M5, the gate electrode of the MOS transistor M7 and the gate electrode of the MOS transistor M13 are connected;
the source electrode of the MOS transistor M5 and the drain electrode of the MOS transistor M6 are connected;
the drain electrode of the MOS tube M7, the drain electrode of the MOS tube M8, the drain electrode of the MOS tube M10, the gate electrode of the MOS tube M14 and the gate electrode of the MOS tube M15 are connected with the output
A terminal;
the drain electrode of the MOS tube M14 and the drain electrode of the MOS tube M15 are connected with the output Q end;
the source electrode of the MOS tube M8 and the drain electrode of the MOS tube M9 are connected;
the source electrode of the MOS transistor M9 and the drain electrode of the MOS transistor M13 are connected;
the grid electrode of the MOS tube M2, the grid electrode of the MOS tube M4, the grid electrode of the MOS tube M6 and the grid electrode of the MOS tube M9 are connected with a C L K input end;
the grid electrode of the MOS tube M3, the grid electrode of the MOS tube M11, the grid electrode of the MOS tube M8 and the grid electrode of the MOS tube M10 are connected with the RST input end;
the source electrode of the MOS transistor M6, the source electrode of the MOS transistor M12, the source electrode of the MOS transistor M13, and the source electrode of the MOS transistor M15 are connected to a ground terminal GND.
6. The time-to-digital converter according to claim 5, wherein said MOS transistor M1, said MOS transistor M2, said MOS transistor M4, said MOS transistor M7, said MOS transistor M10, and said MOS transistor M11 are PMOS transistors;
the MOS transistor M3, the MOS transistor M5, the MOS transistor M6, the MOS transistor M8, the MOS transistor M9, the MOS transistor M12, the MOS transistor M13 and the MOS transistor M15 are NMOS transistors.
7. The time-to-digital converter of claim 1, wherein the gating signal generating circuit comprises a flip-flop B; wherein the content of the first and second substances,
the D input end of the trigger B is used for inputting and connecting a power supply voltage VDD;
the C L K input end of the flip-flop B is used for inputting the START signal;
the RST input end of the flip-flop B is used for inputting the STOP signal;
and the Q output end of the trigger B is used for outputting the gating signal.
8. The time-to-digital converter of claim 1, wherein the monostable pulse generating circuit comprises: delay unit 1, delay unit 2 and inverter I31And NAND gate U31(ii) a Wherein the content of the first and second substances,
the output end of the delay unit 1 is connected with the input end of the delay unit 2 and the register array circuit;
the output end of the delay unit 2 is connected with the phase inverter I31And said nand gate U31An input terminal of;
the phase inverter I31Output end of the NAND gate is connected with the NAND gate U31The other input terminal of (a);
the NAND gate U31Is used for outputting the RST signal.
9. The time-to-digital converter of claim 8, wherein the register array circuit comprises: a plurality of flip-flops C; wherein the content of the first and second substances,
the input ends of C L K of the plurality of flip-flops C are connected with the output end of the delay unit 1;
d input ends of the plurality of flip-flops C are connected with the high-order counter circuit and the low-order decoding circuit;
the Q output ends of the flip-flops C are connected with the serial data output circuit.
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| CN110376872B (en) * | 2019-05-29 | 2020-10-23 | 西安电子科技大学 | Time-to-digital converter based on asynchronous reset and applied to TADC |
| CN110677142A (en) * | 2019-09-09 | 2020-01-10 | 中国人民解放军国防科技大学 | Burr-free asynchronous reset TSPC type D trigger with scanning structure |
| CN110635787A (en) * | 2019-09-09 | 2019-12-31 | 中国人民解放军国防科技大学 | Burr-free asynchronous set TSPC type D trigger with scanning structure |
| CN111208416B (en) * | 2020-01-15 | 2021-08-20 | 西安电子科技大学 | Integrated circuit process credibility detection method and circuit based on time-to-digital converter |
| CN114460830A (en) * | 2021-09-27 | 2022-05-10 | 桂林电子科技大学 | Novel time-to-digital conversion integrated circuit |
| CN114935886B (en) * | 2022-04-21 | 2023-04-28 | 中国科学院上海微系统与信息技术研究所 | Two-stage superconducting time-to-digital converter and superconducting detector imaging system |
| CN116582111B (en) * | 2023-05-23 | 2024-02-23 | 合芯科技有限公司 | Oscillating loop circuit and device and method for measuring reading time of time sequence circuit |
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| JP5262865B2 (en) * | 2009-03-11 | 2013-08-14 | 株式会社リコー | Double integral type analog-digital converter, digital temperature sensor and digital multimeter using the same |
| JP2012244199A (en) * | 2011-05-14 | 2012-12-10 | Handotai Rikougaku Kenkyu Center:Kk | Operational-amplifier-less/capacitor-less ad converter and td converter |
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