CN109804714B

CN109804714B - Automatic reconfiguration type light-emitting circuit

Info

Publication number: CN109804714B
Application number: CN201780051817.3A
Authority: CN
Inventors: P·D·拉克
Original assignee: LITEIDEAS LLC
Current assignee: LITEIDEAS LLC
Priority date: 2016-06-29
Filing date: 2017-06-29
Publication date: 2021-10-26
Anticipated expiration: 2037-06-29
Also published as: EP3479656A4; EP3479656A1; CN109804714A

Abstract

An automatically re-configurable lighting circuit comprising: first and second lamp blocks; a switching mechanism having (i) a first state in which the switching mechanism electrically connects the first light block in parallel with the second light block and (ii) a second state in which the switching mechanism electrically connects the first light block in series with the second light block; a current regulator that generates a current control signal in response to currents in the first and second lamp groups; and a controller electrically connected to the switching mechanism, the controller configured to switch the switching mechanism between the first state and the second state based on the current control signal.

Description

Automatic reconfiguration type light-emitting circuit

Technical Field

The devices and methods disclosed herein relate to electrical lighting devices, and in particular to automatically reconfiguring light emitting circuits.

Background

Semiconductor-based lighting devices, such as lighting devices using Light Emitting Diodes (LEDs), have recently become popular due to their durability and efficiency. Even compared to fluorescent lighting, LED-based lighting can last for longer periods of thousands of hours, while consuming much less watts of power per lumen. However, the LED lighting devices themselves present several challenges. The LED has a minimum forward voltage that must be applied before the LED begins to emit light. When driven by sinusoidal voltage waveforms, such as those typically available from ac line voltages, the network of LEDs may have a gap in the light emission at the point in time when the voltage waveforms drop below the net's total forward voltage. This can create a significant vibration-like effect that is somewhat irritating and reduce the overall light output of the LED-based lighting device.

Accordingly, there is a need for lighting circuits and drivers that can efficiently utilize a larger portion of a power signal having varying voltages.

Disclosure of Invention

In one aspect, an auto-reconfiguration lighting circuit includes: a first electric lamp block; a second electric lamp block; a switch mechanism including a first state in which the switch mechanism electrically connects the first light block in parallel with the second light block and a second state in which the switch mechanism electrically connects the first light block in series with the second light block; a current regulator that generates a current control signal in response to currents in the first and second lamp groups; and a controller electrically connected to the switching mechanism, the controller configured to switch the switching mechanism between the first state and the second state based on the current control signal.

In a related embodiment, the current regulator includes at least one power transistor through which the current in the first and second lamp groups flows, the at least one power transistor has a control terminal, and the current control signal is a signal at the control terminal of the at least one power transistor.

According to other aspects of the invention, the current regulator may further include at least one regulator transistor having an output terminal; and the current control signal is a signal generated at the output terminal of the at least one regulator transistor. The at least one current regulator further includes at least one operational amplifier incorporated in the at least one regulator transistor. The circuit may further include a negative feedback network that supplies negative feedback to the current regulator based on the current. The current regulator may be a current sink. The circuit may further include a control signal sealer.

A method for automatically reconfiguring a lighting circuit is also disclosed. The method comprises the following steps: receiving, by a controller connected to a switching mechanism, a current control signal generated by a current regulator in response to currents in a first lamp group and a second lamp group, the switching mechanism having a first state connecting a first lamp block in parallel with a second lamp block and a second state connecting the first lamp block in series with the second lamp block; and switching, by the controller, the switching mechanism between the first state and the second state based on the current control signal.

Drawings

The following detailed description of the disclosed devices and methods will be better understood when read in conjunction with the appended drawings. It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown.

FIG. 1A is a block diagram depicting an embodiment of a driver as described herein;

FIG. 1B is a schematic diagram depicting an embodiment of a driver circuit as described herein;

FIG. 1C is a schematic diagram depicting an embodiment of a driver circuit as described herein;

FIG. 1D is a schematic diagram depicting an embodiment of a network employing elements described herein;

FIG. 1E is a block diagram depicting an embodiment of a network employing elements described herein;

FIG. 1F is a schematic diagram depicting an embodiment of an adapter as described herein;

FIG. 2A is a block diagram depicting an embodiment of a modified AC decoder as described herein;

FIG. 2B is a schematic diagram depicting an embodiment of a modified AC decoder as described herein;

FIG. 2C is an oscilloscope display depicting an embodiment of a pulse width modulated signal as described herein;

FIG. 2D is an oscilloscope display depicting an embodiment of a pulse width modulated signal as described herein;

FIG. 2E is an oscilloscope display depicting an embodiment of a pulse width modulated signal matched with a corresponding rectified modified AC waveform as described herein;

FIG. 2F is an oscilloscope display depicting an embodiment of a pulse width modulated signal matched with a corresponding rectified modified AC waveform as described herein;

FIG. 3A is a block diagram depicting an embodiment of a modified AC encoder as described herein;

FIG. 3B is a schematic diagram depicting an embodiment of a modified AC encoder as described herein;

FIG. 3C is an oscilloscope display depicting an embodiment of a gate drive waveform as described herein;

FIG. 3D is an oscilloscope display depicting an embodiment of gate drive waveforms as described herein;

FIG. 3E is a diagram depicting an embodiment of a transformer output based on a gate drive signal;

FIG. 3F is an oscilloscope display depicting an embodiment of an unmodified rectified AC waveform as described herein;

FIG. 3G is an oscilloscope display depicting an embodiment of a modified rectified AC waveform as described herein;

FIG. 3H is an oscilloscope display depicting an embodiment of a modified rectified AC waveform as described herein;

FIG. 3I is a schematic diagram depicting an embodiment of a modified AC encoder as described herein;

FIG. 3J is a schematic diagram depicting an embodiment of a modified AC encoder as described herein;

FIG. 4 is a flow chart illustrating a method for encoding signals in a modified AC line;

FIG. 5 is a flow chart illustrating a method for decoding a modified AC signal;

FIG. 6 is a block diagram illustrating an embodiment of an auto-reconfiguration light emitting circuit;

FIG. 7A is a schematic diagram illustrating portions of an embodiment of an automatic reconfiguration light emitting circuit;

FIG. 7B is a schematic diagram illustrating portions of an embodiment of an automatic reconfiguration light emitting circuit;

FIG. 7C is a schematic diagram illustrating portions of an embodiment of an automatic reconfiguration light emitting circuit;

FIG. 8 is a flow chart illustrating a method for automatically reconfiguring a lighting circuit;

FIG. 9 is a block diagram illustrating an embodiment of an auto-reconfiguration light-emitting circuit;

fig. 10A is a schematic diagram illustrating an embodiment of a current regulator;

FIG. 10B is a schematic diagram illustrating portions of an embodiment of an automatic reconfiguration light emitting circuit;

FIG. 11A is a flow chart illustrating a method for automatically reconfiguring a lighting circuit;

FIG. 11B is a schematic diagram illustrating an embodiment of voltage control signal waveforms and current control signal waveforms; and

FIG. 11C is a schematic diagram illustrating an embodiment of voltage waveforms and stepped current waveforms.

Detailed Description

Embodiments of the disclosed smart dimming system provide a convenient and efficient way to dim high-efficiency lighting devices driven by AC power. In some embodiments, elements of the disclosed system may be incorporated in a preexisting electrical network within a home or business to control new accessories using a newly installed system while permitting legacy accessories to be operated through previous means. Some embodiments of the system allow for dimming of smart accessories and full operation of other accessories or appliances on the same circuit. Embodiments of the dimmable power supply draw very little power to control, thereby increasing the efficiency of the system.

Fig. 1A presents a block diagram of an embodiment of a driver 100 for an efficient lighting device. The drive 100 has a power input 101 that receives AC power. The driver utilizes the first terminal 102 and the second terminal 104 to supply power to the load 110. The first output terminal 102 may be connected to the power input 101 through a rectifier 103 and provide a rectified voltage from the power input 101. The second output terminal 104 provides a return path from the load 110 through at least one current regulator 105 that regulates current in response to commands received via the control input 106. In some embodiments, the drive 100 also includes a dc power supply 107 that receives power from the rectifier 103; in some embodiments, the dc power supply 107 provides operating power for the drive 100. The driver 100 may be connected to a load 110 via a first output terminal 102 and a second output terminal 104.

The load 110 may comprise at least one lamp. The at least one electric lamp may comprise at least one electroluminescent lamp, such as an LED. The at least one electric lamp may comprise a plurality of electroluminescent lamps; for example, at least one electric lamp may include a mesh of LEDs connected in series and parallel by conductors. In some embodiments, the load is incorporated in an auto-reconfiguration light emitting circuit as set forth in more detail below with reference to fig. 6-7B.

Rectifier 103 may be a full wave rectifier. The rectifier 103 may be a bridge rectifier. In some embodiments, the rectifier 103 is a high power rectifier; as an example, the rectifier 103 may have a maximum average rectified forward current of at least 1 amp. The rectifier 103 may have a maximum average rectified forward current of at least 1.5A. The rectifier 103 may have a maximum non-repetitive peak forward surge current of at least 50A. The rectifier 103 may have a maximum repetitive reverse voltage level of at least 1000V. The rectifier 103 may have a maximum root mean square ("RMS") bridge input voltage of at least 700V. The rectifier 103 may have a maximum DC reverse voltage of at least 1000V. As a non-limiting example, as shown in fig. 1B, the rectifier 103 may be an MB10S bridge rectifier manufactured by Fairchild (Fairchild) semiconductor corporation of san jose, california, or a rectifier with similar properties. In some embodiments, the driver 100 includes a filter (not shown) to generate a substantially constant DC voltage output; the filter may limit fluctuations in the DC voltage to a particular range that is substantially less than fluctuations present in the unfiltered output from the rectifier 103.

Control input 106 receives a control signal. In some embodiments, the control signal is a pulse width modulated signal. In other embodiments, the control signal is a voltage control signal; the voltage control signal may have a range of possible values between a minimum value and a maximum value. As a non-limiting example, the voltage control signal may be a DC signal of 0 to 10V. The minimum voltage of the voltage control signal may be a ground voltage. The minimum voltage of the voltage control signal may be a virtual ground or a reference voltage, such as a return voltage of the driver 100. The minimum voltage may be positive, negative, or zero. Likewise, the maximum voltage may be positive, negative, or zero. Without limitation, the voltage control signal may range from 0 to 10, from 0 to-10, or may be any other voltage range.

In some embodiments, the at least one current regulator 105 modifies the current flowing from the second output terminal 104 through the at least one current regulator 105 in response to the control signal. As illustrated in fig. 1B, the at least one current regulator 105 may include a transistor 117 that modifies current as determined by a voltage derived from the control signal. For example, the at least one current regulator 105 may apply a voltage based on a control signal at a base of the transistor 117 if the transistor 117 is a bipolar junction transistor. The at least one current regulator 105 may apply a voltage based on a control signal at a gate of the transistor 117 if the transistor 117 is a field effect transistor. In some embodiments, transistor 117 is a metal oxide semiconductor field effect transistor ("MOSFET"). The transistor 117 may be a transistor capable of operating at high current; for example, transistor 117 may be a MOSFET capable of withstanding a maximum continuous drain current of 6A or greater at an operating temperature of 25 degrees celsius. Transistor 117 may be a MOSFET capable of withstanding a maximum continuous drain current of 3.8A or greater at an operating temperature of 100 degrees celsius. Transistor 117 may be a MOSFET capable of withstanding the maximum pulsed drain current of 24A. Transistor 117 may be a MOSFET capable of withstanding a maximum current of 2A during repeated bursts of avalanche or a single burst of avalanche. Transistor 117 may be a MOSFET capable of sustaining a pulse having a single pulse avalanche energy of 88 millijoules. As a non-limiting example, transistor 117 may be an STD7N80K5 MOSFET manufactured by ST microelectronics of Geneva, Switzerland.

The at least one current regulator 105 may include an operational amplifier 111. In some embodiments, amplifier 111 has an output that supplies a voltage based on a control signal to the control terminal of transistor 117; the control terminal is the terminal of transistor 117 that is used to regulate current through the transistor, such as the base of a bipolar junction transistor or the gate of a MOSFET. As an example, in the case where the transistor 117 is a field effect transistor, the amplifier output may be connected to the gate of the transistor 117. In the case where transistor 117 is a bipolar junction transistor, the output may be connected to the base of transistor 117. In some embodiments, where the control signal is a voltage control signal, the control signal is applied to the non-inverting input of amplifier 111, thereby producing a gain proportional to the control signal. At least one current regulator may provide a voltage based on the current returning from the load to the second output terminal 102, causing the amplifier 111 to generate the necessary output voltage to cause the transistor 117 to permit current matching to the control voltage at the non-inverting input. For example, the input to the inverting terminal may be part of a loop including one or more resistors 112, such that the amplifier 111 generates an output that causes the transistor 117 to generate a current that causes the voltage drop across at least one resistor 112 to match the voltage at the non-inverting input. The at least one resistor 112 may be a plurality of parallel resistors. Continuing the example, in some embodiments, with the power supplied by driver 100 rectified, the operational amplifier forms whatever positive output it requires on the gate of transistor 117 for the current flowing through the at least one resistor 112 to produce the same voltage as the voltage signal at the non-inverting input of amplifier 111; assuming that a sufficiently high DC current can be drawn from the load, the voltage drop across the at least one resistor 112 can match the voltage at the non-inverting input of the amplifier 111.

Continuing the example further, in embodiments in which the power supplied by the driver 100 is in the form of an unfiltered rectified voltage, the voltage at the first output terminal 102 varies between 0 and the amplitude of the rectified voltage wave. The voltage at transistor 117 may be the voltage at first output terminal 102 minus the voltage drop across the load; for example, in the case of a net where the load is an LED, the voltage drop is determined by the forward voltage of the LED. Continuing the example further, in some embodiments, the voltage into transistor 117 thus varies from 0 to a value equal to the output voltage minus the voltage drop across the load, and transistor 117 modulated by the amplifier acts as a variable resistor, limiting the current to a value that produces the necessary voltage drop across at least one resistor 112. In the case where the voltage drops close to 0, the transistor 117 can be turned on all the time; nonetheless, the current through transistor 117 may drop to 0 due to the lack of potential. Thus, the voltage across resistor 112 may resemble a square wave over time with a voltage that is more or less constant interrupted to zero from time to time by periodic drops. Due to the rapidity of oscillation and the relative instantaneity of the moment with zero voltage, the resulting current through transistor 117, and thus the power to the load, may appear constant to the user. In some embodiments, in the absence of a control signal, transistor 117 is turned on at full power; in some embodiments, this is because the resistor 133 at the control signal input 106 is connected to the power supply 107, thereby forming a DC signal in the absence of a control signal.

In some embodiments, the at least one current regulator 105 includes a capacitor 1007 in parallel with a resistor that supplies voltage to the control terminal of the at least one transistor 117. The capacitor 1007 can be used to reduce abrupt changes in the current provided by the at least one transistor 117. For example, when the AC waveform voltage increases sufficiently to start the load 110 turning on, the transistor 117 may be fully turned on, and the current initially allowed by the transistor 117 may be relatively high, and the operational amplifier 111 may not be able to modify its gain in response to the negative feedback network quickly enough to avoid spikes in the current through the transistor 117; capacitor 1007 can be used to reduce the voltage provided to the control terminal of at least one transistor 117, thereby reducing the resulting current spike. The capacitor and resistor may be selected to reduce current spikes to produce a light output that meets a given criteria with respect to flicker or other changes in light output visible to the user.

In some embodiments, as shown in fig. 1A, the driver 100 includes a zero current shutdown device 109 that causes the current flowing through the at least one current regulator 105 to drop to zero. In some embodiments, where the control signal is a voltage control signal, the zero current shutdown device 109 cuts off current through the at least one current regulator 105 when the control signal falls within a few tens of millivolts to zero. In some embodiments, the zero current shutdown device 109 includes a comparator 109a that looks at the voltage of the control signal input, compares it to a reference voltage, and causes the at least one current regulator 105 to shut down all power to the load 110 upon the control signal voltage falling below the reference voltage; the reference voltage may be within a few millivolts to zero. As illustrated in fig. 1B, as long as the control signal is higher than the reference voltage, the comparator 109a may output sufficient voltage to reverse bias the switching diode 109B, preventing conduction through the switching diode 109B; when the control signal falls below the reference voltage, the comparator output may switch to the return voltage, forward biasing the switching diode 109b and causing the voltage supplied to the gate or base of the transistor 117 to drop to near zero, turning off the current to the load 110.

In some embodiments, as shown in fig. 1C, the at least one current regulator 105 includes a plurality of current regulators 105. For example, the circuitry of driver 100 may branch to include a first current regulator and a second current regulator. The impedance of the first current regulator may be substantially equal to the impedance of the second current regulator such that the control signal is equally distributed to each regulator. In some embodiments, the first current regulator has a first transistor 117a that regulates current based on a divided control signal at its base or gate as directed by the input voltage. The first transistor 117a may be any transistor suitable for use as the transistor 117 described above with reference to fig. 1B. The first current regulator may have a first operational amplifier 111a supplying a voltage based on a divided control signal to the base or gate of the first transistor 117 a; the first operational amplifier 111a may operate in the same manner as the operational amplifier 111 described above in connection with fig. 1B. The first operational amplifier 111a may use negative feedback supplied to its inverting terminal such that the operational amplifier compares the voltage drop across the at least one resistor 112a due to the current supplied by the transistor 117a through the at least one resistor 112a, as described above with reference to fig. 1B; the resistance of the at least one resistor 112a may be less than the resistance of the at least one resistor 112 to match the divided control signal. As an example, where the at least one resistor 112 in the current regulator 105 receiving the undivided control signal is 10 Ω, the at least one resistor 112a in the current regulator receiving the divided control signal may be 3.9 Ω.

The second current regulator may have a second transistor 117 b; the second transistor 117b may be as described above with reference to the first transistor 117 a. The second current regulator may have a second operational amplifier 111b, which may function in the same manner as the first operational amplifier 111 a; the second operational amplifier 111b may use negative feedback to match the voltage across the second at least one resistor 112b based on the current from the second transistor 117b to the divided control signal, as described above with reference to the first current regulator.

In some embodiments, the zero current shutdown device 109 also branches to both the first and second current regulators; for example, when the control signal is greater than the reference voltage, the comparator 109a may have sufficient voltage to reverse bias a first switching diode 109B connected to the path from the first operational amplifier 111a to the first transistor 117a, and reverse bias a second switching diode 109c connected to the path from the second operational amplifier 111B to the second transistor 117B, as described above in connection with fig. 1B. When the control signal falls below the reference voltage, the comparator 109a may supply a return voltage to both of the switching diodes 109 b-c, forward biasing both of the switching diodes 109 b-c and causing the voltage at the base or gate of each of the first and second transistors 117a, 117b to fall to near zero in order to turn off the current through the first and second transistors 117a, 117 b. In other embodiments, as shown in fig. 7C, the two switching diodes 109 b-C are replaced by a dual switching diode 109d connecting both the zero current turn-off device and the operational amplifiers 111 a-111 b.

In some embodiments, using multiple current regulators 105 for load balancing permits driver 100 to supply a greater amount of power to load 110 by sharing current substantially equally among multiple current regulators 105. The driver 100 may provide a plurality of first output terminals 102 and a plurality of second output terminals 104, allowing the driver 100 to drive several loads (not shown) simultaneously; for example, the driver 100 may have four first output terminals 102 and four second output terminals 104. The load 110 or loads may be configured to take advantage of load balancing properties provided by multiple current regulators; for example, where the load 110 is a LED net, the load 110 may be comprised of two or more separate circuits, each connected to a different first output terminal 102 and second output terminal 104; thus, failure of one circuit in the LED net may not damage a second circuit in the LED net, permitting the net to continue to emit light.

In some embodiments, the load 110 or loads and the driver 100 are configured such that the load or loads are typically run at a fraction (e.g., 60%) of the maximum rated power of the load or components of the loads. Thus, a power surge through driver 100 to load 110 or loads may be absorbed by the load or loads themselves using excess power consumption available in load 110 or loads. In some embodiments, failure of the load or a component of the number of loads causes more power to be delivered to the load or the remaining components of the number of loads. For example, in the event that an LED in the grid fails, ending conduction through that LED, the power through each LED or set of LEDs in parallel with the failed LED is thus increased; unlike in conventional LED networks that operate at or near maximum rated power for each LED, other LEDs in the network can absorb additional current, increasing their power consumption to a higher, yet manageable, rate without failing. Thus, when a single component fails, the load or loads may not suffer from a cascaded component failure, resulting in negligible performance loss and greater useful life of the load or loads due to the isolated failure. In some embodiments, the load or loads combine the use of multiple circuits driven by

multiple output terminals

102, 104 with driving at a power below the maximum rated power to provide multiple classes of robustness; failure of any single circuit due to single component failure is reduced by using fractional power consumption, and failure of the load or an entire circuit of the loads does not prevent the remaining circuits or a circuit from operating properly.

In some embodiments, where the control signal is a voltage control signal, as shown in fig. 1A, the driver 100 includes a resistive voltage divider switch 108. A resistive voltage divider switch 108 places a voltage divider between the control signal input 106 and the at least one current regulator 105. In some embodiments, resistive divider switch 108 has the effect of reducing the voltage of the voltage control signal provided to the at least one current regulator 105 based on the resistance of resistive divider switch 108; the resistive divider switch 108 may have a selectable resistance permitting the power output level of the at least one current regulator 105 to use the resistive divider switch 108 using the resistance of the resistive divider switch 108. In some embodiments, resistive voltage divider switch 108 draws negligible current. As a non-limiting example, the resistive divider switch 108 may permit selection of a value that causes the at least one current regulator 105 to generate 100% power by including a first resistor 108a in the resistive divider switch 108 circuit; for example, where the series resistor 113 has a resistance of 909K Ω and the first resistor 108a has a resistance of 100K Ω, the voltage provided to the at least one current regulator 105 may be approximately 100% of the voltage control signal voltage, and the at least one current regulator 105 may be calibrated to provide full power when the control signal provided to the at least one current regulator 105 is 1V. Likewise, resistive voltage divider switch 108 may permit 75% power to be selected by including a second resistor 108b in the resistive voltage divider switch 108 circuit, 50% power to be selected by including a third resistor 108c in the resistive voltage divider switch 108 circuit, or 25% power to be selected by including a fourth resistor 108 d. Driver 100 may include a manual switch (not shown) that permits a user to select the resistance of resistive voltage divider switch 108. For example, a user may be able to turn a knob (e.g., a 4-bit rotary switch) between positions indicating 100% power, 75% power, 50% power, and 25% power. The resistors in the resistive voltage divider switch 108 may be selected to produce any percentage of the desired output. In some embodiments, the resistor is replaced by a potentiometer or similar device having an adjustable resistance to allow for continuous adjustment of the power level. In still other embodiments, the resistive voltage divider switch is replaced by a single resistor constituting a fixed resistive voltage divider, leaving the current regulation entirely to the control signal.

In some embodiments, as shown in fig. 1A-1C, the driver 100 includes a power supply 107 that provides DC power to the driver 100. The power supply 107 may provide DC power to other components connected to the driver 100, such as the adapter 200 or the signal receiver 300 as described in more detail below in connection with fig. 3A-3H. The power supply 107 may draw a rectified voltage from the rectifier 103. In some embodiments, as shown in fig. 1B, the power supply 107 includes a transient voltage suppressor 114; the transient voltage suppressor 114 may clamp the voltage provided by the power supply 107 at a desired constant value. For example, the transient voltage suppressor 114 may limit the voltage thereacross at about 11 volts DC. In some embodiments, the transient voltage suppressor 114 is SMF9.0A manufactured by Littlefuse corporation of chicago, illinois, or a transient voltage suppressor of similar nature. In other embodiments, the transient voltage suppressor 114 is a Zener (Zener) diode. The transient voltage suppressor 114 may be any circuit element or collection of circuit elements for regulating voltage. The transient voltage suppressor 114 may also protect the circuitry using the power supply 107 from power surges. In some embodiments, the power supply 107 includes a capacitor 115 to filter the voltage signal and set a constant value; the constant voltage may be 10V DC. In some embodiments, the power supply 107 includes a diode 114a to further reduce the voltage to a desired stable value. The power supply 107 may include a resistor 116 a; the resistor 116a may be used to limit the current through the power supply 107 so that the power supply 107 may provide a substantially constant current across a varying voltage input. In other embodiments, the power supply 107 includes a depletion mode MOSFET 116b or similar transistor connected via a line to provide an Idss of 1mA to 2 mA; the depletion mode MOSFET 116b may enable the power supply 107 to provide a constant current regardless of the input voltage to supply all the current required to use the components of the power supply 107. Although the resistor 116a and the depletion mode MOSFET 116B are shown in parallel in fig. 1B-1C, in some embodiments, the power supply 107 includes the MOSFET 116B without the resistor 116a or with a path of the resistor 116 a. Likewise, in some embodiments, the power supply 107 includes a resistor 116a but does not include a MOSFET 116b or a path containing a MOSFET 116 b.

In some embodiments, the power supply 107 includes a power conditioner 720 as illustrated in fig. 7C. The power conditioner 720 may reduce the voltage output by the power supply 107 to a lower constant voltage; for example, power conditioner 720 may reduce a voltage of about 10 volts to a voltage of about 5 volts at its output. In some embodiments, the power supply 107 has a first output at a first voltage level and a second output at a second voltage level; for example, the second output may be the output of power conditioner 720. The two outputs may correspond to DC voltage levels required by two or more different components, such as an operational amplifier requiring 10 volts DC and a microcontroller requiring 5 volts DC as a power supply.

In some embodiments, the driver 100 has unfiltered DC output terminals 118 that enable the driver 100 to provide the voltage from the rectifier 103 to additional devices, such as the modified AC decoder 200 described below in connection with fig. 2A-2F. In some embodiments, the driver 100 includes one or more of its various input or output terminals into a header that can be inserted into another device. As a non-limiting example, the control signal input, return conductor, and power output from the power supply 107 may be supplied to one three-pin tap 119, and unfiltered DC and return from the rectifier 103 may be supplied to two pins of a second three-pin tap 120; without limitation, the first three pin connectors 119 may be 91614-303G connectors manufactured by FCI american technology ltd, of casson, nevada, and the second three pin connectors may be 91614-303G connectors; the joint may be a similar product.

In some embodiments, driver 100 control signal input 106 is connected to an input to voltage follower 121. The voltage follower 121 may ensure that the driver 100 does not reduce the voltage of the control signal to any non-negligible extent by presenting a very high input impedance for the control signal while drawing the necessary current to maintain a signal to the at least one control circuit 105 that matches the voltage of the control signal. The input to the voltage follower may include a parallel transient voltage suppressor 122. In some embodiments, transient voltage suppressor 122 has a minimum clamp voltage of 19.1V, a maximum clamp voltage of 25V, and a peak power dissipation of 300W; the transient voltage suppressor may be T12S5, manufactured by diode corporation of dallas, texas, or a similar device. The control signal input may be a port separate from the connector; in other embodiments, the connector only supplies control signal inputs.

In some embodiments, the driver 100 also includes a control signal output port 123 that relays control signals from the control signal input 106; in some embodiments, the output terminal 123 receives the control signal by being connected between the input port 106 and the voltage follower 121. Driver 100 may include a second voltage follower 124, the output of which goes to output port 123; the second voltage follower 124 may ensure that the necessary current is supplied, for example, from the power supply 107 to maintain the voltage level of the control signal, while presenting a high input impedance for the driver circuit 100 such that the control signal to the voltage follower 121 is not reduced. The output port 123 may have a parallel transient voltage suppressor 125; the transient voltage suppressor 125 may be as described above for the transient voltage suppressor 122. In other embodiments, there is no control signal output port 123.

The control signal output port 123 may permit a second device capable of receiving control signals to receive control signals from the driver 100 a. The second device may be a second driver 100 b; the second driver 100b may be constructed as disclosed above for the driver 100 in connection with fig. 1A-1D. In some embodiments, the control signal output port 123 is directly wired to the control input 106b of the second driver 100 b. In other embodiments, the control signal output port 123 of the first driver 100a is connected to the control signal input 106b of the second driver 100b through an adapter 126. As illustrated in FIG. 1F, the adapter 126 may have an input port 127 that receives a control signal and an output port 128 that outputs the control signal. In some embodiments, adapter 126 has a voltage follower 129 that receives a control signal from input port 127 and outputs the control signal to output port 128; in some embodiments, the voltage follower 129 ensures that the adapter 126 has a very high input impedance, thereby ensuring that the received control signal is not altered by the adapter 126, while supplying the current necessary to maintain substantially the same control signal to the output port 128 (as required by the device receiving the signal from the output port 128). With the adapter 126 connected to the second drive 100b, the adapter 126 may draw power from the power supply 107 of the second drive 100b via the power supply input. In some embodiments, adapter 126 has a transient voltage suppressor 130a across its input port 127. The adapter 126 may have a transient voltage suppressor 130b across its output port 128. Each of the transient voltage suppressors 130 a-130B may be as described above for the transient voltage suppressor 122 with reference to fig. 1B-1D. In some embodiments, some of the inputs and outputs of the adapter 126 are provided as splices; the joints may be adapted to connect to corresponding joints of the drive 100 b. For example, the adapter 126 may have a first three pin connector 131 with a return on a first pin, a control signal output on a second pin, and a power supply input on a third pin. The adapter 126 may have a second three pin connector 132 with a return on the first pin and an unfiltered DC input on the second pin; the unfiltered DC input may not be connected to anything in the adapter 126. The

joints

131, 132 may be adapted to connect to the

joints

119, 120 of the driver 100 b; for example, where the

connectors

119, 120 of the drive 100b are 91614-303 female connectors (as described above in connection with FIGS. 1A-1D), the

connectors

131, 132 of the adapter 126 may be 95293-03G connectors manufactured by FCI American technology, Inc. of Carson, Nevada. In some embodiments, the control signal is very low power and can be conveyed using small gauge wire. The connection between one driver and another driver may include isolation circuitry (not shown) that isolates the control signals from the power circuitry at each driver.

Driver 100a may receive control signals from any device capable of outputting control signals. The driver 100a may receive a control signal from the second driver. The driver 100a may receive the control signal by means of the adapter 126. In some embodiments, driver 100a receives control signals from a wireless receiver (not shown) that transforms wireless signals into control outputs; the wireless receiver may be a digital receiver. In some embodiments, a user may wirelessly transmit a power level command to a wireless receiver using a wireless transmitter (not shown); for example, a wireless receiver may be configured to receive such a signal from a mobile device (e.g., a smartphone) configured to send near field communication signals and transform the received signal into a control signal. A mobile application running on a mobile device may permit a user to interact with a user interface. The user interface may enable a user to select a power level of the drive 100a from a power level list (e.g., a drop-down list). In some embodiments, the driver 100a receives control signals only from the modified AC decoder 200 as described below in connection with fig. 2A-2F. In other embodiments, the driver 100a may receive a control signal input from a circuit (not shown) that contains electronics to isolate the circuit from the driver 100a when the circuit generates the control signal.

In some embodiments, the driver 100a receives a control signal from the modified AC decoder 200. Fig. 2A illustrates one embodiment of a modified AC decoder 200. Fig. 2B is a schematic diagram of circuitry in an embodiment of a modified AC decoder 200. In some embodiments, the modified AC decoder 200 decodes the modified AC line signal pattern to extract the control signal command for dimming control of the driver 100. In some embodiments, the modified AC decoder 200 receives the modified AC line signal pattern as an unfiltered rectified DC voltage signal from the driver 100 as described above with reference to fig. 1A-1F. The modified AC decoder 200 may operate by detecting a length of time, referred to herein as an "off time," during which the voltage of the AC voltage waveform is substantially equal to zero, and interpreting the length of time and converting to a control signal. The off-time may occur at or near the zero-crossing point of each half-cycle in the modified AC voltage waveform. The off-time may be substantially centered at a zero-crossing point of the AC waveform; in other words, the off-time portion before the zero-crossing point may be substantially equal to the off-time portion after the zero-crossing point. In other embodiments, the off-time portion before the zero-crossing is slightly shorter or slightly longer than the off-time portion immediately after the zero-crossing. The modified AC voltage waveform may be modified from a conventional sinusoidal waveform to a waveform that switches to 0V for a particular amount of time before and after each zero intercept in the sinusoidal waveform; the length of time that the waveform is at 0 volts may be set by a modified AC encoder 300 as set forth in more detail below in connection with fig. 3A-3H.

In some embodiments, the modified AC decoder 200 includes a processor 201 that measures the length of the off time and transforms the length into a pulse width modulated signal; the pulse width modulated signal may be a constant on "logic 1" signal when the off-time length is a value indicative of a control signal (e.g., the largest command possible in the voltage control signal). The processor 201 may be any processor suitable for executing the algorithm described with reference to fig. 2A-2F using the circuit elements described with reference to fig. 2A-2F. As a non-limiting example, the processor 201 may be a microprocessor. The processor 201 may be a microcontroller. The processor 201 may be a Central Processing Unit (CPU). The processor 201 may be a neural network. The processor 201 may be any other kind of processor used in a computing device, including, for example, a Graphics Processing Unit (GPU). By way of non-limiting example, the processor 201 may be a PIC12F1822 microprocessor manufactured by Microchip technology, Inc. of Chandler, Arizona, or similar product.

In some embodiments, the control signal output by the processor is a pulse width modulated signal. Fig. 2C shows a pulse width modulation output from the processor 201 associated with an off time corresponding to one control signal. Fig. 2D shows a pulse width modulation output from the processor 201 associated with another off-time corresponding to another control signal. The pulse width modulated signal may correspond to a voltage control signal to which the pulse width modulated signal is to be converted, for example, generated by the PWM/DC converter 202 as described below, as set forth in more detail below. As a non-limiting example, in some embodiments, when the processor 201 detects a 1 millisecond off time, it generates an output that results in a maximum voltage control signal (e.g., 10 vdc of the 0-10V DC control signals); in some embodiments, when the processor 201 detects a 2 millisecond off time, the processor produces an output that results in a minimum signal (e.g., a 0V DC signal, or a signal in the 0 to 10V DC signal range that is close to 0V DC). Continuing the example, an intermediate off-time length of between 1 and 2 milliseconds may correspond to a voltage control output having an intermediate value between a minimum voltage level and a maximum voltage level; in some embodiments, the control signal output varies as a substantially linear function of the turn-off time. The processor may receive a signal having one substantially constant voltage value (logic 0) indicating an off-time per half cycle and a second substantially constant voltage value (logic 1) indicating an on-time per half cycle.

In some embodiments, processor 201 uses a running average software filter to provide smoothing operations and minimize flicker due to noise transients. In some embodiments, the running average filter replaces the values of discrete data points obtained from a range centered on the selected data point with an average of the values of the discrete data points; thus, the running average filter may sample the incoming off-time and average across a set of previous samples (e.g., the previous 31 samples), producing a number equal to the average across the set of previous samples. Thus, if the off-time length is changed from 1ms to 1.5ms for a transient time period (e.g., as may be produced by random fluctuations in the voltage in the AC input), the effect may be minimized and the control signal output may change by a negligible amount; if the changed off time is continuous, the average value may be shifted to reflect the continuous change, producing a modified control signal output.

The modified AC decoder 200 may include a PWM/DC converter 202 that converts the pulse width modulated signal to a voltage control signal. The PWM/DC converter 202 may include an RC network 203 composed of at least one resistor and at least one capacitor that averages the pulse width modulated signal to generate a constant voltage. In some embodiments, the constant voltage is at a level between 0V and the "on" or "logic 1" voltage of the pulse width modulated signal; where the "on" voltage is equal to the maximum voltage of the voltage control signal, the constant voltage output by the RC network may be a value within the range of the voltage control signal. The processor may be programmed to generate the pulses necessary to generate an average voltage equal to the voltage control signal for the detected off-time. The pulse width modulated signal example from fig. 2C results in a lower constant voltage output from the PWM/DC converter 202 compared to the pulse width modulated signal example from fig. 2D. In embodiments where the "on" (logic 1) voltage of the pulse width is not equal to the maximum voltage control value, the PWM/DC converter 202 may include an amplifier 204 that maps a constant voltage to a voltage control range; for example, the amplifier may map a constant voltage generated over a range between 0 and 5V DC onto a 0 to 10V DC range. For example, where the processor 201 outputs pulses having an "on" voltage of about 5V DC or slightly less than 5V DC, the amplifier 204 may have a gain of 2 or slightly greater than 2, modifying the constant voltage to a voltage between 0 and 10V. As shown in fig. 2B, the amplifier 204 may be an operational amplifier whose negative feedback network causes the gain of the amplifier to generate a voltage such that the voltage generated by the feedback network at the inverting input is equal to the input at the inverting input of the operational amplifier; those skilled in the art will appreciate that selecting the resistors that constitute the voltage divider will permit the gain of the operational amplifier to be calibrated to any desired number up to the drive voltage of the amplifier. The amplifier 204 may be powered by the power supply 107 of the driver 100 as described above with reference to fig. 1A-1F. The PWM/DC converter 202 may include a voltage follower 205 that replicates the output of the converter 202; the voltage follower 205 may present a high input impedance to the converter 202, ensuring that the voltage control signal is not dropped by a load (e.g., driver 100) connected to the modified AC decoder, while providing the current necessary to maintain the control signal output at the output of the voltage follower 205. The voltage follower 205 may also be powered by the power supply 107 of the driver 100 as described above in connection with fig. 1A-1F. In some embodiments, the voltage output by the PWM/DC converter never fully drops to 0; in some embodiments, where the control signal is a voltage control signal, the driver 100 may use the zero current shutdown device 109 to detect a near zero voltage in the control signal and cut off current from the at least one current regulator 105, as shown above with reference to fig. 1A-1F. In other embodiments, the driver 100 mimics a conventional triac dimmer in the sense that it reduces the light output to a very weak level, but does not turn off.

The modified AC decoder 200 may include a comparator 206 that detects the beginning and end of the off-time in the modified AC signal and switches the logic level at the output of the comparator 206 at both the beginning and end of the off-time. As a non-limiting example, where the modified AC signal has been rectified by the rectifier 103 described above in connection with fig. 1A-1F, the comparator 206 may have an internal voltage threshold below which the comparator 206 switches the output logic level to logic 0; for example, the comparator may have an internal voltage threshold of.4V, such that it outputs a logic 0 signal for a rectified voltage range between.4V and 0V. In some embodiments, the switching of the logic levels by the comparators results in a clear signal to the processor 201 that delineates the off-time conveyed in the modified AC signal. The modified AC decoder 200 may also include a resistive voltage divider 207 before the comparator 206. Resistive voltage divider 207 may reduce the overall voltage of the modified AC waveform delivered to comparator 206. In some embodiments, the resistive voltage divider 207 enables the comparator 206 to capture the true width of the turn off time and provide a consistent logic 0 output to the processor 201. The resistive voltage divider 207 may also enhance the noise immunity of the modified AC decoder 200. Fig. 2E and 2F illustrate oscilloscope outputs showing a rectified modified AC signal divided by resistive voltage divider 207 that is higher than the corresponding logic signal output by comparator 206 input to processor 201; in some embodiments, the use of comparator 206 and resistive voltage divider 207 enhances the ability of processor 201 to convert the off-time profile 230 in the rectified modified AC signal to clear and reproducible logic 1 and 0 profiles 231. In some embodiments, a first resistive voltage divider 207 may be used to convert a modified AC signal of a first amplitude to a desired amplitude for the comparator 206, and a second resistive voltage divider 207 may be used to convert a modified AC signal having a second amplitude to a desired amplitude for the comparator 206; as a non-limiting example, one resistive voltage divider may be installed for a 120V line voltage, a second resistive voltage divider may replace the first resistive voltage divider for a 220V line voltage, a third resistive voltage divider may be swapped in for a 277V line voltage, and a fourth resistive voltage divider may be installed for a 480V line voltage. In some embodiments, the only step necessary to have the modified AC decoder 200 operate in the new line voltage is to install a new resistive voltage divider 207. In some embodiments, the resistive voltage divider 207 is adjustable; for example, in some embodiments, the modified AC decoder 200 includes a switch (not shown) that allows a user to connect the select resistive voltage divider 207 as needed to operate the modified AC decoder 200 in a particular line voltage. The switches may function as described above with reference to fig. 1A-1C for resistive divider switch 108; for example, the resistive voltage divider may include a potentiometer. The potentiometer may be controlled by a manual knob having a flag to indicate the position of the knob to place the potentiometer at the correct resistance level in order to allow the modified AC decoder 200 to function at a given line voltage.

In some embodiments, the modified AC decoder 200 includes a DC voltage converter 208. The DC voltage converter 208 may convert DC power received from the power supply 107 of the driver 100 as described above with reference to fig. 1A-1F to different DC voltages required by one or more components of the modified AC decoder 200. The DC voltage converter 208 may include a voltage reference 209. For example, in some embodiments, processor 201 has an operating voltage of 5V DC instead of 10V DC; the DC voltage converter 208 may include a voltage reference 209 that outputs 5 vdc. As a non-limiting example, the voltage reference 209 may be a MAX 61055V DC reference manufactured by Maxim Integrated products of san Jose, Calif. In some embodiments, some components are powered by the output of the DC voltage converter 208, while other components are powered by the power supply 107 input; as a non-limiting example, the processor 201 and the comparator 206 may be powered by the DC voltage converter 208, while the components of the PWM/DC converter 202 may be powered by the power supply voltage.

The modified AC decoder 200 may set one or more of its input and output terminals into a junction for connection to other devices. As a non-limiting example, the modified AC decoder 200 may have a first three pin connector 210 having a return on a first pin, a control signal output on a second pin, and a power supply input on a third pin. The modified AC decoder 200 may have a second three pin connector 211 with a return on the first pin and an unfiltered DC input on the second pin.

Joints

210, 211 may be adapted to connect to

joints

119, 120 of drive 100 b; for example, where the

connectors

119, 120 of the drive 100b are 91614-303G connectors as described above in connection with FIGS. 1A-1D, the

connectors

210, 211 of the modified AC decoder 200 may be 95293-03G connectors manufactured by FCI American technology, Inc. of Carson, Nevada.

Fig. 3A illustrates a block diagram of a modified AC encoder 300. In some embodiments, modified AC encoder 300 converts an AC signal received at input port 301 to a modified AC signal containing an off-time as described above with reference to fig. 2A-2F, which is output at output port 302. In some embodiments, the modified AC signal has one off time per half cycle. The off-time may be a time period during which the voltage of the modified AC signal is substantially zero. In some embodiments, the length of the off time corresponds to the information transmitted by the modified AC encoder 300. The off-time may be centered at a zero-crossing point of a substantially sinusoidal waveform of the modified AC signal. In some embodiments, centering the off-time at the zero-crossing point places the power interruption created by the off-time at a point in the AC waveform where the transmitted power is typically minimal; thus, the modified AC signal may transmit an essentially unreduced amount of power to the appliance driven by the modified AC signal. Furthermore, placing the turn-off time at about the zero-crossing may minimize voltage transients caused by the turn-off time as compared to AC signals generated by conventional dimming devices (e.g., triac dimmers).

In some embodiments, the modified AC encoder 300 includes a bipolar switch 303 that is switched off during off times to prevent conduction of the AC signal and is switched on at other times to permit transmission of the AC signal through the bipolar switch 303. In some embodiments, the bipolar switch 303 is controlled by the processor 304. The processor 304 may control the bipolar switch 303 through a gate drive circuit 305. In some embodiments, as shown in fig. 3B, the bipolar switch 303 includes two transistors; in some embodiments, the bipolar switch 303 includes a first MOSFET 306 and a second MOSFET 307, the source of the first MOSFET 306 is electrically connected to the source of the second MOSFET 307; the gate of the first MOSFET 306 may be electrically connected to the gate of the second MOSFET 307. In one embodiment, the drain of the first MOSFET 306 points in the opposite direction to the drain of the second MOSFET 307; thus, during one half cycle, if the first MOSFET 306 is turned on, the AC waveform may be conducted through the freewheeling diodes of the first and second MOSFETs 306, 307, and during the opposite half cycle, the AC waveform may be conducted through the freewheeling diodes of the second and first MOSFETs 307, 306. By way of non-limiting example, the first MOSFET 306 may be IXFT24N80P, manufactured by FCI america technology, llc of carson, nevada, or a similar product. In some embodiments, the second MOSFET is any MOSFET suitable for use as the first MOSFET. Although the first MOSFET 306 and the second MOSFET 307 are described for purposes of simplicity, any voltage controlled transistor (as employed in the disclosed modified AC encoder 300) that can have its capacitance at the control point (i.e., its gate, base, or similar component) remain essentially constant for at least one half cycle can be used for either the first MOSFET 306 or the second MOSFET 307. The AC line input 301 may enter the drain of the first MOSFET 306 and the modified AC output 302 may exit the drain of the second MOSFET 307.

The first MOSFET 306 and the second MOSFET 307 can be turned on and off in common in response to a voltage pulse signal emitted by the gate drive circuit 305; the voltage signal may correspond to the beginning and end of the turn-off time calculated by the processor 304, as set forth in more detail below. When the first MOSFET 306 is conductive, the second MOSFET 307 may permit conduction through its freewheeling diode 307 a. Likewise, when the second MOSFET 307 is conductive, the first MOSFET 306 may permit conduction through the freewheeling diode 306a of the first MOSFET 306. In some embodiments, the original AC waveform is conducted through the bipolar switch 303 that is essentially unchanged except during the off time. When the first MOSFET 306 and the second MOSFET 307 receive a positive voltage pulse from the gate drive circuit 305, the gate capacitance of each of the first MOSFET 306 and the second MOSFET 307 charges, causing the first MOSFET 306 and the second MOSFET 307 to turn on and remain turned on and conductive until the gate capacitance discharges due to receiving a negative voltage pulse, due to gradually discharging through a resistor in the absence of a gate pulse, as described in more detail below. In some embodiments, the first MOSFET 306 and the second MOSFET 307 receive a positive voltage pulse at the end of the programmed turn-off time, causing the freewheeling diodes of one of the first MOSFET 306 and the second MOSFET 307 and the other of the first MOSFET 306 and the second MOSFET 307 to conduct an essentially unmodified AC waveform. When the first MOSFET 306 and the second MOSFET 307 receive a negative voltage pulse, the negative pulse causes the gate capacitance of the first MOSFET 306 and the second MOSFET 307 receiving the pulse to discharge, and the first MOSFET 306 and the second MOSFET 307 are turned off; in some embodiments, the first MOSFET 306 and the second MOSFET 307 have conducted most of the unmodified AC waveform during the programmed on-time, and receive a negative pulse at the beginning of the programmed off-time, turning off the AC waveform until the first MOSFET 306 and the second MOSFET 307 are activated by a new positive voltage pulse from the gate drive circuit 305 to allow the AC waveform to resume being transmitted through the bipolar switch 303.

In some embodiments, the pairs of small switching transistors 308 a-308 b prevent the gates of the first MOSFET 306 and the second MOSFET 307 from discharging too quickly when directing a pulse to the gates of the first MOSFET 306 and the second MOSFET 307. The switching transistors 308 a-308 b may be MOSFETs. As a non-limiting example, the switching transistors 308 a-308 b may be IRML2803 MOSFET, manufactured by International rectifier corporation of Elssento, Calif., or a similar product. In some embodiments, when the gate drive circuit 305 directs a pulse of a first polarity toward the switching transistors 308 a-308 b, one switching transistor 308a conducts the pulse through its freewheeling diode; the pulse turns on the gate of the other transistor 308b to cause it to conduct a pulse as well, completing the circuit. When a pulse of opposite polarity is sent from the gate drive circuit 305, the freewheeling diode of the other transistor 308b conducts the pulse, while the pulse turns on the gate of the first transistor 308a to also conduct the pulse. Between the pulses, both switching transistors 308 a-308 b are turned off so that the gate capacitances of the first MOSFET 306 and the second MOSFET 307 are not discharged through the switching transistors 308 a-308 b. In some embodiments, the discharge circuit 309 drains parasitic capacitance from the first MOSFET 306 and the second MOSFET 307 during the off time, as described in more detail below in connection with fig. 3B.

In some embodiments, the gate drive circuit generates the voltage pulse by feeding a substantially square wave into the transformer 310. By way of non-limiting example, the transformer may be an 78253/35JC transformer manufactured by Tonta Power Solutions (Murata Power Solutions) of Mansfield, Mass, or similar product. In some embodiments, the transformer 310 is designed to saturate very quickly, resulting in only brief pulses of opposite polarity occurring at the 0-1 and 1-0 transition points. Fig. 3C and 3D illustrate two exemplary square waves output by the processor 304. FIG. 3E illustrates an exemplary form of a transformer output; the positive and negative square wave inputs result in very brief positive or negative spikes in the output voltage, respectively, that return to zero almost immediately upon transformer saturation. The square wave in fig. 3C may correspond to an off-time of about 2 milliseconds, while the square wave in fig. 3D may correspond to an off-time of about 1 millisecond. In some embodiments, the square wave is provided to one terminal of transformer primary 310 by non-inverting gate driver 311 (e.g., a non-inverting MOSFET driver) and to a second terminal of transformer primary 310 by inverting gate driver 312 (e.g., an inverting MOSFET driver). As a non-limiting example, the non-inverting gate driver 311 may be a TPS2829 non-inverting high speed MOSFET driver manufactured by texas instruments, dallas, texas, or similar product. As a non-limiting example, the inverted gate driver 311 may be a TPS2828 inverted high speed MOSFET driver manufactured by texas instruments, dallas, texas, or similar product. In some embodiments, both inverting gate driver 312 and non-inverting gate driver 311 generate their square waveforms in response to a square wave input from processor 304. In some embodiments, the square wave output by the processor 304 has a peak at logic 1 and a valley at logic 0; the logic 1 portion of the processor 304 square wave output may be provided to the transformer primary through the non-inverting gate 311, while the logic 0 portion may be provided as a negative logic 1 pulse to the transformer primary such that the transformer primary 310 receives a square wave having twice the amplitude and inverted polarity of the processor output.

The processor 304 may be any suitable processor for executing the algorithm described with reference to fig. 3A-3H using the components described with reference to fig. 3A-3H. The processor 304 may be any of the processors 201 as described above with reference to fig. 2A-2F. As a non-limiting example, the processor 304 may be a microprocessor. The processor 304 may be a microcontroller. The processor 304 may be a Central Processing Unit (CPU). The processor 304 may be a neural net. Processor 304 may be any other kind of processor used in a computing device, including, for example, a Graphics Processing Unit (GPU). By way of non-limiting example, the processor 304 may be a PIC16F 18238 microcontroller manufactured by Microchip technology, Inc. of Chandler, Arizona, or similar product.

In some embodiments, the processor 304 receives the rectified waveform of the AC line voltage and the control signal, calculates an off time corresponding to the control signal, and outputs a signal to the gate drive circuit 305 that directs the gate drive circuit 305 to cause the bipolar switch 303 to switch off the modified AC voltage during the calculated off time. The control signal may be any of the control signals described above in connection with fig. 1A-2F. In some embodiments, the processor 304 places the turn-off time near the zero crossing of the AC waveform. As described above, placing the off-time close to the zero crossing of the AC waveform may eliminate voltage transients associated with load current interruption. In addition, a load driven by the modified AC wave may receive negligible power during portions of the AC waveform proximate to the zero crossing; for example, where the load is a net of LEDs, conduction may only occur near the peak of the AC line voltage waveform, causing the waveform near the zero crossing to be modified to have essentially no effect on the performance of the net of LEDs.

In some embodiments, the processor 304 determines the location of a zero voltage point in the AC input line. The processor 304 may use the sine wave equation V by using the frequency and peak voltage of the AC waveform_{instantaneous}＝V_peaksin (ω t) determines the zero voltage point by calculating the instantaneous voltage over time, where ω is the angular frequency of the AC waveform. The processor 304 may determine the initial voltage by sampling the AC waveform instantaneous voltage. The peak voltage and angular frequency of the AC waveform may be stored in a memory accessible by the processor 304. In other embodiments, the processor 304 detects the zero crossing point by detecting the point of a logic 0 at which the AC waveform falls below a threshold voltage; for a given waveform and threshold voltage, the processor 304 may be programmed to detect how long before the actual zero crossing point a logic 0 detection occurs. In some embodiments, the processor combines logic 0 detection with the calculation of the zero crossing point to determine how often logic 0 detection occurs before the zero crossing point. Modified AC encoder 300 may include a resistive voltage divider 313 that divides the voltage of the AC waveform; the instantaneous voltage of the divided AC waveform may be calculated as V_{instantaneous}Voltage divider partial pressure ratio V_peaksin (ω t), where the divider division ratio is the fraction of the instantaneous voltage provided to processor 304 by resistive divider 313. In some embodiments, the smaller the voltage divider division ratio, the closer to the actual zero crossing point the logic 0 detection will occur for a given threshold voltage. In some embodiments, the resistive voltage divider 313 has at least one resistor selected to cause a logic 0 detection point to occur slightly more than 1 millisecond before the actual zero crossing point; for example, a resistive voltage divider forming a voltage divider division ratio of 1/51 may cause a zero detection point to occur slightly more than 1 millisecond before the zero crossing point. Different resistive voltage dividers may be selected to cause logic 0 detection to occur slightly more than 1 millisecond before the zero crossing of different AC line voltages (e.g., 230V or 480V lines). In some embodiments, the resistive voltage divider 313 is adjustable; for example, switches or potentiometers (not shown) may allow a user to calibrate the resistive voltage divider as necessary to allow the modified AC encoder 300 to operate at a given line voltage, as described above with reference to fig. 2A-2F.

In some embodiments, the resistive voltage divider 313 is selected to cause a logic 0 detection point to occur at a known number of microseconds before the zero crossing point. The processor 304 may be configured to calculate a linear function of the control signal to determine how many microseconds after the detection point of logic 0 to begin the turn off time; in some embodiments, the processor 304 computes a second linear function of the control signal to determine how many microseconds after the detection point of logic 0 to end the off-time. The processor 304 may calculate the off-time by setting the start and end of the off-time relative to the determined zero-crossing point, as described above. In some embodiments, the time from the beginning of the zero crossing is substantially the same as the time from the zero crossing to the end time, such that the off time is substantially centered at the zero crossing; the "off" period may move slightly to the left or right from the center as the AC line voltage changes, but not enough to disrupt proper operation. In some embodiments, the duration of the off-time (which is the time from the beginning to the end of the off-time) is at least 1 millisecond long; in some embodiments, a minimum off time of 1 millisecond ensures that the "on-to-off and" off-to-on "transitions are readily detectable by a device that interprets the off time as a signal (e.g., the modified AC decoder 200) as described in more detail above in connection with fig. 2A-2F. In some embodiments, the off time is at most 2 milliseconds; a maximum time of 2 milliseconds may ensure minimal disruption to the modified AC waveform. In some embodiments, the processor 304 maps the control signal to a calculated turn-off time. As a non-limiting example, where the control signal is a 0-to-10V DC signal, the mapping function may be a linear function, whereby a 0V DC control signal causes the processor 304 to output an off-time of 2 msec duration (approximately 1 msec on either side of the zero crossing), a 5V DC control signal causes the processor to output a 1.5 msec off-time (approximately.75 msec on either side of the zero crossing), and a 10V DC control signal causes the processor 304 to output a 1 msec off-time (approximately.5 msec on either side of the zero crossing); values between those three 0-10V DC values may cause processor 304 to output off-times between the three off-time values, as determined by the linear function implementing the three mappings described. In some embodiments, an "off" input to the processor provided by the on-off switch as described in more detail below in connection with fig. 3B causes the processor to stop driving the gate driver to direct the bipolar switch 303 to close the modified AC line, shutting off power to downstream devices, as described above with reference to fig. 3A-3B. FIG. 3F illustrates an unmodified rectified AC input; fig. 3G-3H illustrate two rectified modified AC waveforms having different off times. Alternatively, the on-off switch used as a logic controller to the processor is replaced by an on-off (single or three-way) switch that cuts off power to the entire dimmer circuit.

The input to the processor 304 may include at least one control signal input 314. The control signal input 314 may be connected to an external port 315 that may accept external control signals from any device capable of delivering control signals; in some embodiments, the external port is connected to a wireless receiver that generates control signals, as described above. The external port 315 may be connected to any device that can generate a control signal, such as a dimmer switch (e.g., a sliding potentiometer), a potentiometer operated by a knob, a capacitive dimmer knob, a programmable logic controller, or other device. In some embodiments, the means to supply the control signal includes circuitry to isolate the means from the modified AC encoder 300; in other embodiments, the modified AC encoder 300 contains circuitry to isolate the external port 315 from the rest of the modified AC encoder 300. The external port 315 may be scaled by a resistive voltage divider 315a to input signals at a voltage range acceptable by the processor 304; for example, where the processor 304 is configured to accept a 0-5V DC control signal, the resistive voltage divider 315a may divide the voltage of the 0-10V DC control signal in half. The control signal input 314 may be connected to a dimmer control 316 incorporated in the modified AC encoder 300. The dimmer control 316 may be a potentiometer, such as a dimmer slide potentiometer. The dimmer control 316 may also be calibrated to input control signals within a range that the processor 304 is configured to accept, such as a voltage control range from 0 to 5V DC. In some embodiments, the modified AC encoder 300 includes both an external port 315 and a dimmer control 316 that may be connected to the control signal input 314. The external port 315 and the dimmer control 316 may be connected via a switch 317 that enables one or the other to be selected as the source of the control signal; the switch 317 may be a manual switch. In some embodiments, the modified AC encoder 300 has the dimmer control 316 and does not have the external port 315; fig. 3I is a block diagram depicting an embodiment of a modified AC encoder 300 with a dimmer control 316 and without an external control signal port 315. In other embodiments, the modified AC encoder 300 has the external control signal port 315 and no dimmer control 316; fig. 3J is a block diagram depicting an embodiment of the modified AC encoder 300 with the external control signal port 315 and without the dimmer control 316. The control signal port 315 may be connected to the rest of the modified AC encoder 300 via an isolated control signal transformer that electrically isolates the port 315 from the rest of the circuitry in the modified AC encoder 300.

In some embodiments, modified AC encoder 300 includes an on-off switch 318. In some embodiments, the processor 304 interprets the on-off switch 318 placed in the "off" position as a command not to activate the gate drive circuit 305. In some embodiments, the bipolar switch 303 includes a resistor 319 that discharges the gate capacitance of each of the first MOSFET 306 and the second MOSFET 307 in the absence of a pulse from the gate drive circuit 305; the discharge of the gate capacitance of both the first MOSFET 306 and the second MOSFET 307 can shut off both the first MOSFET 306 and the second MOSFET 307, causing the modified AC line to stop conducting and shutting off power to all devices attached to the modified AC line, including the driver 100, the load 110 driven by the driver 100, the adapter 126 powered by the driver 100, and the modified AC decoder 200 powered by the driver 100. In some embodiments, when the on-off switch 318 is in the "on" position, the processor converts the voltage at the control signal input 314 to on and off time signals, as described above with reference to fig. 3B.

The input to the processor 304 may include an AC line voltage sample input 320. In some embodiments, the line voltage sample input 320 provides a waveform representation of an AC line voltage waveform to the processor 304. In some embodiments, the AC line voltage waveform is rectified by a rectifier 321 before being input to the AC line voltage sample input 320. The rectifier 321 may be any rectifier suitable for use as the rectifier 103 as disclosed above with reference to fig. 1A-1F. In some embodiments, the rectifier 321 is a full-wave rectifier. The rectifier 321 may be a bridge rectifier. The AC line voltage waveform may be reduced using the resistive voltage divider 313 as described above with reference to fig. 3B.

An input to the processor 304 may include a power supply 322. The power supply 322 may use the transient voltage suppressor 323 and the capacitive filter 324 to generate a stable DC voltage from the AC line voltage, as described above with reference to fig. 1A-1F. In some embodiments, the power supply 322 includes a diode 323a to further reduce the voltage to a desired stable value. The regulated DC voltage may be 10V DC. In some embodiments, the AC line voltage is provided to the power supply 322 in a form rectified by a rectifier 321. The power supply 322 may include a voltage converter 325 to convert the power supply voltage to a second voltage; the voltage converter 325 may be constructed as described above for the DC voltage converter 208 with reference to fig. 2A-2B. The voltage converter 325 may generate a DC voltage of 5V. In some embodiments, the voltage from the voltage converter 325 powers the processor. In some embodiments, the voltage from the voltage converter 325 powers the non-inverting gate driver 311. In some embodiments, the voltage from the voltage converter 325 powers the inverting gate driver 312. In some embodiments, the dimmer control 316 is powered by a voltage from the power supply 322 itself.

In some embodiments, the discharge circuit 309 drains parasitic capacitance from the first MOSFET 306 and the second MOSFET 307 during the off time through a single transistor 326 that connects the modified AC line to the return through a full wave rectifier 327. Transistor 326 may be turned on during the off time, connecting and discharging any non-zero voltage on the modified AC line across the resistor during the off time. Any suitable circuit may turn on transistor 326 during the off time. For example, transistor 326 may be turned on by a positive voltage from inverted gate driver 312, such that transistor 326 is turned on; when the non-inverted square wave is a logic 1 and the inverted square wave is a logic 0. As an example, transistor 326 may be a MOSFET having a gate connected to the output of an inverting MOSFET driver. The leakage circuit 309 may contain any other set of elements that can be used to drain parasitic capacitance; for example, instead of being rectified, the leakage circuit 309 may contain a bipolar switch similar to the bipolar switch 303 described above that is open during the off time.

The modified AC encoder 300 may be housed in a housing (not shown). The housing may be shaped to fit in a wall recess. In some embodiments, the housing may be secured in a wall recess; the housing may have screw holes or fastener-free engagement features that allow the housing to be snapped into place in the wall recess. The housing may contain manual controls that permit the user to operate the dimmer 316 or the on-off switch 318; for example, the on-off switch 318 may be a conventional light switch. The on-off switch 318 may be a push button switch. The dimmer 316 may be connected to a manual slide switch or to a rotatable knob.

Fig. 1D illustrates an exemplary network in which a modified AC encoder 300 feeds a modified AC signal to a first driver 100a driving a first load 110a, a second driver 100b driving a second load 110b, a third driver 100c driving a third load 110c, and a fourth load 110D directly connected to the modified AC line voltage. In a non-limiting example, the first and third drivers 100a and 100c are connected to modified AC decoders 200 a-200 b that convert the off-times encoded by the modified AC encoder 300 into control signals. Thus, the first and third drivers 100a and 100c may reduce the current to the first and third loads 110a and 110c as specified in the modified AC line by the control signals encoded by the modified AC encoder 300. Continuing the example, the second driver 100b is not connected to the modified AC decoder, and thus it drives the second load 110b at full power. The fourth load 110d may be any AC appliance; for example, the fourth load 110d may be an electrical appliance that is not a lighting device. Other appliances may require a substantially normal AC signal to operate and may operate effectively at any dimming level. The fourth load 110d may be entirely drawn from the modified AC line as if the modified AC line were a normal AC line. If the off switch of the modified AC encoder 300 is activated, the modified AC line may stop conducting, and the first driver 100a, the first load 110a, the second driver 100b, the second load 110b, the third driver 100c, the third load 110c, and the fourth load 110d may all stop operating.

In some embodiments, the modified AC encoder 300, the modified AC decoder 200, the adapter 126, and the driver 100 as described above present a simple design that requires a minimum number of low cost components to implement. By gating the AC line "on" and "off based on the commanded brightness, the modified AC line similarly supplies power to the dimmable and non-dimmable accessories. Non-dimmable accessories that are not configured to decode the signal from the modified AC encoder 300 may run at full power on the modified AC line, but turn on and off when power to the accessory is turned off in response to operation of the on-off switch 318. The modified AC line functions essentially in the same manner as an unmodified AC line for any device that is not capable of decoding the off-time signal generated by the modified AC encoder 300; thus, in some embodiments, when modified AC encoder 300 commands a device capable of decoding the off-time signal to dim, other devices driven by the modified AC line continue to operate at full power as before.

Fig. 4 illustrates some embodiments of a method 400 for encoding signals in a modified ac line. The method 400 includes receiving, by a processor, a control signal (401). The method 400 includes sampling, by a processor, an ac waveform having a substantially regular cycle period generated by an ac power source (402). The method 400 includes calculating, by a processor, an off-time having a duration based on a control signal (403). The method 400 includes disconnecting, by the processor, a bipolar switch connecting the alternating current power source to the modified alternating current (404). The method 400 includes turning on, by a processor, a bipolar switch upon passage of a duration (405).

Referring to fig. 4 in more detail and to fig. 1A-3J, the processor 304 receives a control signal (401). This may be implemented as described above with reference to fig. 1A-3J. The control signal may be any of the control signals as described above in connection with fig. 1A-3J. As a non-limiting example, the control signal may be a direct current voltage control signal, as described above with reference to fig. 1A-3J; the control signal may be a DC control signal of 0 to 10V. The processor 304 may receive control signals via the control input 314 as described above with reference to fig. 3A-3J. The processor 304 may receive a control signal from the dimmer control 316. The processor 304 may receive control signals from an external device, such as a wireless device.

The processor 304 samples 402 an ac waveform having a substantially regular cycle period generated by the ac power source. The processor 304 may sample the waveform using the AC line voltage sampling input 320 as described above in connection with fig. 3A-3J.

The processor 304 calculates an off-time having a duration based on the control signal (403). This may be implemented as described above with reference to fig. 3A-3J. In some embodiments, the processor 304 calculates the duration of the off-time by calculating a function of the control signal; for example, where the control signal is a DC signal of 0-10V, the processor 304 may calculate the duration using a linear function, whereby according to the linear function, 0 maps to an off-time of duration 2 milliseconds, 1 maps to an off-time of duration 1 millisecond, and intervening control signal values map to durations between 1 millisecond and 2 milliseconds. In other embodiments, the processor 304 maps the control signals to a duration stored in a memory of the processor 304.

The processor 304 switches off the bipolar switch 303(404) connecting the ac power source to the modified ac power. In some embodiments, the processor 304 switches off the bipolar switch 303 as described above in connection with fig. 3A-3J. In some embodiments, the processor 304 switches off the bipolar switch for substantially half the duration before the zero crossing time in the alternating current waveform; for example, where the off-time duration is 2 milliseconds, the processor 304 may turn off the bipolar switch 1 millisecond before the zero-crossing time. The processor 304 may turn off the bipolar switch for substantially half the duration before the zero crossing time by: the zero crossing time is calculated and the bipolar switch is switched off for a duration approximately half the time before the zero crossing time. In some embodiments, processor 304 calculates the zero-crossing time by: detecting a voltage peak time in the alternating current waveform to solve an equation describing a waveform of zero intercept time in the alternating current waveform; the equation may be a sinusoidal equation for the voltage of the ac power source, as described above with reference to fig. 3A-3J. Solving the equation may involve adding a quarter cycle to the voltage peak time; for example, a regular sine wave has a zero-intercept quarter cycle of the sine wave after the voltage peak. The voltage peak may be a local minimum voltage. The voltage peak may be a local maximum voltage.

In other embodiments, the processor 304 detects a logic 0 time at which the sampled alternating current waveform falls to logic 0, retrieves a stored value substantially equal to a difference between the logic 0 time and a zero crossing, subtracts half of the duration from the difference to obtain a turn-off time, and turns off the bipolar switch at the turn-off time. The logic 0 detection point may be set to reach the stored value prior to the zero crossing point using the resistive voltage divider 313 as described above with reference to fig. 1A-3J; in some embodiments, where the resistive voltage divider 313 is adjustable, the user may adjust the resistive voltage divider such that the amount of time that the logic 0 detection point is substantially equal to the stored value before the zero crossing point occurs.

The processor 304 turns on the bipolar switch 303(405) immediately after the duration elapses; that is, the processor 304 may turn on the bipolar switch 303 again when an amount of time equal to the duration has elapsed since the bipolar switch 303 was turned off from the processor 304. In some embodiments, the processor 304 turns on the bipolar switch 303 as described above in connection with fig. 1A-3J. The processor 304 may switch the bipolar switch 303 off and on again after the duration has elapsed; for example, the processor 304 may turn off the bipolar switch 303 before each zero crossing and turn it on again after each zero crossing. In some embodiments, interrupting the modified AC waveform near each zero crossing enables a device (such as decoder 200 described above with reference to fig. 2A-2F) to accurately determine the off-time duration despite voltage transients or other transient phenomena affecting the AC waveform.

Fig. 5 illustrates some embodiments of a method 500 for decoding a modified alternating current signal. The method 500 includes sensing, by a processor coupled to a modified alternating current line having a modified alternating current signal, an off-time in the modified alternating current signal (501). The method 500 includes issuing, by a processor, a control signal based on the detected off-time (502).

Referring to fig. 5 and to fig. 1A-3J in more detail, the processor 201 senses the off time in the modified alternating current signal (501). In some embodiments, the processor 201 senses the turn-off time as described above with reference to fig. 2A-2F. As a non-limiting example, the processor 201 may sense the off-time by detecting when the modified ac signal falls below a first threshold and detecting when the modified ac signal subsequently exceeds a second threshold. The threshold may be a positive or negative number; for example, the threshold may represent an absolute value such that a negative or positive voltage having an absolute value exceeding the threshold exceeds the threshold.

The processor 201 issues a control signal based on the detected off-time (502). In some embodiments, the processor 201 issues control signals as described above with reference to fig. 2A-2F. As a non-limiting example, the processor 201 may issue the control signal by issuing a pulse width modulated signal. In some embodiments, the processor 201 maps the off-time to a voltage level of the voltage control signal. The processor 201 may transmit a series of pulses having an average voltage level substantially equal to the mapped voltage level; in the presence of the PWM/DC converter 202, the converter 202 may convert the signal to a voltage control signal, as described above with reference to fig. 2A-2F. In some embodiments, processor 201 performs a running average filter as described above with reference to fig. 2A-2F. For example, the processor 201 may sense a plurality of off times in the modified alternating current signal and calculate an average of the plurality of off times. The processor 201 may issue a control signal based on the calculated average.

Fig. 6 presents a block diagram of an embodiment of an automatically reconfigured lighting circuit 600. The circuit 600 includes a first lamp block 601. The circuit includes a second light block 602. The circuit includes a first switching mechanism 603. The first switching mechanism 603 has a first state in which the first switching mechanism electrically connects the first light block 601 in parallel with the second light block 602. The first switching mechanism 603 has a second state in which the first switching mechanism 603 electrically connects the first light block 601 in series with the second light block 602. The circuit 600 includes a controller 604 electrically connected to the first switching mechanism 603, the controller 604 configured to sample a voltage of the power signal to the first and second light blocks 601, 602 to switch the first switching mechanism 603 to a first state when the voltage falls below a first threshold voltage, and to switch the first switching mechanism 603 to a second state when the voltage exceeds the first threshold voltage.

Looking in more detail at fig. 6, the circuit 600 includes a first light block 601. As further illustrated in fig. 7A, the first light block 601 includes at least one light 701. At least one electric lamp 701 may be any device that converts electrical energy into light; the light may include visible light as well as infrared and ultraviolet light. Without limitation, at least one electric lamp 701 may be fluorescent, incandescent, or electroluminescent. The at least one electric lamp 701 may be a Light Emitting Diode (LED). The at least one electric lamp 701 may be an Organic Light Emitting Diode (OLED). In some embodiments, the first lamp block includes a plurality of lamps; for example, the first light block 601 may include a plurality of LEDs ranging up to tens or hundreds of LEDs. In some embodiments, where at least one lamp 701 is a device that operates only when current flows in one direction, all lamps are connected to accept current flow in a single direction. In the case where the electric lamp in the first block is arranged to accept only one direction of current flow, the power signal may be rectified to cause current to flow in only that one direction; rectification may be performed using any rectification circuit including, but not limited to, a half-wave rectifier, a full-wave rectifier, or a bridge rectifier. In case the current through the first lamp block 601 always flows in the same direction, the end of the first lamp block 601 into which the positive current enters may be denoted as the "positive end" of the first lamp block, and the end of the first lamp block 601 from which the positive current exits may be denoted as the "negative end" of the first lamp block.

The circuit includes a second light block 602. The second light block 602 may include any light suitable for use in the first light block 601. The second light block 602 may include any number or configuration of lights suitable for the first light block 601. In some embodiments, the number of lamps in the second lamp block 602 is different from the number of lamps in the first lamp block 601; for example, the number of lamps in the second light block 602 may be selected to have a total forward operating voltage different from the minimum voltage of the first light block 601 defined as the block lighting. In some embodiments, the number of lamps in the first and second blocks is selected such that in the first state of the first switching mechanism 603, switching both blocks into a parallel configuration results in a forward operating voltage of a desired fraction value for the series configured forward operating voltage generated by the second state of the first switching mechanism 603; as a non-limiting example, the desired fraction value may be half of the forward operating voltage of the configuration in the second state of the first switching mechanism 603. In the case where the current through the second light block 602 always flows in the same direction, the end of the second light block 602 into which the positive current enters may be denoted as the "positive end" of the second light block 602, and the end of the second light block 602 from which the positive current exits may be denoted as the "negative end" of the second light block 602. Similarly, the entire portion of the circuit containing the first and second light blocks may be labeled "light circuit"; the point at which the positive current enters the lamp circuit may be denoted as the "positive terminal" of the lamp circuit, and the point at which the positive current leaves the lamp circuit may be denoted as the "negative terminal" of the lamp circuit.

In some embodiments, the first light block 601 is connected to the second light block 602 by one or more diodes 702 that permit current to flow between the first light block and the second light block when the first switching mechanism 603 is in one of the first and second states, but do not permit current to flow between the first light block and the second light block when the first switching mechanism 603 is in the other of the first and second states. The one or more diodes 702 may be positioned such that the one or more diodes are forward biased and conductive when the first lamp block 601 is in series with the second lamp block 602, and are reverse biased and therefore non-conductive when the first lamp block 601 is in parallel with the second lamp block 602. For example, in the embodiment illustrated in fig. 7A, the negative end of the first light block 601 is connected to the positive end of the second light block through a diode 702 that is forward biased in the same direction as the LEDs depicted in the first and second light blocks, such that when no other connection is made between the first light block 601 and the second light block 602, the diode is forward biased and current flows from the first light block 601 through the second light block 602; continuing the example, if in fig. 7A the positive end labeled "2" of the second light block 602 is connected to the positive end labeled "positive" of the light circuit and the negative end labeled "1" of the first light block 601 is connected to the negative end labeled "negative" of the light circuit, then the potential difference between the first light block 601 and the second light block 602 is no longer sufficient to forward bias the diode 702, which will not conduct.

Referring again to fig. 6, the circuit includes a first switching mechanism 603. The first switching mechanism 603 has a first state in which the first switching mechanism electrically connects the first light block 601 in parallel with the second light block 602. The first switching mechanism 603 has a second state in which the first switching mechanism 603 electrically connects the first light block 601 in series with the second light block 602. In some embodiments, as illustrated for example in fig. 7A, the first switch mechanism 603, when in the first state, connects the positive terminal of the first light block 601 to the positive terminal of the second light block 602; the connections may be direct, or may pass through one or more additional circuit elements. Each of the first and second light blocks 601, 602 may be connected to the negative terminal of the lamp circuit, either directly or through one or more additional circuit elements. For example, where the second light block 602 is connected in series or parallel with a third light circuit (as set forth in more detail below), the second light block 602 may be connected to the negative terminal of the light circuit through the third light block.

In a second state of the first switching mechanism 603, the first switching mechanism can connect the negative terminal of the first lamp block 601 to the positive terminal of the second lamp block 602; in the presence of a diode connecting the negative end of the first light block 601 to the positive end of the second light block 602, the switching mechanism can achieve a series connection by blocking the connection between the positive end of the first light block 601 and the positive end of the second light block 602, thereby forward biasing the diode 702 to electrically connect the negative end of the first light block 601 to the positive end of the second light block 602, as described above. The switching mechanism may alternatively use transistors or other devices to affect the connection.

In some embodiments, the first switching mechanism 603 includes at least one transistor. For example, as illustrated in fig. 7A, the first switching mechanism 603 may include a first transistor 703 that turns on to connect the positive terminal of the first light block 601 to the positive terminal of the second light block 602, as described above. The first transistor 703 may be any transistor suitable for transmitting a power signal from one part of the circuit to another. For example, the first transistor 703 may be a MOSFET, such as a power MOSFET. The first transistor 703 may be a p-channel MOSFET or an n-channel MOSFET. In some embodiments, the first transistor 703 receives the gate voltage directly from the output from the controller 604. In other embodiments, the first transistor 703 receives its gate voltage from a control transistor 704, which in turn is controlled by a signal from the controller 604. As a non-limiting example, the controller 604 may send a signal to turn on the control transistor 704, which may be any suitable transistor. The current through the control transistor 704 can be used to set the voltage at the gate of the first transistor 703 to turn on the first transistor 703; for example, where the first transistor 703 is a p-channel MOSFET, the control transistor 704 may provide a return path that drops the voltage at the gate of the first transistor 703 to turn on the first transistor 703, so that the first transistor 703 turns on and connects the positive terminal of the first lamp block 601 to the positive terminal of the second lamp block 602.

The first switching mechanism 603 may include a second transistor 705 that connects the negative terminal of the first lamp block 601 to the negative terminal of the lamp circuit when the first switching mechanism 603 is in the first state. The second transistor 705 may be any transistor suitable for transmitting a power signal from one part of the circuit to another. For example, the second transistor 705 may be a MOSFET, such as a power MOSFET. The second transistor 705 may be a p-channel MOSFET or an n-channel MOSFET. In some embodiments, the second transistor 705 receives the gate voltage directly from the output from the controller 604. In other embodiments, the second transistor 705 receives its gate voltage from the control transistor 704, which in turn is controlled by a signal from the controller 604. As a non-limiting example, the controller 604 may send a signal to turn on the control transistor 704, which may be any suitable transistor. The current through the control transistor 704 can be used to set the voltage at the gate of the second transistor 705 to turn on the second transistor 705; for example, where the second transistor 705 is a p-channel MOSFET, the control transistor 704 may provide a return path that drops the voltage at the gate of the second transistor 705 to turn on the second transistor 705, such that the second transistor 705 conducts and connects the negative terminal of the first lamp block 601 to the negative terminal of the lamp circuit (labeled "negative" herein). In some embodiments, as illustrated in fig. 7A, a single control transistor 704 controls both the first transistor 703 and the second transistor 705; alternatively, each of the first transistor 703 and the second transistor 705 may have its own control transistor.

In some embodiments, as described above, the first switch mechanism 603 enters the second state by disconnecting the connection between the positive terminal of the first light block 601 and the positive terminal of the second light block 602; the diode 702 may then be forward biased, permitting a series connection. In other embodiments, the first switching mechanism 603 includes one or more transistors (not shown) connecting the first light block 601 in series with the second light block 602; for example, a transistor may connect the negative terminal of the first lamp block 601 to the positive terminal of the second lamp block 602.

Referring again to fig. 6, the circuit 600 includes a controller 604 electrically connected to the first switching mechanism 603. The controller 604 may be any device suitable for use as the controller 201 as described with reference to fig. 2B or the controller 304 as described with reference to fig. 3B. The controller 604 is configured to sample the voltage of the power signals to the first light block 601 and the second light block 602. The power signal may be variable. In some embodiments, the power signal may be modeled by a substantially periodic waveform. The power signal may be substantially sinusoidal; for example, the power signal may be in the form of an alternating current. In other embodiments, the power signal is a rectified ac waveform; for example, the power signal may be a half-wave rectified waveform. In other embodiments, the power signal is a full-wave rectified waveform, for example, reasonably approximating | sin (ω t + φ) |. As illustrated in fig. 7C, the power signal may be generated by the rectifier 103, which may be a half-wave, full-wave, or bridge rectifier, as described above with reference to fig. 1A-1C.

In some embodiments, as illustrated in fig. 7C, controller 604 samples the power signal by sampling the voltage of resistive voltage divider 706. Resistive voltage divider 706 may be used to scale the amplitude of the power signal such that the amplitude of the power signal is within a tolerable range of the input of controller 604. Resistive voltage divider 706 may also be connected to a voltage limiting device 707 for clamping the voltage within a safe range of the input of controller 604. The voltage limiting device 707 may be a zener diode. The voltage limiting device 707 may include a double Schottky (Schottky) diode that limits the voltage to a safe range between DC 2 and return.

In some embodiments, controller 604 samples the power signal by converting the waveform using an analog-to-digital converter; the analog-to-digital converter may be incorporated into the controller 604 itself; for example, the controller 604 may be configured to convert an input from a pin (e.g., the pin labeled "5" in the controller in fig. 7C) to a number using an analog-to-digital conversion protocol. The controller 604 is configured to switch the first switching mechanism 603 to a first state when the voltage falls below a first threshold voltage, and to switch the first switching mechanism 603 to a second state when the voltage exceeds the first threshold voltage. The controller 604 may be configured to detect when the voltage level represented by the converted waveform falls below a first voltage threshold and activate the first switching device 603 to switch to a first state; this may be accomplished by sending a voltage signal to the first transistor 703, the second transistor 705, or the control transistor 704 as described above with reference to fig. 7A. Likewise, the controller 604 may be configured to determine that the converted waveform has exceeded the first threshold voltage and switch the first switching device 603 to the second state; this may be accomplished, for example, by setting the voltage at the gates of the first transistor 703, the second transistor 705, or the control transistor 704 such that the first transistor 703 and the second transistor 705 are turned off, as described above.

In some embodiments, when a waveform, such as a rectified AC waveform, supplies power to the first and second light blocks 601, 602, the controller 604 samples the waveform. In such embodiments, when the waveform is at its minimum, the first lamp block 601 is in parallel with the second lamp block 602, and thus has a lower total forward operating voltage than it would have if in series; therefore, the first and second lamp blocks emit light while the waveform voltage is still low. In such embodiments, as the waveform rises, the voltage supplied to the first and second light blocks increases, reaching a first threshold; the controller 604, detecting that a threshold is reached, uses a first switching mechanism 603 to place the first light block 601 in series with the second light block 602. If the threshold voltage is properly selected, a series arrangement will occur when the waveform voltage is high enough to cause light emission at the higher forward operating voltage of the series configuration. When the waveform drops from its peak again, the controller 604 may sense that the waveform passes below the first threshold and switch the first and second light blocks 601, 602 back into parallel so that they continue to emit light as the voltage decreases.

Referring again to fig. 6, in some embodiments the circuit 600 includes a third light block 605. The third light block 605 may be any light block suitable for use as the first light block 601 or the second light block 602. The end of the third lamp block 605 into which positive current enters may be referred to as the "positive end". The end of the third light block 605 from which positive current flows may be referred to as the "negative end". The circuit 600 may also include a second switching mechanism 606. Second switching mechanism 606 may be capable of switching between a first state in which second switching mechanism 606 electrically connects second light block 602 and third light block 605 in parallel and a second state in which second switching mechanism 606 electrically connects second light block 602 and third light block 605 in series.

Referring now to fig. 7B, in some embodiments, the second switching mechanism 606 includes at least one transistor. For example, the second switching mechanism 606 can include a third transistor 708 that is turned on to connect the positive terminal of the third light block 605 to the positive terminal of the second light block 602, as described above. The third transistor 708 may be any transistor suitable for transmitting a power signal from one portion of the circuit to another. For example, the third transistor 708 may be a MOSFET, such as a power MOSFET. The third transistor 708 may be a p-channel MOSFET or an n-channel MOSFET. In some embodiments, the third transistor 708 receives the gate voltage directly from the output from the controller 604. In other embodiments, third transistor 708 receives its gate voltage from control transistor 709, which in turn is controlled by a signal from controller 604. As a non-limiting example, the controller 604 may send a signal to turn on the control transistor 709, which may be any suitable transistor. The current through the control transistor 709 may be used to set the voltage at the gate of the third transistor 708 to turn on the third transistor 708; for example, where the third transistor 708 is a p-channel MOSFET, the control transistor 709 may provide a return path that drops the voltage at the gate of the third transistor 708 to turn on the third transistor 708 so that the third transistor 708 turns on and connects the positive terminal of the second light block 602, which is denoted by the numeral 2 in the figure, to the positive terminal of the third light block 605, which is denoted by the numeral 4 in the figure.

The second switching mechanism 606 can include a fourth transistor 710 that connects the negative terminal of the second light block 602 to the negative terminal of the third light block 605 when the second switching mechanism 606 is in the first state. The fourth transistor 710 may be any transistor suitable for transmitting a power signal from one part of the circuit to another. For example, the fourth transistor 710 may be a MOSFET, such as a power MOSFET. The fourth transistor 710 may be a p-channel MOSFET or an n-channel MOSFET. In some embodiments, the fourth transistor 710 receives the gate voltage directly from the output from the controller 604. In other embodiments, the fourth transistor 710 receives its gate voltage from the control transistor 709, which in turn is controlled by a signal from the controller 604. As a non-limiting example, the controller 604 may send a signal to turn on the control transistor 709, which may be any suitable transistor. The current through the control transistor 709 may be used to set the voltage at the gate of the fourth transistor 710 to turn on the fourth transistor 710; for example, where the fourth transistor 710 is a p-channel MOSFET, the control transistor 709 may provide a return path that drops the voltage at the gate of the fourth transistor 710 to turn on the fourth transistor 710, such that the fourth transistor 710 is on and connects the negative terminal of the second light block 602 to the negative terminal of the third light block 605 (which in some embodiments is the same as the negative terminal of the light circuit (labeled "negative" herein)). In some embodiments, as illustrated in fig. 7B, a single control transistor 709 controls both the third transistor 708 and the fourth transistor 710; alternatively, each of the third transistor 708 and the fourth transistor 710 may have its own control transistor.

In some embodiments, the second light block 602 is connected to the third light block 605 by one or more diodes 711 that permit current to flow between the second and third light blocks when the second switching mechanism 606 is in one of the first and second states, but do not permit current to flow between the second and third light blocks when the second switching mechanism 606 is in the other of the first and second states. The one or more diodes 711 may be positioned such that the one or more diodes are forward biased and conductive when the second light block 602 is in series with the third light block 605, and are reverse biased and therefore non-conductive when the second light block 602 is in parallel with the third light block 605. For example, in the embodiment illustrated in fig. 7B, the negative end of the second light block 602 is connected to the positive end of the third light block 605 through a diode 711, which is forward biased in the same direction as the LEDs depicted in the second and third light blocks, such that when no other connection is made between the second light block 602 and the third light block 605, the diode 711 is forward biased and current flows from the second light block 602 through the third light block 605; continuing the example, if in fig. 7A the positive terminal labeled "2" of the second light block 602 is connected to the positive terminal labeled "4" of the third light block 605 and the negative terminal labeled "negative" of the third light block 605 is connected to the negative terminal labeled "3" of the second light block 602, then the potential difference between the second light block 602 and the third light block 605 is no longer sufficient to forward bias the diode 711, which will not conduct.

In some embodiments, the second switching mechanism 606 enters the second state by disconnecting the connection between the positive terminal of the third light block 605 and the positive terminal of the second light block 602, as described above. In the case where there is a diode 711 connecting the two blocks, the diode 711 may then be forward biased, permitting a series connection. In other embodiments, the second switching mechanism 606 includes one or more transistors (not shown) connecting the third light block 605 in series with the second light block 602; for example, a transistor may connect the negative terminal of the second light block 602 to the positive terminal of the third light block 605.

In some embodiments, the controller 604 is further configured to detect that the voltage of the power signal is below a second threshold and switch the second switching mechanism 606 to the first state. In some embodiments, the controller 604 is also configured to detect that the power signal is above a second threshold and switch the second switching mechanism 606 to a second state. The threshold detection may be performed in the same manner as detecting the first threshold as described above.

In some embodiments, the controller 604 is further configured to switch the second switching mechanism 606 to the first state when the voltage waveform falls below the first threshold. For example, the controller may be configured to keep the third and second light blocks 605, 602 in series with each other but in parallel with the first light block 601 when the waveform is below a first threshold, and switch the second switching mechanism 606 to place the second and third light blocks 602, 605 in parallel while switching the first switching mechanism 603 to place the second and third light blocks 602, 605 in parallel with each other when the waveform is above the first threshold; thus, the second light block 602 and the third light block 605 may each be in series with the first light block 601. The controller 604 may be further configured to switch the second switch 606 to a second position when the power signal voltage exceeds a second threshold (which may be higher than the first threshold) such that at the peak of the waveform, the first light block 601, the second light block 602, and the third light block 605 are all connected in series.

Continuing with the above example, the forward operating voltages of the first, second, and third light blocks 601, 602, 605 may be selected such that the three series and parallel combinations described above result in the desired fraction values of the forward operating voltages of the three blocks in series. For example, if each of the second and third light blocks 602 and 605 has half the forward operating voltage of the first light block 601, then in the above example, the light circuit would have twice the forward operating voltage of the first light block 601 when the signal voltage is above the second threshold and all three blocks are in series; thus, below the first threshold, when the second and third blocks in series are connected in parallel with the first electrical block 601, the lamp circuit forward operating voltage may be at 50% of the forward operating voltage of the full series configuration, or equal to the forward operating voltage of the first electrical block 601. Continuing the example, above the first threshold but below the second threshold, when the first lamp block 601 is connected in series with the parallel combination of the second lamp block 602 and the third lamp block 605, the forward operating voltage of the lamp circuit will be 75% of the forward operating voltage of the full series configuration, or 1.5 times the forward operating voltage of the first lamp block 601.

Returning again to fig. 6, the circuit 600 may include a current regulator 607. The current regulator 607 may be used to limit the current supplied to the lamp circuit by the power signal. The current regulator 607 may be any suitable current regulator, including a current sink. In some embodiments, the current regulator 607 is an embodiment of the current regulator 105 described above with reference to fig. 1A-1D. The controller 604 may be configured to adjust the current regulator 607 so as to increase or decrease the current supplied to the lamp circuit in response to changes in the voltage waveform of the power signal. In some embodiments, the controller 604 changes the current level permitted by the current regulator 607 upon detecting that the voltage waveform of the power signal has exceeded or fallen below at least one threshold. The at least one threshold may comprise a first threshold. The at least one threshold may include a second threshold. The at least one threshold may include one or more thresholds above, below, or between the first and second thresholds. For example, the controller 604 may have a first current change threshold between zero volts and a first threshold, a second current change threshold at the first threshold, a third current change threshold between the first threshold and the second threshold, a fourth current change threshold at the second threshold, and a fifth current change threshold between the second current change threshold and the peak of the power signal voltage waveform.

In some embodiments, the controller 604 causes the current regulator 607 to change the current level based on the voltage waveform crossing one or more current thresholds. From the perspective of controller 604, the current regulator may have a default setting; that is, in the absence of a command from the controller 604, the current regulator 607 may be set to allow a certain amount of current. The default setting of the current regulator 607 may be the default setting to which the current regulator returns when no input is received. The default setting of the current regulator 607 may be the current level to which the current regulator is set by another device; for example, the default setting of the current regulator 607 may be manually set by a switch (e.g., the resistive divider switch 108). The default setting of the current regulator 607 may be set using the control signal, as described above in connection with fig. 1A-1C for the current regulator 105. Thus, for example, a user may set the dimmer control signal input 314 using a manual dimmer switch or a remote device, causing the control signal to the current regulator 607 to establish a default current setting.

In some embodiments, the controller 604 modifies the current level permitted by the current regulator 607 by setting the current level to a percentage of a default setting in response to the waveform crossing one or more thresholds. In some embodiments, the default setting is the maximum level to which the controller 604 can set the current regulator 607, and the percentage to which the controller 604 sets the current regulator 607 is 100% or less. For example, when the waveform is below a first current change threshold, for example, because the controller 604 detects that the waveform has fallen below the first current change threshold, the controller 604 may set the current regulator 607 to a default set first percentage, which may be a relatively low percentage; for illustrative purposes, the low percentage may be 20%. Continuing the example, when the waveform exceeds the first current change threshold, the controller 604 may set the current regulator 607 to a second percentage of the default setting, which may be greater than the first percentage; as a non-limiting example, the higher percentage may be 30% of the default setting. Continuing the example further, when the voltage waveform of the power signal exceeds the second current change threshold, which may be the first threshold described above, the controller 604 may set the current regulator 607 to a third percentage of the default setting; the third percentage may be greater than the second percentage. As a non-limiting example, the third percentage may be 45% of the default setting. Continuing the example still further, when the voltage waveform exceeds the third current change threshold, the controller 604 may set the current regulator 607 to a fourth percentage of the default setting; the fourth percentage may be greater than the third percentage. As a non-limiting example, the fourth percentage may be 54% of the default setting. Continuing the example, when the voltage waveform exceeds the fourth current change threshold, which may be the second threshold described above with respect to commands to the switching

mechanisms

603, 606, the controller 604 may set the current regulator 607 to a fifth percentage of the default setting; the fifth percentage may be greater than the fourth percentage. As a non-limiting example, the fifth percentage may be 83% of the default setting. Continuing the example further, when the voltage waveform exceeds the fifth current change threshold, the controller 604 may set the current regulator 607 to a sixth percentage of the default setting; the sixth percentage may be 100% of a default setting.

The controller 604 may also modify the current level in response to the reduced power signal voltage waveform. The command to modify the current level in response to the falling waveform may supplement the command to modify the current level in response to the rising waveform. As a non-limiting example, the controller 604 may set the current regulator 607 to a fifth percentage when the voltage waveform falls below a fifth current change threshold. Continuing the example, when the voltage waveform falls below the fourth current change threshold, the controller 604 may set the current regulator 607 to a fourth percentage. Continuing the example further, when the voltage waveform falls below the third current change threshold, the controller 604 may set the current regulator 607 to a third percentage. Continuing the example still further, the controller 604 may set the current regulator 607 to a second percentage when the voltage waveform falls below a second current change threshold. Continuing the example again, the controller 604 may set the current regulator 607 to the first percentage when the voltage waveform falls below the first current change threshold.

In some embodiments, where the current regulator 607 sets its current level according to the control signal (as described above with reference to fig. 1A-1C), the controller 604 modifies the current level of the current regulator 607 by modifying the control signal. For example, as illustrated in fig. 7C, the current regulator 607 may set the one or more transistors to a given resistance level based on a voltage difference between a feedback network at the inverting input terminal of the one or more operational amplifiers and a voltage proportional to the control signal voltage at the non-inverting input terminal of the one or more operational amplifiers, as described above with reference to fig. 1B-1C. Continuing the example, the controller 604 can modify the voltage level generated by the control signal to change the setting of the power transistor. For example, the default setting of the current regulator 607 may use the voltage across the default resistor 712 as the voltage at the positive terminal of the one or more operational amplifiers. The controller 604 may reduce the voltage across the default resistor 712 by placing the default resistor 712 in parallel with one or more signal modification resistors 713 a-713 c. For example, the controller 604 may modify the control terminal voltage of the first signal modifying transistor 714a to allow current to flow through the first current modifying resistor 713 a. The controller 604 may modify the control terminal voltage of the second signal modifying transistor 714b to allow current to flow through the second current modifying resistor 713 b. The controller 604 may modify the control terminal voltage of the third signal modifying transistor 714c to allow current to flow through the third current modifying resistor 713 c. Although three signal modifying resistors 713 a-713C are depicted in fig. 7C, in other embodiments, there may be more or fewer signal modifying resistors and signal modifying transistors 714 a-714C.

The controller 604 may place the default resistor 712 in parallel with any combination of one or more of the signal modification resistors 713 a-713 c to generate the desired control signals in order to set the current regulators to the desired percentages. As a non-limiting example, the controller 604 may place the first signal modifying resistor 713a in parallel with the default resistor 712 when the voltage waveform is below a first threshold and place the second signal modifying resistor 713b in parallel with the default resistor when the voltage waveform is above the first threshold and below a second threshold; continuing the example, controller 604 may use third signal modifying resistor 713c to set the current to be at an intermediate level between those established by default resistor 712, first signal modifying resistor 713a, and second signal modifying resistor 713b by placing third signal modifying resistor 713c in parallel with the combination of default resistor 712, first signal modifying resistor 713a, and second signal modifying resistor 713 b. As a further illustration of the example and with reference to the example above for setting the current at the percentage of the default current, the controller 604 may set the current regulator 607 at the first lowest percentage of the default current by placing the third signal modifying resistor 713c in parallel with the default resistor 712. Continuing the example further, the controller may set the current regulator 607 at a second percentage by placing the first signal modifying resistor 713a in parallel with the third signal modifying resistor 713c and the default resistor 712. Continuing the example still further, the controller 604 may set the current regulator 607 at a third percentage by removing the third signal modifying resistor 713c and leaving the first signal modifying resistor 713a in parallel with the default resistor 712. Continuing the example again, the controller 604 may set the current regulator 607 at a fourth percentage by placing the third signal modifying resistor 713c and the second signal modifying resistor 713b in parallel with the default resistor 712 (and removing the first signal modifying resistor 713a from the parallel combination). Continuing the example again, the controller 604 may set the current regulator 607 at a fifth percentage by removing the third signal modifying resistor 713c from the parallel combination to leave the second signal modifying resistor 713b in parallel with the default resistor 712. Continuing the example further, the controller 604 may set the current regulator 607 to a sixth percentage by removing the second signal modifying resistor 713b from the parallel combination to leave the default resistor 712 to adjust the current level without further modification.

In the event that the current change threshold is the same as the threshold for changing the voltage by reconfiguring the lamp circuit (as described above), the controller 604 may command both the change and reconfiguration of the current using the same wires. For example, a first control signal may be carried by first control signal conductor 715. A first control signal conductor 715 may be electrically connected to both the first switching mechanism 603 and the first signal modifying transistor 714 a. Likewise, a second control signal may be transmitted by the controller 604 on a second control signal conductor 716, which may be electrically connected to the second switching mechanism 606 and to the second signal-modifying transistor 714 b. In some embodiments, the connector 717 connects the current regulator 607 and the controller 604 to corresponding connectors 608 incorporated into the lamp circuit and the first and

second switching mechanisms

603 and 606. The

fittings

717, 608 may use any kind of connector incorporating them, including ribbon cables, compact connectors, or soldered connections. In some embodiments, the junction 608 of the lamp circuit and switching mechanism has

multiple terminals

608a, 608b, such that multiple such circuits may be connected in parallel or in series; in some embodiments, the current or voltage supplied by the current regulator 607 is adjusted to account for the larger current or voltage required by the daisy-chained lighting circuit.

Those skilled in the art will recognize that further combinations of signal modifying resistors 713 a-713 c and default resistor 712 may be used to set different current levels by modifying the programming of controller 604; likewise, one or more of the above-described resistor combinations may be omitted to omit one or more of the above-described percentages without departing from the concepts described herein. In other embodiments, one or more of the signal modification resistors 713 a-713 c may include circuit elements having variable resistance. For example, one or more of the signal modifying transistors 714 a-714 c may be partially turned on by the controller 604, forming a variable resistance that is modified by the controller 604; the controller 604 may use a digital-to-analog converter (not shown) or a capacitive averaging network, such as the PWM/DC converter 202 described above with reference to fig. 2A-2B, to convey the varying voltage to one or more signal modifying transistors 714 a-714 c. As a non-limiting example, the third signal modifying transistor 714c may be controlled to have a variable resistance, allowing for substantially continuous insertion of the current waveform output by the current regulator 607.

The embodiments of the auto-reconfiguration light emitting circuit described above can reduce total harmonic distortion by changing the forward voltage of the lamp circuit to approximate the voltage waveform of the ac power signal. The circuit may also modify the current to the lamp circuit to reduce total harmonic distortion; where current modification is performed by altering a control signal to a current regulator, the disclosed circuit may have a novel effect of permitting a user to control the overall intensity of emitted light by setting a current level while still modifying the current according to the waveform to reduce distortion.

Fig. 8 illustrates some embodiments of a method 800 for reconfiguring a network of light emitting diodes in response to a voltage signal. The method 800 includes sampling (801) a voltage level of a power signal by a controller connected to a first switching mechanism having a first state connecting a first light block in parallel with a second light block and a second state connecting the first light block in series with the second light block. The method 800 includes detecting, by a controller, that a voltage level has dropped below a first threshold (802). The method 800 includes switching, by the controller, the first switching mechanism to a first state (803). The method 800 includes detecting, by the controller, that the voltage level has risen above a first threshold (804). The method 800 includes switching, by the controller, the first switching mechanism to a second state (805).

Looking in more detail at figure 8 and with reference to figures 6-7C, the controller 604 samples the voltage level of the power signal (801). In some embodiments, this is implemented as described above with reference to fig. 6-7C.

The controller 604 detects that the voltage level has dropped below a first threshold (802). In some embodiments, this is implemented as described above with reference to fig. 6-7C.

The controller 604 switches the first switching mechanism 603 to the first state (803). In some embodiments, this is implemented as described above with reference to fig. 6-7C.

The controller 604 detects that the voltage level has risen above a first threshold (804). In some embodiments, this is implemented as described above with reference to fig. 6-7C.

The controller 604 switches the switching mechanism to a second state (805). In some embodiments, this is implemented as described above with reference to fig. 6-7C.

In some embodiments, as described above, the circuit includes a second switching mechanism 606 capable of switching between a first state in which the second switching mechanism 606 electrically connects the second light block 602 and the third light block 605 in parallel and a second state in which the second switching mechanism 606 electrically connects the second light block 602 and the third light block 605 in series; the controller 604 may detect that the voltage of the power signal is below a second threshold and switch the second switching mechanism 606 to the first state. In some embodiments, this is implemented as described above with reference to fig. 6-7C. In some embodiments, the controller 604 detects that the power signal is above a second threshold and switches the second switching mechanism 606 to a second state. This may be performed as described above with reference to fig. 6-7C.

In some embodiments, the controller 604 detects at least one current change threshold and, in response to the detection, causes the current regulator 607, which regulates the power signal, to change from a first current level to a second current level. This may be implemented as described above with reference to fig. 6-7C. The at least one current change threshold may include one or more of the first and second thresholds, as described above. The at least one current threshold may also include one or more intermediate thresholds, as described above.

Fig. 9 presents a block diagram of an embodiment of an automatic reconfiguration light emitting circuit 900. The circuit 900 includes a first lamp block 901. The circuit includes a second light block 902. The circuit includes a first switching mechanism 903. The first switching mechanism 903 has a first state in which the first switching mechanism electrically connects the first light block 901 in parallel with the second light block 902. The first switching mechanism 903 has a second state in which the first switching mechanism 903 electrically connects the first lamp block 901 in series with the second lamp block 902. The circuit 900 includes a current regulator 907 that generates a current control signal in response to currents in the first and second light blocks 901, 902. The circuit 900 includes a controller 904 electrically connected to the first switching mechanism 903, the controller 904 configured to switch the switching mechanism 903 between a first state and a second state based on a current control signal.

Looking in more detail at fig. 9, the circuit 900 includes a first light block 901. The first light block 901 can be any light block suitable for use as the first light block 601 described above in connection with fig. 6-7C. The second light block 602 may be any light block suitable for use as the second light block 602 described above in connection with fig. 6-7C. The switching mechanism 903 may be any switching mechanism suitable for use as the switching mechanism 603 described above in connection with fig. 6-7C.

Circuit 900 includes a current regulator 907. The current regulator 907 may be any of the current regulators described above with reference to fig. 1A-8; as a non-limiting example, the current regulator 907 may be a current sink. The current regulator 907 generates a current control signal. The current control signal may be a signal that regulates a component of the current regulator 907 through which current flows (e.g., a power transistor), as described in more detail below.

In some embodiments, as illustrated in fig. 10A, the current regulator 907 includes at least one power transistor 1001 through which current in the first and second lamp groups flows. The at least one power transistor 1001 may be any transistor suitable for use as the at least one transistor 117 described above with reference to fig. 1A. For example and without limitation, the at least one power transistor 1001 may include a MOSFET; power transistor 1001 includes a power MOSFET designed to regulate current at high amperage. At least one power transistor 1001 may have a control terminal 1002 as defined above in connection with fig. 1A-1B. In some embodiments, the current control signal is a signal at the control terminal 1002 of the at least one power transistor 1001. In some embodiments, the current control signal causes the at least one power transistor 1001 to increase or decrease the effective resistance of the at least one power transistor 1001 to increase or decrease the amount of current flowing through the first and second light blocks 901, 902.

The current regulator 907 may include at least one regulator transistor 1003. The at least one regulator transistor 1003 may be any transistor suitable for use as the transistor 117 described above with reference to fig. 1A-1B. For example and without limitation, the at least one regulator transistor 1003 may include a bipolar junction transistor, a field effect transistor, or a MOSFET. At least one regulator transistor 1003 may have an output terminal 1004. The output terminal 1004 may be a terminal through which current flows when the at least one regulator transistor 1003 is turned "on"; as non-limiting examples, the output terminal 1004 may be a source or drain terminal if the at least one regulator transistor 1003 is a MOSFET, or a collector or emitter terminal if the at least one regulator transistor 1003 is a bipolar junction transistor. In some embodiments, the current control signal is a signal generated at the output port 1004 of the at least one regulator transistor 1003. The at least one regulator transistor 1003 may be combined with one or more additional circuit elements to form a current regulator 907. For example, as shown in fig. 10B, in some embodiments, the at least one current regulator includes at least one operational amplifier 111 a-111B. The at least one operational amplifier 111 a-111 b may incorporate at least one regulator transistor, for example, because one or more of the transistors constitute the circuitry of the operational amplifier.

As illustrated in fig. 10A-10B, the current regulator 907 may include a negative feedback network 1005 that supplies negative feedback to the current regulator 907 based on the current. The negative feedback network 1005 may include one or more resistors. In some embodiments, the negative feedback network 1005 causes the current regulator 907 to be used to decrease current when current increases, and to increase current when current decreases. For example, where the current regulator 907 includes operational amplifiers 111 a-111B (as shown in fig. 10B), the increase in current through the negative feedback network 1005 causes the voltage at the inverting terminals of the operational amplifiers 111 a-111B to increase, which reduces the voltage difference between the inverting and non-inverting terminals of the operational amplifiers 111 a-111B, causing the voltage output at the output terminals of the operational amplifiers 111 a-111B to decrease, reducing the gate voltage of the power transistor 1001 and increasing the effective resistance of the power transistor 1001. This may function as described above in connection with fig. 1A-8 with respect to the current regulator.

The controller 904 may be any device suitable for use as the controller 604 described above with reference to fig. 6-7C. One or more wires or circuit elements may convey the current control signal to controller 904. The one or more wires or circuit elements may include a resistor or resistive voltage divider (not shown) that reduces the voltage of the current control signal such that the voltage of the current control signal is within a voltage range of the input to the controller 904. One or more wires or circuit elements may include a zener diode 1006 or similar device that reduces the voltage input to the controller 904 to a particular range; for example, the zener diode 1006 may drop the voltage output to the controller 904 to a value that the controller 904 interprets as being between a digital 1 and a digital 0. Alternatively, a comparator (not shown) may convert the voltage output to a digital 1 or digital 0 value based on a reference voltage. The connection from the current regulator 907 to the controller 904 may also include a voltage clamping element, such as a schottky diode as described above with reference to fig. 6-7C.

Referring again to fig. 9, in some embodiments, the circuit 900 includes a third light block 905. The third light block 905 may be any light block suitable for use as the first light block 901 or the second light block 902. The third light block 905 may be connected to the second light block 902 and the first light block 901. The circuit 900 may also include a second switching mechanism 906. The second switching mechanism 906 can be capable of switching between a first state in which the second switching mechanism 906 electrically connects the second light block 902 and the third light block 905 in parallel and a second state in which the second switching mechanism 906 electrically connects the second light block 902 and the third light block 905 in series. The second switching mechanism 906 may be any switching mechanism suitable for use as the second switching mechanism 606 described above.

The controller 904 may be connected to one or more signal modifying transistors 714 a-714C that permit current to flow through one or more signal modifying resistors 713 a-713C as described above with reference to fig. 6-7C to modify the control signal delivered to the current regulator 907.

In some embodiments, sampling the current control signal within the current regulator 907 enables the controller 904 to determine the state of the power waveform more accurately than conventional methods of sampling one or more parameters of the waveform itself to determine its state; this is because a high noise environment can cause the sampling of the voltage or current in the power waveform to be inaccurate. In conventional approaches, inaccurate readings may result in improper configuration of LEDs and associated current levels, which results in inconsistent brightness levels and unacceptable levels of THD in the current waveform. In contrast, configuring the LEDs and associated current levels based solely on timing considerations triggered by the start of LED conduction (as determined from the current control signal) after the zero crossing of the power signal results in stable, repeatable and superior operation in a high noise environment.

Fig. 11A illustrates some embodiments of a method 1100 for reconfiguring a network of light emitting diodes in response to a voltage signal. The method 1100 includes receiving, by a controller connected to a switching mechanism having a first state connecting a first light block in parallel with a second light block and a second state connecting the first light block in series, a current control signal generated by a current regulator in response to current in the first and second light groups (1101). The method 1100 includes switching, by a controller, a switching mechanism between a first state and a second state based on a current control signal (1102).

Looking in more detail at fig. 11 and with reference to fig. 9-10B, the controller 904 receives a current control signal generated by a current regulator 907 in response to currents in the first and

second lamp groups

901, 902. The controller 904 may sample the current control signal to obtain a representation of the current control signal waveform. In some embodiments, the controller 904 samples the current control signal using an analog-to-digital converter, as described above with reference to fig. 6-7C.

In other embodiments, where the current has a substantially periodic waveform with a zero voltage point, the controller 904 detects when the waveform reaches a point near the zero voltage point of the waveform based on the received current control signal; the substantially periodic waveform may be a rectified ac waveform. In the case where the current control signal is generated by the current regulator based on current based on negative feedback, the controller 904 may detect a point close to the zero voltage point of the waveform by detecting that the current control signal has reached a maximum level. For example, as illustrated in fig. 11B, where the current regulator 907 includes an operational amplifier that reads the current through a negative feedback network, the first and second light blocks 901, 902 may stop conducting if the rectified voltage AC waveform 1103 passes below a certain level 1103a, since the waveform has dropped below the forward operating voltage, so the current drops to zero; thus, the operational amplifier output 1104 may suddenly increase to the positive rail voltage of the amplifier 1104 b. As illustrated, the positive rail voltage of the amplifier may be several times the voltage that the current control signal 1104 has when current is flowing.

In some embodiments, the controller 904 detects that the current control signal 1104 has reached the maximum level by detecting that the voltage based on the current control signal 1104 is a digital 1 voltage. In some embodiments, where the controller receives the control signal 1104 through the zener diode 1006, the breakdown voltage of the zener diode shifts the control signal 1104 to a range from a digital 1 to a digital 0; in that case, the controller 904 may receive a digital 1 signal from the control signal 1104 when current is not flowing and a lower voltage corresponding to a digital 0 signal when current begins to flow. The controller 904 may also detect that the current control signal has dropped from a maximum level; the controller 904 may accomplish this by detecting that the voltage based on the current control signal is a digital 0 voltage.

The controller 904 switches the switching mechanism 903 between a first state and a second state based on the current control signal. In some embodiments, the controller 904 maintains a time interval in the memory of the controller 904 for a time from a detected transition between a digital 1 and a digital 0 to when the AC waveform may have a voltage that exceeds one or more of the thresholds described above with reference to fig. 6-8. The controller 904 may use a clock or similar timing device to determine when each of the thresholds has been crossed in the positive and negative directions and cause the switching mechanism 903 to switch between the first state and the second state; the switching may be implemented as described above with reference to fig. 6-8. Where the circuit 900 includes the second switching mechanism 906 and the third light block 905, the controller 904 may likewise switch the second switching mechanism 906 between its first and second states, as described above with reference to fig. 6-8.

In some embodiments, the controller 904 modifies the current level permitted by the current regulator 907 by setting the current level to a percentage of a default setting in response to the waveform crossing one or more thresholds (as determined by the time elapsed since a given transition in the detected current control signal). The controller 904 may set the current level upon the waveform crossing a threshold, as described above with reference to fig. 6-8. Fig. 11C shows an exemplary stepped current waveform 1105 and an exemplary corresponding voltage waveform 1103 regulated by the controller 904 and the current regulator 907.

In some embodiments, controller 904 determines the frequency of the AC waveform that supplies power to circuit 900 by measuring the time between possible transitions in current control signal 1104. For example, in some embodiments, the controller 904 detects that the control signal 1104 has reached a maximum level a first time, detects that the current control signal 1104 has fallen from a maximum level, detects that the current control signal 1104 has reached a maximum level a second time, and measures the time elapsed between the first and second times. The controller 904 may match the elapsed time with the number of description periods; for example, where the elapsed time corresponds to the wavelength of a 60 hertz full wave rectified signal, the controller 904 may match the elapsed time to a stored value representing the 60 hertz full wave rectified signal. The controller 904 may then use the stored ideal 60 hertz full wave rectified wave to determine when the AC power signal has exceeded or fallen below a threshold, set a current level, and change the state of the switching

mechanisms

903, 906 as described above with reference to fig. 6-7C.

It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. The present examples and embodiments, therefore, are to be considered in all respects as illustrative and not restrictive, and the invention is not to be limited to the details given herein.

Claims

1. An automatically re-configurable lighting circuit, the circuit comprising:

a first electric lamp block;

a second electric lamp block;

a switching mechanism having (i) a first state in which the switching mechanism electrically connects the first light block in parallel with the second light block and (ii) a second state in which the switching mechanism electrically connects the first light block in series with the second light block;

a current regulator that generates a current control signal in response to currents in the first and second lamp groups; and

a controller electrically connected to the switching mechanism, the controller configured to switch the switching mechanism between the first state and the second state based on the current control signal;

wherein the current regulator comprises at least one power transistor through which the current in the first and second lamp groups flows, the at least one power transistor having a control terminal; and is

The current control signal is a signal at the control terminal of the at least one power transistor.

2. The circuit of claim 1, wherein:

the current regulator further comprises at least one regulator transistor having an output terminal; and is

The current control signal is a signal generated at the output terminal of the at least one regulator transistor.

3. The circuit of claim 2, wherein the at least one current regulator further comprises at least one operational amplifier incorporating the at least one regulator transistor.

4. The circuit of claim 1, further comprising a negative feedback network that supplies negative feedback to the current regulator based on the current.

5. The circuit of claim 1, wherein the current regulator is a current sink.

6. The circuit of claim 5, further comprising a control signal sealer.

7. A method for automatically reconfiguring a lighting circuit, the method comprising:

receiving, by a controller connected to a switching mechanism, a current control signal generated by a current regulator in response to currents in a first lamp group and a second lamp group, the switching mechanism having a first state connecting a first lamp block in parallel with a second lamp block and a second state connecting the first lamp block in series with the second lamp block; and

switching, by the controller, the switching mechanism between the first state and the second state based on the current control signal;

wherein the current has a substantially periodic waveform with a zero voltage point, and the method further comprises detecting, by the controller, a zero voltage point of the waveform based on the received current control signal.

8. The method of claim 7, wherein the substantially periodic waveform is a rectified alternating current waveform.

9. The method of claim 7, wherein the current control signal is generated by the current regulator based on negative feedback based on the current, and wherein detecting the zero voltage point of the waveform further comprises detecting that the current control signal has reached a maximum level.

10. The method of claim 9, wherein detecting that the current control signal has reached a maximum level further comprises detecting that a voltage based on the current control signal is a digital 1 voltage.

11. The method of claim 9, further comprising detecting that the current control signal has dropped from the maximum level.

12. The method of claim 11, wherein detecting that the current control signal has dropped from the maximum level further comprises detecting that a voltage based on the current control signal is a digital 0 voltage.