CN109800511B - Correction method and system for maintaining time violation for finding optimal common point - Google Patents
Correction method and system for maintaining time violation for finding optimal common point Download PDFInfo
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- CN109800511B CN109800511B CN201910063867.4A CN201910063867A CN109800511B CN 109800511 B CN109800511 B CN 109800511B CN 201910063867 A CN201910063867 A CN 201910063867A CN 109800511 B CN109800511 B CN 109800511B
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Abstract
The invention discloses a retention time violation correction method and a retention time violation correction system for searching an optimal common point, wherein the implementation steps comprise: traversing all the violating paths with the hold time violations, finding out the logic units in the violating paths, and summarizing to obtain a logic unit set; searching a logic unit corresponding to the optimal common point in the logic unit set, and inserting a delay unit with unit delay equivalent to the margin of the established time sequence recorded by the logic unit; updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic units corresponding to the optimal common point; the above process is repeated until the number of repairable time violations for all logic cells in the set of logic cells is 0. The invention reduces the cost on area and power consumption by searching the optimal common point of the hold time violation path and inserting a proper delay unit into the optimal common point to repair the hold time violation method.
Description
Technical Field
The invention relates to the field of digital integrated circuit design, in particular to a retention time violation correction method and a retention time violation correction system for finding an optimal common point, which are used for retention time violation repair in a digital integrated circuit design flow.
Background
In the current integrated circuit, a large number of synchronous digital circuits are used, and a large number of sequential logic units such as registers in the synchronous digital circuits are controlled by a uniform clock signal and work synchronously according to the beat of the clock signal. However, in the circuit implementation process, the transmission delay of the clock signal reaching each register cannot be completely consistent. When the clock delay of the start register of a timing path is less than the clock delay of the end register, and the transmission delay of the data signal on the timing path is less than the difference between the clock delays of the start and end, the hold time (hold) violation occurs in the circuit, and the circuit function is wrong.
In order to avoid the hold time violation, it is a common practice in the industry to trace back each logic unit on the data path from the end register of the timing path, and insert a certain amount of delay units (delay buffers) according to the setup time margin of the timing path where the logic unit is located to artificially increase the transmission delay of the data signal. However, inserting delay cells into a circuit incurs overhead on circuit area and power consumption, and especially for circuits with a large number of hold time violation paths, inserting delay cells into each violation path generally results in a large increase in area and power consumption, and even results in a circuit with too high local density to insert enough delay cells into the circuit without space to repair the hold time violation.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: in view of the above problems in the prior art, the present invention provides a retention time violation correction method and system for finding an optimal common point, and the present invention repairs the retention time violation by finding an optimal common point of a retention time violation path and inserting an appropriate delay unit into the optimal common point, thereby reducing overhead on area and power consumption.
In order to solve the technical problems, the invention adopts the technical scheme that:
a hold time violation correction method for searching an optimal common point includes the following implementation steps:
1) Traversing all the violating paths with the hold time violations, and finding out all the logic units in the violating paths;
2) Summarizing all logic units violating the paths to obtain a logic unit set;
3) Searching a logic unit corresponding to the optimal common point in the logic unit set;
4) Inserting a delay unit with unit delay equivalent to the margin of the establishing time sequence recorded by the logic unit into the output end of the logic unit corresponding to the found optimal common point;
5) Updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic units corresponding to the optimal common point;
6) Judging whether the repairable retention time violation number of all the logic units in the logic unit set is 0, and if not, skipping to execute the step 1); otherwise, end and exit.
Preferably, the detailed steps of step 3) include:
3.1 Obtaining the number of repairable time violations of each logic unit in the logic unit set;
3.2 The logical unit corresponding to the optimal common point is determined according to the number of the modifiable violating paths of the logical unit.
Preferably, the detailed steps of step 3.1) include: and analyzing and counting the hold time violation values and the set-up time timing margins of all timing paths passing through the logic unit aiming at each logic unit in the logic unit set, and then finding out the number of the violation paths of which the absolute values of the hold time violation values are smaller than the set-up time timing margins as the number of the repairable violation paths of the logic unit.
Preferably, the detailed steps of step 3.2) include: judging whether a single logic unit with the maximum number of the repairable violating paths exists or not, and if so, taking the logic unit as a logic unit corresponding to the optimal common point; otherwise, selecting the logic unit with the maximum sum of the absolute values of the violation values of the modifiable violation path as the logic unit corresponding to the optimal common point.
The present invention also provides a hold time violation correction system for finding optimal common points, comprising a computer device programmed to perform the steps of the hold time violation correction method for finding optimal common points of the present invention as described above.
The present invention also provides a retention time violation correction system for finding an optimal common point, comprising a computer device having a storage medium having stored therein a computer program programmed to execute the aforementioned retention time violation correction method for finding an optimal common point of the present invention.
The present invention also provides a computer readable storage medium having stored therein a computer program programmed to execute the aforementioned retention time violation correction method of finding an optimal common point of the present invention.
The present invention also provides a hold time violation correction system for finding an optimal common point, comprising:
the logic unit traversal program unit is used for traversing all the violation paths with the retention time violation and finding out all the logic units in the violation paths;
the logic unit summarizing program unit is used for summarizing all the logic units violating the path to obtain a logic unit set;
the optimal common point searching program unit is used for searching the logic units corresponding to the optimal common points in the logic unit set;
a delay unit insertion program unit, which is used for inserting a delay unit with unit delay equivalent to the margin of the set-up time sequence recorded by the logic unit at the output end of the logic unit corresponding to the found optimal common point;
a time updating program unit for updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic unit corresponding to the optimal common point;
the loop judgment program unit is used for judging whether the repairable retention time violation number of all the logic units in the logic unit set is 0, and if not, skipping to execute the logic units and traversing the program units; otherwise, end and exit.
Preferably, the searching for the logic unit corresponding to the optimal common point by the optimal common point searching program unit specifically includes: and acquiring the number of repairable retention time violations of each logic unit in the logic unit set, and searching the logic unit with the maximum value of the number of repairable retention time violations as the logic unit corresponding to the found optimal common point.
Compared with the prior art, the invention has the following advantages: in a circuit, a plurality of timing paths with hold time violations usually pass through the same logic units, that is, the violating timing paths have a common point, and a plurality of hold time violating paths can be repaired simultaneously by inserting delay units into the common point units. Based on the discovery, the invention reduces the overhead of area and power consumption by a method of searching the optimal common point of the hold time violation path and inserting a proper delay unit into the optimal common point to repair the hold time violation.
Drawings
FIG. 1 is a schematic flow chart of a method according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the implementation steps of the retention time violation correction method for finding the optimal common point in this embodiment include:
1) Traversing all the violation paths with hold time (hold) violation, and finding out all logic units in the violation paths;
2) Summarizing all logic units violating the paths to obtain a logic unit set;
3) Searching a logic unit corresponding to the optimal common point in the logic unit set;
4) Inserting a delay unit with unit delay equivalent to the margin of the set-up time sequence recorded by the logic unit into the output end of the logic unit corresponding to the found optimal common point;
5) Updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic units corresponding to the optimal common point;
6) Judging whether the number of repairable retention time violations of all logic units in the logic unit set is 0, and if not, skipping to execute the step 1); otherwise, end and exit.
In this embodiment, the detailed steps of step 3) include:
3.1 Obtaining a number of repairable hold time violations for each logical unit in the set of logical units;
3.2 The logical unit corresponding to the optimal common point is determined according to the number of the modifiable violating paths of the logical unit.
In this embodiment, the detailed steps of step 3.1) include: and analyzing and counting the hold time violation values and the set-up time timing margins of all timing paths passing through the logic unit aiming at each logic unit in the logic unit set, and then finding out the number of the violation paths of which the absolute values of the hold time violation values are smaller than the set-up time timing margins as the number of the repairable violation paths of the logic unit.
In this embodiment, the detailed steps of step 3.2) include: judging whether a single logic unit with the maximum number of the repairable violating paths exists or not, and if so, taking the logic unit as a logic unit corresponding to the optimal common point; otherwise, selecting the logic unit with the maximum sum of the absolute values of the violation values of the modifiable violation path as the logic unit corresponding to the optimal common point.
In summary, the retention time violation correcting method for finding the optimal common point in this embodiment first traverses all the timing paths having the retention time violation, finds all the logic units in the timing paths, and analyzes and counts, for each logic unit, the retention time violation values, the setup time timing margins, and the number of violation paths (i.e., the number of the correctable violation paths) whose retention time violation values (absolute values) are smaller than the setup time timing margins of all the timing paths passing through the unit. Finding out the logic unit with the most number of the repairable violating paths, selecting the logic unit with the largest sum of the absolute values of the violating values of the repairable violating paths for the condition that a plurality of logic units have the same number of the repairable violating paths, inserting a delay unit with the same value as the established time sequence allowance at the output end of the logic unit, updating the time sequence information of the relevant time sequence paths after the insertion is completed, and repeating the method until all the time violation paths are maintained to be repaired.
The embodiment also provides a retention time violation correction system for finding the optimal common point, which comprises a computer device programmed to execute the steps of the retention time violation correction method for finding the optimal common point according to the embodiment.
The present embodiment further provides a retention time violation correcting system for finding an optimal common point, which includes a computer device, wherein a storage medium of the computer device stores therein a computer program programmed to execute the aforementioned retention time violation correcting method for finding an optimal common point of the present embodiment.
The present embodiment also provides a computer-readable storage medium having stored therein a computer program programmed to execute the aforementioned retention time violation correcting method of finding an optimal common point of the present embodiment.
The present embodiment further provides a retention time violation correction system for finding an optimal common point, including:
the logic unit traversal program unit is used for traversing all the violation paths with the retention time violation and finding out all the logic units in the violation paths;
the logic unit summarizing program unit is used for summarizing all logic units violating the path to obtain a logic unit set;
the optimal common point searching program unit is used for searching the logic units corresponding to the optimal common points in the logic unit set;
the delay unit insertion program unit is used for inserting a delay unit with unit delay equivalent to the margin of the set-up time sequence recorded by the logic unit at the output end of the logic unit corresponding to the found optimal common point;
a time updating program unit for updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic unit corresponding to the optimal common point;
the loop judgment program unit is used for judging whether the repairable retention time violation number of all the logic units in the logic unit set is 0, and if not, skipping to execute the logic units and traversing the program units; otherwise, end and exit.
In this embodiment, the finding of the logic unit corresponding to the optimal common point by the optimal common point finding program unit specifically includes: and acquiring the number of repairable time violations of each logic unit in the logic unit set, and searching the logic unit with the largest value of the number of repairable time violations as the found logic unit corresponding to the optimal public point.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (9)
1. A hold time violation correction method for finding an optimal common point is characterized by comprising the following implementation steps:
1) Traversing all violation paths with retention time violation, and finding out all logic units in the violation paths;
2) Summarizing all logic units violating the paths to obtain a logic unit set;
3) Searching a logic unit corresponding to the optimal common point in the logic unit set;
4) Inserting a delay unit with unit delay equivalent to the margin of the establishing time sequence recorded by the logic unit into the output end of the logic unit corresponding to the found optimal common point;
5) Updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic units corresponding to the optimal common point;
6) Judging whether the number of repairable retention time violations of all logic units in the logic unit set is 0, and if not, skipping to execute the step 1); otherwise, end and exit.
2. The hold time violation correcting method for finding optimal common points according to claim 1, wherein the detailed step of step 3) comprises:
3.1 Obtaining the number of repairable time violations of each logic unit in the logic unit set;
3.2 The logical unit corresponding to the optimal common point is determined according to the number of the modifiable violating paths of the logical unit.
3. The hold time violation correction method for finding optimal common points according to claim 2, wherein the detailed step of step 3.1) comprises: and analyzing and counting the hold time violation values and the set-up time timing margins of all timing paths passing through the logic unit aiming at each logic unit in the logic unit set, and then finding out the number of the violation paths of which the absolute values of the hold time violation values are smaller than the set-up time timing margins as the number of the repairable violation paths of the logic unit.
4. The hold time violation correction method for finding optimal common points according to claim 2, wherein the detailed step of step 3.2) comprises: judging whether a single logic unit with the maximum number of the repairable violating paths exists or not, and if so, taking the logic unit as a logic unit corresponding to the optimal common point; otherwise, selecting the logic unit with the maximum sum of the absolute values of the violation values of the modifiable violation path as the logic unit corresponding to the optimal common point.
5. A hold time violation correction system for finding an optimal common point, comprising a computer device, characterized by: the computer device is programmed to perform the steps of the hold time violation correction method of finding an optimal common point according to any of claims 1-4.
6. A hold time violation correction system for finding an optimal common point, comprising a computer device, characterized by: the storage medium of the computer device stores therein a computer program programmed to execute the method for correcting hold time violation for finding an optimal common point according to any one of claims 1 to 4.
7. A computer-readable storage medium characterized by: the computer readable storage medium has stored therein a computer program programmed to execute the method for correcting hold time violation for finding an optimal common point according to any one of claims 1 to 4.
8. A hold time violation correction system that finds an optimal common point, comprising:
the logic unit traversal program unit is used for traversing all the violating paths with the violating holding time and finding out all the logic units in the violating paths;
the logic unit summarizing program unit is used for summarizing all the logic units violating the path to obtain a logic unit set;
the optimal common point searching program unit is used for searching the logic units corresponding to the optimal common points in the logic unit set;
the delay unit insertion program unit is used for inserting a delay unit with unit delay equivalent to the margin of the set-up time sequence recorded by the logic unit at the output end of the logic unit corresponding to the found optimal common point;
a time updating program unit for updating the hold time violation values and the set-up time sequence margin values of all the time sequence paths passing through the logic unit corresponding to the optimal common point;
the loop judgment program unit is used for judging whether the repairable retention time violation number of all the logic units in the logic unit set is 0, and if not, skipping to execute the logic units and traversing the program units; otherwise, end and exit.
9. The system for correcting violations of holding time for finding optimal common points according to claim 8, wherein the finding of the logical units corresponding to the optimal common points by the optimal common point finding program unit specifically means: and acquiring the number of repairable time violations of each logic unit in the logic unit set, and searching the logic unit with the largest value of the number of repairable time violations as the found logic unit corresponding to the optimal public point.
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| CN112597739B (en) * | 2020-12-30 | 2023-04-07 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2011164740A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Apparatus and method for circuit design |
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN105787213A (en) * | 2016-04-01 | 2016-07-20 | 中国人民解放军国防科学技术大学 | Repairing method of retention time violation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011164740A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Apparatus and method for circuit design |
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN105787213A (en) * | 2016-04-01 | 2016-07-20 | 中国人民解放军国防科学技术大学 | Repairing method of retention time violation |
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