CN109787709B - Passive optical network, and encoding and decoding determining method and device - Google Patents

Passive optical network, and encoding and decoding determining method and device Download PDF

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Publication number
CN109787709B
CN109787709B CN201711122047.5A CN201711122047A CN109787709B CN 109787709 B CN109787709 B CN 109787709B CN 201711122047 A CN201711122047 A CN 201711122047A CN 109787709 B CN109787709 B CN 109787709B
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switch
uplink
downlink
encoder
sub
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CN109787709A (en
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刘铮
卢刘明
郭勇
黄新刚
张伟良
袁立权
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ZTE Corp
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ZTE Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems

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Abstract

The invention provides a passive optical network, a method and a device for determining encoding and decoding; wherein, passive optical network includes: a first switch and a second switch; the first switch is used for controlling the working states of a downlink encoder and a downlink decoder which are positioned in a downlink channel of a Passive Optical Network (PON); the second switch is used for controlling the working states of an upstream encoder and an upstream decoder located in an upstream channel of the PON. The invention solves the problem that the coding and decoding modes of the uplink and downlink channels are not flexible enough in the related technology.

Description

Passive optical network, and encoding and decoding determining method and device
Technical Field
The invention relates to the field of optical communication, in particular to a passive optical network, and a method and a device for determining encoding and decoding.
Background
In an Ethernet Passive Optical Network (EPON)/Gigabit Passive PON (GPON) in the related art, both an uplink channel and a downlink channel use an RS (255,223) or an RS (255,239) coding method, and parameters such as codeword length, code rate and the like of the uplink channel and the downlink channel are the same, where RS (255,223) indicates that the codeword length after coding is 255, the information bit number before coding is 223, and similarly, RS (255,239) indicates that the codeword length after coding is 255 and the information bit number before coding is 239. However, as the 50Gbps EPON/GPON system introduces Low Density Parity Check Code (LDPC) codes, the length of the LDPC Code word may be flexibly adjusted within a certain range according to the service requirements of the uplink and downlink channels. Therefore, the same encoding method is adopted for the uplink and downlink channels in the related art, and the requirement of a 50gbps epon/GPON system for introducing LDPC encoding is no longer met. Moreover, the large codebook scheme of LDPC 16K-bit proposed by the Institute of Electrical and Electronics Engineers (IEEE) standard in the related art has high computational complexity, large decoding processing delay of about 10us, and is also unacceptable for delay-sensitive high-speed services.
In view of the above technical problems in the related art, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the invention provides a passive optical network, a coding and decoding determining method and a coding and decoding determining device, which are used for at least solving the problem that a coding and decoding mode of an uplink channel and a downlink channel in the related technology is not flexible enough.
According to an embodiment of the present invention, there is provided a passive optical network including: a first switch and a second switch; the first switch is used for controlling the working states of a downlink encoder and a downlink decoder which are positioned in a downlink channel of a Passive Optical Network (PON); the second switch is used for controlling the working states of an upstream encoder and an upstream decoder located in an upstream channel of the PON.
Optionally, the downlink encoder includes: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downstream decoder includes: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder includes: an uplink RS encoder and an uplink LDPC encoder; the upstream decoder includes: an uplink RS decoder and an uplink LDPC decoder.
Optionally, the first switch comprises: a first sub-switch and a second sub-switch; the second switch includes: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; and the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
Optionally, when the value of the first sub-switch is a first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the first sub-switch value is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
Optionally, when the first sub-switch takes a value of a first designated value, the second sub-switch takes a value of a third designated value, the third sub-switch takes a value of a fifth designated value, and the fourth sub-switch takes a value of a seventh designated value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the system comprises an uplink RS encoder, an uplink LDPC encoder, and an uplink RS decoder and an uplink LDPC decoder which are cascaded.
Optionally, the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is between 2k bits and 16k bits.
Optionally, when the first sub-switch takes a second specified value, the second sub-switch takes a third specified value, the third sub-switch takes a sixth specified value, and the fourth sub-switch takes a seventh specified value, the codeword lengths used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers.
Optionally, when the first sub-switch takes a second specified value, the second sub-switch takes a third specified value, the third sub-switch takes a fifth specified value, and the fourth sub-switch takes an eighth specified value, the uplink RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
Alternatively, the codeword length used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
Optionally, the passive optical network further includes: an optical line terminal OLT and an optical network unit ONU; wherein, the OLT is used for transmitting at least one of the following appointed information to the ONU: information of a first sub-switch, information of a second sub-switch, information of a third sub-switch, information of a fourth sub-switch, a coding mode and a coding parameter used by an uplink RS encoder, a coding mode and a coding parameter used by a downlink RS encoder, a coding mode and a coding parameter used by an uplink LDPC encoder, and a coding mode and a coding parameter used by a downlink LDPC encoder; the ONU is used for receiving the specified information transmitted by the OLT and feeding back confirmation information for indicating that the ONU has correctly received the information to the OLT in case of correctly receiving the information.
Optionally, in a case where the OLT serves as a transmitter and the ONU serves as a receiver, the downlink RS encoder and the downlink LDPC encoder are located in the OLT, and the downlink RS decoder and the downlink LDPC decoder are located in the ONU; in the case where the OLT functions as a receiver and the ONU functions as a transmitter, the upstream RS encoder and the upstream LDPC encoder are located in the ONU, and the upstream RS decoder and the upstream LDPC decoder are located in the OLT.
According to an embodiment of the present invention, there is provided a codec determination method including: determining the state of a first switch and the state of a second switch in the passive optical network; and determining the coding mode and the decoding mode in the downlink channel according to the state of the first switch, and determining the coding mode and the decoding mode in the uplink channel according to the state of the second switch.
Optionally, the encoding mode in the downlink channel is determined by the operating state of a downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the operating state of a downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the operating state of an uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the operating state of an uplink decoder located in the uplink channel.
Optionally, the downlink encoder includes: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downstream decoder includes: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder includes: an uplink RS encoder and an uplink LDPC encoder; the upstream decoder includes: an uplink RS decoder and an uplink LDPC decoder.
Optionally, the first switch comprises: a first sub-switch and a second sub-switch; the second switch includes: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; and the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
Optionally, when the value of the first sub-switch is a first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the first sub-switch value is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
Optionally, when the first sub-switch takes a value of a first designated value, the second sub-switch takes a value of a third designated value, the third sub-switch takes a value of a fifth designated value, and the fourth sub-switch takes a value of a seventh designated value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the system comprises an uplink RS encoder, an uplink LDPC encoder, and an uplink RS decoder and an uplink LDPC decoder which are cascaded.
Optionally, the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is between 2k bits and 16k bits.
Optionally, when the first sub-switch takes a second specified value, the second sub-switch takes a third specified value, the third sub-switch takes a sixth specified value, and the fourth sub-switch takes a seventh specified value, the codeword lengths used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers.
Optionally, when the first sub-switch takes a second specified value, the second sub-switch takes a third specified value, the third sub-switch takes a fifth specified value, and the fourth sub-switch takes an eighth specified value, the uplink RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
Alternatively, the codeword length used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
According to an embodiment of the present invention, there is provided a codec determination apparatus including: the first determining module is used for determining the state of a first switch and the state of a second switch in the passive optical network; and the second determining module is used for determining the coding mode and the decoding mode in the downlink channel according to the state of the first switch and determining the coding mode and the decoding mode in the uplink channel according to the state of the second switch.
According to yet another embodiment of the present invention, there is also provided a storage medium including a stored program, wherein the program performs any one of the methods described above when executed.
According to yet another embodiment of the present invention, there is also provided a processor for executing a program, wherein the program executes to perform the method of any one of the above.
According to the invention, as the first switch and the second switch are added in the passive optical network, wherein the first switch is used for controlling the working states of the downlink encoder and the downlink decoder which are positioned in the downlink channel of the passive optical network PON; the second switch is used for controlling the working states of an uplink encoder and an uplink decoder which are positioned in an uplink channel of the PON; the coding and decoding modes of the downlink channel can be controlled through the first switch, the coding and decoding modes of the uplink channel are realized through the second switch, and the uplink channel and the downlink channel can use independent coding and decoding modes, so that the flexibility of the coding and decoding modes of the uplink channel and the downlink channel is improved, and the problem that the coding and decoding modes of the uplink channel and the downlink channel in the related technology are not flexible enough can be solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic structural diagram of a passive optical network provided in accordance with a preferred embodiment of the present invention;
fig. 2 is a flowchart illustrating a codec determination method according to an embodiment of the present invention;
fig. 3 is a block diagram of a codec determining apparatus according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure of a cascade of an RS codec and an LDPC codec according to the present invention;
fig. 5 is a schematic structural diagram of an RS codec switch of a downlink channel being 0 and an LDPC codec switch being 1 according to the preferred embodiment of the present invention;
fig. 6 is a schematic structural diagram of an RS codec switch of an uplink channel being 0 and an LDPC codec switch being 1 according to the preferred embodiment of the present invention;
fig. 7 is a schematic structural diagram of an RS codec switch of an uplink channel being 1 and an LDPC codec switch being 0 according to the preferred embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example 1
The embodiment of the present invention provides a Passive Optical Network, where the Passive Optical Network may be a digital Ethernet Passive Optical Network (EPON)/Gigabit Passive Optical Network (GPON), and specifically may be an EPON/GPON system that introduces 50Gbps, but is not limited thereto.
Fig. 1 is a schematic structural diagram of a passive optical network provided according to a preferred embodiment of the present invention, and as shown in fig. 1, the passive optical network provided by the embodiment of the present invention includes: a first switch 10 and a second switch 12; wherein, the first switch 10 is used to control the working states of the downstream encoder 102 and the downstream decoder 104 located in the downstream channel of the passive optical network PON; the second switch 12 is used to control the operation of an upstream encoder 122 and an upstream decoder 124 located in the upstream channel of the PON.
With the passive optical network, because a first switch 10 and a second switch 12 are added in the passive optical network, wherein the first switch 10 is used to control the working states of a downstream encoder 102 and a downstream decoder 104 located in a downstream channel of the passive optical network PON; the second switch 12 is used for controlling the working states of an upstream encoder 122 and an upstream decoder 124 located in an upstream channel of the PON; furthermore, the encoding and decoding mode of the downlink channel can be controlled by the first switch 10, and the encoding and decoding mode of the uplink channel can be realized by the second switch 12, so that the uplink and downlink channels can use respective independent encoding and decoding modes, and the flexibility of the uplink and downlink encoding and decoding modes is increased, and therefore, the problem that the encoding and decoding modes of the uplink and downlink channels are not flexible enough in the related art can be solved.
It should be noted that the coding scheme in the downlink channel is determined by the operating state of the downlink encoder 102 located in the downlink channel, the decoding scheme in the downlink channel is determined by the operating state of the downlink decoder 104 located in the downlink channel, the coding scheme in the uplink channel is determined by the operating state of the uplink encoder 122 located in the uplink channel, and the decoding scheme in the uplink channel is determined by the operating state of the uplink decoder 124 located in the uplink channel.
It should be noted that the above operating states may include: the operation and the stop operation are performed, but not limited thereto.
It should be noted that, the downlink encoder may include: a downlink RS encoder and a downlink LDPC encoder; the downlink decoder may include: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder may include: an uplink RS encoder and an uplink LDPC encoder; the uplink decoder may include: an uplink RS decoder and an uplink LDPC decoder.
In an embodiment of the present invention, the first switch 10 may include: a first sub-switch and a second sub-switch; the second switch 20 may include: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; and the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
The first switch 10, the first sub-switch, the second switch 20, the third sub-switch, and the fourth sub-switch may be digital switches, the first sub-switch and the third sub-switch may be RS codec switches, and the second sub-switch and the fourth sub-switch may be LDPC codec switches, but are not limited thereto.
It should be noted that, when the first sub-switch takes the value as the first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the first sub-switch value is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
The first specified value, the third specified value, the fifth specified value, and the seventh specified value may be the same or different; the second specified value, the fourth specified value, the sixth specified value, and the eighth specified value may be the same or different.
In an embodiment of the present invention, when the first sub-switch takes on the first specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the seventh specified value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the system comprises an uplink RS encoder, an uplink LDPC encoder, and an uplink RS decoder and an uplink LDPC decoder which are cascaded. The problem that an error-floor (error-floor) is easy to occur due to the small code word length (BER is less than 10^ (10)) can be avoided through the cascade connection of the encoder and the decoder.
The uplink RS encoder is an RS (255,223) or an RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); the downlink RS encoder is RS (255,223) or RS (255, 239); the downlink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
It should be noted that the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is between 2k bits and 16k bits. By using the code word length between 2k bits and 16k bits, a smaller code word length can be used, and the time delay of decoding processing can be further reduced.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the sixth specified value, and the fourth sub-switch takes on the seventh specified value, the codeword lengths used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers. That is, the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder may use all codeword lengths.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the eighth specified value, the uplink RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239. By the method, different coding and decoding modes used by the uplink and downlink channels are realized.
It should be noted that the length of the codeword used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
In an embodiment of the present invention, the passive optical network may further include: an optical line terminal OLT and an optical network unit ONU; wherein, the OLT is used for transmitting at least one of the following appointed information to the ONU: information of a first sub-switch, information of a second sub-switch, information of a third sub-switch, information of a fourth sub-switch, a coding mode and a coding parameter used by an uplink RS encoder, a coding mode and a coding parameter used by a downlink RS encoder, a coding mode and a coding parameter used by an uplink LDPC encoder, and a coding mode and a coding parameter used by a downlink LDPC encoder; the ONU is used for receiving the specified information transmitted by the OLT and feeding back confirmation information for indicating that the ONU has correctly received the information to the OLT in case of correctly receiving the information.
It should be noted that, the information of the first sub switch may include: the first sub-switch, the function of the first sub-switch, and the value of the first sub-switch, but not limited thereto. The information of the second sub-switch may include: a second sub-switch, a function of the second sub-switch and a value of the second sub-switch, but not limited thereto; the information of the third sub-switch may include: a third sub-switch, a function of the third sub-switch, and a value of the third sub-switch, but not limited thereto; the information of the fourth sub switch may include: a fourth sub-switch, a function of the fourth sub-switch, and a value of the fourth sub-switch, but not limited thereto.
It should be noted that, when the OLT serves as a transmitter and the ONU serves as a receiver, the downlink RS encoder and the downlink LDPC encoder are located in the OLT, and the downlink RS decoder and the downlink LDPC decoder are located in the ONU; in the case where the OLT functions as a receiver and the ONU functions as a transmitter, the upstream RS encoder and the upstream LDPC encoder are located in the ONU, and the upstream RS decoder and the upstream LDPC decoder are located in the OLT.
Example 2
An embodiment of the present invention further provides a method embodiment of a codec determining method, where the embodiment may be applied to the passive optical network described in embodiment 1, and fig. 2 is a schematic flow diagram of the codec determining method provided in the embodiment of the present invention, and as shown in fig. 2, the method includes:
step S202, determining the state of a first switch and the state of a second switch in the passive optical network;
and step S204, determining the coding mode and the decoding mode in the downlink channel according to the state of the first switch, and determining the coding mode and the decoding mode in the uplink channel according to the state of the second switch.
According to the method, the first switch and the second switch are added in the passive optical network, wherein the coding and decoding modes in the downlink channel and the coding and decoding modes in the uplink channel are respectively determined according to the state of the first switch and the state of the second switch, so that the uplink channel and the downlink channel can use independent coding and decoding modes, and the flexibility of the uplink coding and decoding modes and the downlink coding and decoding modes is improved, and therefore the problem that the coding and decoding modes of the uplink channel and the downlink channel in the related technology are not flexible enough can be solved.
It should be noted that the encoding mode in the downlink channel is determined by the operating state of the downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the operating state of the downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the operating state of the uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the operating state of the uplink decoder located in the uplink channel.
It should be noted that the above operating states may include: the operation and the stop operation are performed, but not limited thereto.
It should be noted that, the downlink encoder may include: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downlink decoder may include: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder may include: an uplink RS encoder and an uplink LDPC encoder; the uplink decoder may include: an uplink RS decoder and an uplink LDPC decoder.
In one embodiment of the present invention, the first switch may include: a first sub-switch and a second sub-switch; the second switch may include: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; and the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
The first switch, the first sub-switch, the second switch, the third sub-switch, and the fourth sub-switch may be digital switches, the first sub-switch and the third sub-switch may be RS codec switches, and the second sub-switch and the fourth sub-switch may be LDPC codec switches, but are not limited thereto.
It should be noted that, when the first sub-switch takes the value as the first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the first sub-switch value is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
The first specified value, the third specified value, the fifth specified value, and the seventh specified value may be the same or different; the second specified value, the fourth specified value, the sixth specified value, and the eighth specified value may be the same or different.
In an embodiment of the present invention, when the first sub-switch takes on the first specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the seventh specified value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the system comprises an uplink RS encoder, an uplink LDPC encoder, and an uplink RS decoder and an uplink LDPC decoder which are cascaded. The problem that an error-floor (error-floor) is easy to occur due to the small code word length (BER is less than 10^ (10)) can be avoided through the cascade connection of the encoder and the decoder.
The uplink RS encoder is an RS (255,223) or an RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); the downlink RS encoder is RS (255,223) or RS (255, 239); the downlink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
It should be noted that the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is between 2k bits and 16k bits. Namely, a smaller codeword length can be used, and further, the time delay of decoding processing can be reduced.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the sixth specified value, and the fourth sub-switch takes on the seventh specified value, the codeword lengths used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the eighth specified value, the uplink RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
It should be noted that the length of the codeword used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
In an embodiment of the present invention, the passive optical network may further include: an optical line terminal OLT and an optical network unit ONU; before the step S202, the method may further include: the OLT negotiates with the ONU; specifically, the method comprises the following steps:
the OLT transmits at least one of the following specifying information to the ONU: information of a first sub-switch, information of a second sub-switch, information of a third sub-switch, information of a fourth sub-switch, a coding mode and a coding parameter used by an uplink RS encoder, a coding mode and a coding parameter used by a downlink RS encoder, a coding mode and a coding parameter used by an uplink LDPC encoder, and a coding mode and a coding parameter used by a downlink LDPC encoder; the ONU receives the designation information transmitted from the OLT and feeds back confirmation information indicating that the ONU has correctly received the information to the OLT in the case of correctly receiving the information.
It should be noted that, the information of the first sub switch may include: the first sub-switch, the function of the first sub-switch, and the value of the first sub-switch, but not limited thereto. The information of the second sub-switch may include: a second sub-switch, a function of the second sub-switch and a value of the second sub-switch, but not limited thereto; the information of the third sub-switch may include: a third sub-switch, a function of the third sub-switch, and a value of the third sub-switch, but not limited thereto; the information of the fourth sub switch may include: a fourth sub-switch, a function of the fourth sub-switch, and a value of the fourth sub-switch, but not limited thereto.
It should be noted that, when the OLT serves as a transmitter and the ONU serves as a receiver, the downlink RS encoder and the downlink LDPC encoder are located in the OLT, and the downlink RS decoder and the downlink LDPC decoder are located in the ONU; in the case where the OLT functions as a receiver and the ONU functions as a transmitter, the upstream RS encoder and the upstream LDPC encoder are located in the ONU, and the upstream RS decoder and the upstream LDPC decoder are located in the OLT.
Optionally, the main body of the above steps may be an OLT, an ONU, or the like, but is not limited thereto.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 3
In this embodiment, a device for determining encoding and decoding is further provided, where the device is used to implement the foregoing embodiments and preferred embodiments, and details of the foregoing description are omitted. As used below, the term "module" may be a combination of software and hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 3 is a block diagram of a codec decision apparatus according to an embodiment of the present invention, and as shown in fig. 3, the apparatus includes:
a first determining module 32, configured to determine a state of a first switch and a state of a second switch in the passive optical network;
and a second determining module 34, connected to the first determining module 32, for determining the coding mode and the decoding mode in the downlink channel according to the state of the first switch, and determining the coding mode and the decoding mode in the uplink channel according to the state of the second switch.
By the device, the first switch and the second switch are added in the passive optical network, wherein the coding and decoding modes in the downlink channel and the coding and decoding modes in the uplink channel are respectively determined according to the state of the first switch and the state of the second switch, so that the uplink channel and the downlink channel can use independent coding and decoding modes, and the flexibility of the uplink coding and the downlink coding and decoding modes is improved, and therefore the problem that the coding and decoding modes of the uplink channel and the downlink channel in the related technology are not flexible enough can be solved.
It should be noted that the encoding mode in the downlink channel is determined by the operating state of the downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the operating state of the downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the operating state of the uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the operating state of the uplink decoder located in the uplink channel.
It should be noted that the above operating states may include: the operation and the stop operation are performed, but not limited thereto.
It should be noted that, the downlink encoder may include: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downlink decoder may include: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder may include: an uplink RS encoder and an uplink LDPC encoder; the uplink decoder may include: an uplink RS decoder and an uplink LDPC decoder.
In one embodiment of the present invention, the first switch may include: a first sub-switch and a second sub-switch; the second switch may include: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; and the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
The first switch, the first sub-switch, the second switch, the third sub-switch, and the fourth sub-switch may be digital switches, the first sub-switch and the third sub-switch may be RS codec switches, and the second sub-switch and the fourth sub-switch may be LDPC codec switches, but are not limited thereto.
It should be noted that, when the first sub-switch takes the value as the first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the first sub-switch value is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
The first specified value, the third specified value, the fifth specified value, and the seventh specified value may be the same or different; the second specified value, the fourth specified value, the sixth specified value, and the eighth specified value may be the same or different.
In an embodiment of the present invention, when the first sub-switch takes on the first specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the seventh specified value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the system comprises an uplink RS encoder, an uplink LDPC encoder, and an uplink RS decoder and an uplink LDPC decoder which are cascaded. The problem that an error-floor (error-floor) is easy to occur due to the small code word length (BER is less than 10^ (10)) can be avoided through the cascade connection of the encoder and the decoder.
The uplink RS encoder is an RS (255,223) or an RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); the downlink RS encoder is RS (255,223) or RS (255, 239); the downlink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
It should be noted that the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is between 2k bits and 16k bits. Namely, a smaller codeword length can be used, and further, the time delay of decoding processing can be reduced.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the sixth specified value, and the fourth sub-switch takes on the seventh specified value, the codeword lengths used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers.
In an embodiment of the present invention, when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the eighth specified value, the uplink RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); here, RS (255,223) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) denotes an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
It should be noted that the length of the codeword used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
The above-described apparatus may be located in the OLT or may be located in the ONU, but is not limited thereto.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Example 4
An embodiment of the present invention further provides a storage medium including a stored program, where the program executes any one of the methods described above.
Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide a processor configured to execute a program, where the program executes to perform any of the steps in the method.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
For a better understanding of the present invention, the present invention is further described below in conjunction with the preferred embodiments.
The preferred embodiment of the present invention provides a preferred scheme: adding RS codec switches (equivalent to the first sub-switch and the third sub-switch) and LDPC codec switches (equivalent to the second sub-switch and the fourth sub-switch) in a downlink channel; and an RS codec switch and an LDPC codec switch are added in an uplink channel. The downlink channel and the uplink channel can use different coding modes, and the switch is 1 to indicate that the coder and the decoder work; the switch is 0, indicating that the codec is off. The 1 may correspond to the first designated value, the third designated value, the fifth designated value, and the seventh designated value, and the 0 may correspond to the second designated value, the fourth designated value, the sixth designated value, and the eighth designated value.
It should be noted that: the RS coder-decoder and the interleaver use the coding and interleaving mode of the original protocol; when the RS codec is turned off, the LDPC codec can utilize the original interleaver and deinterleaver; when the LDPC codec is turned off, the 50Gbps EPON/GPON system can seamlessly fall back to the 10Gbps EPON/GPON system.
When the RS codec switch is 1 and the LDPC codec switch is 1, the RS encoder and the LDPC codec are cascaded. At this time, the RS codec follows the original RS (255,223) or RS (255, 239); the LDPC codec may use a smaller codeword length between 2K-bit and 16K-bit. The decoding processing time delay is reduced, and the problem that error-floor is easy to occur below a small word length @ BER ^ 10 (-10) is solved through a cascade RS codec. Fig. 4 is a schematic structural diagram of the cascade of the RS codec and the LDPC codec preferably provided in accordance with the present invention.
In the preferred embodiment, the uplink channel and the downlink channel use independent encoding methods and encoding parameters, and the Optical Line Terminal (OLT) transmits the switching information of the RS codec switch, the LDPC codec switch, the RS (n1, k1), the LDPC (n2, k2), the RS codec switch, the LDPC codec switch, the RS (n3, k3), and the LDPC (n4, k4) and the switching information of (n1, k1), (n2, k2), (n3, k3), (n4, k4) to the ONU, and feeds back ACK information to the OLT if the Optical Network Unit (ONU) receives the information correctly. nx represents the length of the code word after encoding, and kx represents the number of information bits before encoding.
The first preferred embodiment:
an RS codec switch and an LDPC codec switch are added in a downlink channel; and an RS codec switch and an LDPC codec switch are added in an uplink channel.
When the RS codec switch is equal to 1 and the LDPC codec switch is equal to 1, the RS encoder is cascaded with the LDPC codec. At this time, the RS codec follows the original RS (255,223) or RS (255, 239);
the LDPC codec may use a smaller codeword length between 2K-bit and 16K-bit. The processing time delay of the decoder is reduced, and the problem that error-floor is easy to occur below a small word length @ BER ^ 10 (-10) is solved through the cascade RS codec.
The structure of the cascade of the RS codec and the LDPC codec is shown in FIG. 4.
The OLT transmits the switch information of the RS codec switch of the downlink channel, the LDPC codec switch, the LDPC (n2, k2), the switch information of the RS codec switch of the uplink channel, the LDPC codec switch, the LDPC (n4, k4), the parameter information of (n2, k2), (n4, k4) and the like to the ONU, and the ONU feeds back ACK information to the OLT if the ONU receives the ACK information correctly. nx represents the length of the code word after encoding, and kx represents the number of information bits before encoding.
The second preferred embodiment:
an RS codec switch and an LDPC codec switch are added in a downlink channel; and an RS codec switch and an LDPC codec switch are added in an uplink channel.
The switch of the RS codec of the downlink channel is equal to 0, and the switch of the LDPC codec is equal to 1;
the switch of the RS codec of the uplink channel is 0, and the switch of the LDPC codec is 1;
the LDPC codec can use all codeword lengths and utilize the interleaver and deinterleaver of the original protocol.
The LDPC codec for the downlink channel and the LDPC codec for the uplink channel are shown in fig. 5 and 6, where fig. 5 is a schematic structural diagram of an RS codec switch for the downlink channel being 0 and an LDPC codec switch being 1 according to the preferred embodiment of the present invention, and fig. 6 is a schematic structural diagram of an RS codec switch for the uplink channel being 0 and an LDPC codec switch being 1 according to the preferred embodiment of the present invention.
The OLT transmits the switch information of the RS codec switch of the downlink channel, the LDPC codec switch, the LDPC (n2, k2), the switch information of the RS codec switch of the uplink channel, the LDPC codec switch, the LDPC (n4, k4), the parameter information of (n2, k2), (n4, k4) and the like to the ONU, and the ONU feeds back ACK information to the OLT if the ONU receives the ACK information correctly. nx represents the length of the code word after encoding, and kx represents the number of information bits before encoding.
The third preferred embodiment:
an RS codec switch and an LDPC codec switch are added in a downlink channel; and an RS codec switch and an LDPC codec switch are added in an uplink channel.
The switch of the RS codec of the downlink channel is equal to 0, and the switch of the LDPC codec is equal to 1;
the switch of the RS codec of the uplink channel is 1, and the switch of the LDPC codec is 0;
at this time, the RS codec of the uplink channel adopts the original RS (255,223) or RS (255,239), and can utilize the characteristics of RS codes to overcome the uplink burst errors well and can also utilize the characteristics of low processing delay of RS decoders;
the downlink channel LDPC coder-decoder can use all code word lengths and is suitable for the characteristic of large downlink service block length.
The structure of the LDPC codec for the downlink channel and the RS codec for the uplink channel is shown in fig. 5 and 7, where fig. 7 is a schematic structural diagram that the RS codec switch for the uplink channel is 1 and the LDPC codec switch is 0 according to the preferred embodiment of the present invention.
The OLT transmits the switching information of the RS codec switch of the downlink channel, the LDPC codec switch, the LDPC (n2, k2), the switching information of the RS codec switch of the uplink channel and the LDPC codec switch, parameter information of (n2, k2) and the like to the ONU, and if the ONU receives the information correctly, the ONU feeds back ACK information to the OLT. nx represents the length of the code word after encoding, and kx represents the number of information bits before encoding.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (23)

1. A passive optical network, comprising: a first switch and a second switch; the first switch is used for controlling the working states of a downlink encoder and a downlink decoder which are positioned in a downlink channel of a Passive Optical Network (PON); the second switch is used for controlling the working states of an upstream encoder and an upstream decoder which are positioned in an upstream channel of the PON;
the encoding mode in the downlink channel is determined by the working state of a downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the working state of a downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the working state of an uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the working state of an uplink decoder located in the uplink channel;
wherein the operating state comprises: and performing work and stopping work.
2. The passive optical network of claim 1, wherein the downstream encoder comprises: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downstream decoder includes: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder includes: an uplink RS encoder and an uplink LDPC encoder; the upstream decoder includes: an uplink RS decoder and an uplink LDPC decoder.
3. A passive optical network as claimed in claim 2, wherein the first switch comprises: a first sub-switch and a second sub-switch; the second switch includes: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
4. The PON of claim 3, wherein when the first sub-switch value is a first designated value, the working states of the downlink RS encoder and the downlink RS decoder are working; when the value of the first sub-switch is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth specified value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth specified value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
5. The PON of claim 4, wherein when the first sub-switch value is the first specified value, the second sub-switch value is the third specified value, the third sub-switch value is the fifth specified value, and the fourth sub-switch value is the seventh specified value, the RS decoder is cascaded with the LDPC decoder; the uplink RS encoder and the uplink LDPC encoder, and the uplink RS decoder and the uplink LDPC decoder are cascaded.
6. The PON of claim 5, wherein the codeword word lengths used by the upstream LDPC encoder, the upstream LDPC decoder, the downstream LDPC encoder and the downstream LDPC decoder are between 2k bits and 16k bits.
7. The PON of claim 4, wherein when the first sub-switch value is the second specified value, the second sub-switch value is the third specified value, the third sub-switch value is the sixth specified value, and the fourth sub-switch value is the seventh specified value, the lengths of the codewords used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder are arbitrary numbers.
8. The PON of claim 4, wherein when the first sub-switch value is the second specified value, the second sub-switch value is the third specified value, the third sub-switch value is the fifth specified value, and the fourth sub-switch value is the eighth specified value, the RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); wherein RS (255,223) represents an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) represents an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
9. The passive optical network of claim 8, wherein the codeword length used by the downstream LDPC encoder and the downstream LDPC decoder is an arbitrary number.
10. The passive optical network of claim 3, further comprising: an optical line terminal OLT and an optical network unit ONU;
wherein the OLT is configured to communicate at least one of the following designation information to the ONU: information of the first sub-switch, information of the second sub-switch, information of the third sub-switch, information of the fourth sub-switch, a coding mode and a coding parameter used by the uplink RS encoder, a coding mode and a coding parameter used by the downlink RS encoder, a coding mode and a coding parameter used by the uplink LDPC encoder, and a coding mode and a coding parameter used by the downlink LDPC encoder;
the ONU is used for receiving the specified information transmitted by the OLT and feeding back confirmation information for indicating that the ONU correctly receives the information to the OLT under the condition of correctly receiving the information.
11. The passive optical network of claim 10,
in the case that the OLT serves as a transmitter and the ONU serves as a receiver, the downstream RS encoder and the downstream LDPC encoder are located in the OLT, and the downstream RS decoder and the downstream LDPC decoder are located in the ONU;
in the case where the OLT functions as a receiver and the ONU functions as a transmitter, the upstream RS encoder and the upstream LDPC encoder are located in the ONU, and the upstream RS decoder and the upstream LDPC decoder are located in the OLT.
12. A method for determining coding and decoding, comprising:
determining the state of a first switch and the state of a second switch in the passive optical network;
determining a coding mode and a decoding mode in a downlink channel according to the state of the first switch, and determining a coding mode and a decoding mode in an uplink channel according to the state of the second switch;
the encoding mode in the downlink channel is determined by the working state of a downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the working state of a downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the working state of an uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the working state of an uplink decoder located in the uplink channel;
wherein the operating state comprises: and performing work and stopping work.
13. The method of claim 12, wherein the downstream encoder comprises: a downlink RS encoder and a downlink low density parity check code LDPC encoder; the downstream decoder includes: a downlink RS decoder, a downlink LDPC decoder; the uplink encoder includes: an uplink RS encoder and an uplink LDPC encoder; the upstream decoder includes: an uplink RS decoder and an uplink LDPC decoder.
14. The method of claim 13, wherein the first switch comprises: a first sub-switch and a second sub-switch; the second switch includes: a third sub-switch and a fourth sub-switch; the first sub-switch is used for controlling the working states of the downlink RS encoder and the downlink RS decoder; the second sub-switch is used for controlling the working states of the downlink LDPC encoder and the downlink LDPC decoder; the third sub-switch is used for controlling the working states of the uplink RS encoder and the uplink RS decoder; the fourth sub-switch is used for controlling the working states of the uplink LDPC encoder and the uplink LDPC decoder.
15. The method according to claim 14, wherein when the first sub-switch takes on a first designated value, the operating status of the downlink RS encoder and the downlink RS decoder is operating; when the value of the first sub-switch is a second designated value, the working states of the downlink RS encoder and the downlink RS decoder are stop working; when the value of the second sub-switch is a third designated value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are working; when the value of the second sub-switch is a fourth specified value, the working states of the downlink LDPC encoder and the downlink LDPC decoder are stop working; when the value of the third sub-switch is a fifth specified value, the working states of the uplink RS encoder and the uplink RS decoder are working; when the value of the third sub-switch is a sixth specified value, the working states of the uplink RS encoder and the uplink RS decoder are stopped; when the value of the fourth sub-switch is a seventh designated value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are working; and when the value of the fourth sub-switch is an eighth specified value, the working states of the uplink LDPC encoder and the uplink LDPC decoder are stop working.
16. The method according to claim 15, wherein when the first sub-switch value is the first specified value, the second sub-switch value is the third specified value, the third sub-switch value is the fifth specified value, and the fourth sub-switch value is the seventh specified value, the downlink RS encoder, the downlink LDPC encoder, the downlink RS decoder, and the downlink LDPC decoder are cascaded; the uplink RS encoder and the uplink LDPC encoder, and the uplink RS decoder and the uplink LDPC decoder are cascaded.
17. The method of claim 16, wherein the codeword length used by the upstream LDPC encoder, the upstream LDPC decoder, the downstream LDPC encoder, and the downstream LDPC decoder is between 2k bits and 16k bits.
18. The method according to claim 15, wherein when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the sixth specified value, and the fourth sub-switch takes on the seventh specified value, the codeword length used by the uplink LDPC encoder, the uplink LDPC decoder, the downlink LDPC encoder, and the downlink LDPC decoder is an arbitrary number.
19. The method of claim 15, wherein when the first sub-switch takes on the second specified value, the second sub-switch takes on the third specified value, the third sub-switch takes on the fifth specified value, and the fourth sub-switch takes on the eighth specified value, the upstream RS encoder is RS (255,223) or RS (255, 239); the uplink RS decoder is RS (255,223) or RS (255, 239); wherein RS (255,223) represents an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 223, and RS (255,239) represents an encoder in which the code word length after encoding is 255 and the number of information bits before encoding is 239.
20. The method of claim 19, wherein the codeword length used by the downlink LDPC encoder and the downlink LDPC decoder is an arbitrary number.
21. An apparatus for determining a codec, comprising:
the first determining module is used for determining the state of a first switch and the state of a second switch in the passive optical network;
a second determining module, configured to determine a coding mode and a decoding mode in a downlink channel according to the state of the first switch, and determine a coding mode and a decoding mode in an uplink channel according to the state of the second switch;
the encoding mode in the downlink channel is determined by the working state of a downlink encoder located in the downlink channel, the decoding mode in the downlink channel is determined by the working state of a downlink decoder located in the downlink channel, the encoding mode in the uplink channel is determined by the working state of an uplink encoder located in the uplink channel, and the decoding mode in the uplink channel is determined by the working state of an uplink decoder located in the uplink channel;
wherein the operating state comprises: and performing work and stopping work.
22. A storage medium comprising a stored program, wherein the program when executed performs the method of any one of claims 12 to 20.
23. A processor, configured to run a program, wherein the program when running performs the method of any one of claims 12 to 20.
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