CN109786331B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109786331B CN109786331B CN201711105051.0A CN201711105051A CN109786331B CN 109786331 B CN109786331 B CN 109786331B CN 201711105051 A CN201711105051 A CN 201711105051A CN 109786331 B CN109786331 B CN 109786331B
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Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is provided with a first fin part, a first mask layer is arranged on the first fin part, and the second area is provided with a second initial fin part; forming a first doping layer on the side wall of the first fin part, wherein first doping ions are arranged in the first doping layer; forming an initial isolation layer, wherein the top of the first mask layer is exposed out of the initial isolation layer; after the initial isolation layer is formed, removing part of the second initial fin part to form a second fin part; forming a third fin part on the second fin part by an epitaxial process, wherein second doped ions are arranged in the third fin part, and the conductivity type of the second doped ions is opposite to that of the first doped ions; forming a fourth fin part on the third fin part; removing part of the initial isolation layer to form an isolation layer, wherein the top of the isolation layer is lower than the top of the fourth fin part and higher than or flush with the top of the third fin part; after the isolation layer is formed, removing the first doping layer on the side wall of the first fin part; and then annealing treatment is carried out. The method has few steps.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, in order to achieve higher operation speed, larger data storage capacity and more functions, semiconductor devices are developed towards higher element density and higher integration level, and therefore, gate structures of transistors become thinner and shorter, so that source and drain doped regions in substrates on two sides of the gate structures are too close to each other, and short channel effects of the transistors are more likely to occur.
In the prior art, methods for suppressing short channel effects include: increasing the resistance between the source and drain doped regions; or inhibiting the migration of carriers in the channel between the source and drain doped regions. The method for increasing the resistance between the source-drain doped regions comprises the following steps: lightly doping; alternatively, a semiconductor-on-insulator material is used as the substrate. The method for inhibiting the carrier from moving in the channel between the source-drain doped regions comprises the following steps: the channel region, the pocket region or the halo region is over-doped with opposite type ions.
However, the conventional process for suppressing the short channel effect is complicated.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aim to reduce the process complexity of inhibiting the short channel effect.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is provided with a first fin part on the substrate, the top of the first fin part is provided with a first mask layer, and the second area is provided with a second initial fin part on the substrate; forming a first doping layer on the side wall of the first fin portion, wherein first doping ions are arranged in the first doping layer; forming an initial isolation layer on the substrate, wherein the initial isolation layer exposes the top surface of the first mask layer and covers the first doping layer and the side wall of the second initial fin portion; after the initial isolation layer is formed, removing part of the second initial fin part to form a second fin part, wherein the initial isolation layer on the second fin part is internally provided with a first opening; forming a third fin part on the second fin part by using the first mask layer and the initial isolation layer on the side wall of the first opening as masks and adopting an epitaxial process, wherein the third fin part is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions; forming a fourth fin portion on the third fin portion, wherein the top surface of the fourth fin portion is exposed out of the top surface of the initial isolation layer; and removing part of the initial isolation layer to form an isolation layer, wherein the top surface of the isolation layer is lower than the top surfaces of the first fin portion and the fourth fin portion, and the top surface of the isolation layer is higher than or flush with the top surface of the third fin portion.
Optionally, the material of the first doped layer includes: oxygen gasSilicon is oxidized; the atomic percentage concentration of the first doping ions in the first doping layer is as follows: 5.0E19atoms/cm3～8.0E21atoms/cm3。
Optionally, the first doping layer further covers a sidewall of the second fin portion; the forming steps of the first doping layer, the initial isolation layer, the second fin portion and the first opening include: forming a first initial doping layer on the side walls of the first fin part and the second initial fin part; forming an initial isolation layer on the substrate, the first fin part, the second initial fin part and the side wall of the first initial doping layer, wherein the top of the initial isolation layer is exposed out of the top surface of the first mask layer; removing part of the second initial fin part to form a second fin part, wherein the initial isolation layer on the second fin part is internally provided with a first opening; and removing the first initial doping layer on the side wall of the first opening, and forming a first doping layer on the side walls of the first fin part and the second fin part.
Optionally, after the forming the first initial doping layer and before the forming the initial isolation layer, the forming method further includes: forming a stop layer on the surface of the side wall of the first initial doping layer; the material of the stop layer comprises: silicon nitride.
Optionally, the atomic percentage concentration of the second doping ions in the third fin portion is: 5.0E19atoms/cm3～5.0E21atoms/cm3。
Optionally, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor; the first doped ions are P-type ions, and the second doped ions are N-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.
Optionally, the material of the third fin portion includes silicon germanium or silicon; the forming process of the third fin portion comprises the following steps: an epitaxial growth process; when the third fin portion is made of silicon germanium, the parameters of the epitaxial growth process include: a silicon source gas comprising SiH, a germanium source gas, hydrogen chloride and hydrogen4Or SiH2Cl2The germanium source gas comprises GeH4The flow rates of the silicon source gas, the germanium source gas and the hydrogen chloride gas are all 1 standardThe milliliter/minute is between 2000 and 0.1 standard milliliter/minute, and the flow rate of the hydrogen is between 50 and 0.1 standard liter per minute; the process for doping the second doping ions in the third fin portion comprises an in-situ doping process; when the second doping ions are phosphorus ions, the parameters of the in-situ doping process include: the dopant source comprises a phosphorus source comprising PH3And the flow rate of the doping source is 1-2000 standard ml/min.
Optionally, the first region is used to form a PMOS transistor, and the second region is used to form an NMOS transistor; the first doped ions are N-type ions, and the second doped ions are P-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.
Optionally, the material of the third fin portion comprises a compound composed of III-V group elements or silicon; the compound composed of III-V group elements comprises indium gallium arsenic;
optionally, the annealing process includes: spike annealing process or laser annealing process; the parameters of the spike annealing process include: the temperature is 900 ℃ to 1050 ℃.
Optionally, the material of the first mask layer includes silicon nitride or silicon oxynitride.
Optionally, after forming the isolation layer, the forming method further includes: forming a first gate structure crossing the first fin portion; forming first source-drain doped regions in the first fin portions on two sides of the first gate structure respectively, wherein the first source-drain doped regions are provided with first source-drain ions, and the conductivity types of the first source-drain ions and the first doped ions are opposite; forming a second gate structure crossing the second fin portion, the third fin portion and the fourth fin portion; and forming second source drain doped regions in the fourth fin parts on two sides of the second gate structure respectively, wherein second source drain ions are arranged in the second source drain doped regions, and the conductivity types of the second source drain ions and the second doped ions are opposite.
The present invention also provides a semiconductor structure comprising: the substrate comprises a first area and a second area, wherein the first area is provided with a first fin part on the substrate, the bottom of the first fin part is provided with first doped ions, and the top of the first fin part is provided with a first mask layer; the first doping layer is positioned on the side wall of the first fin part; the second fin portion is located on the second region substrate, a third fin portion and a fourth fin portion are located on the third fin portion, second doped ions are arranged in the third fin portion, and the conductivity type of the second doped ions is opposite to that of the first doped ions; the isolation layer is located on the substrate, the top of the isolation layer is lower than the top surfaces of the first fin portion and the fourth fin portion, and the top surface of the isolation layer is higher than or flush with the top surfaces of the first doping layer and the third fin portion.
Optionally, the material of the first doped layer includes: silicon oxide; the atomic percentage concentration of the first doping ions in the first fin part is as follows: 5.0E19atoms/cm3～8.0E21atoms/cm3。
Optionally, the atomic percentage concentration of the second doping ions in the third fin portion is: 5.0E19atoms/cm3～5.0E21atoms/cm3。
Optionally, the first region is used to form an NMOS transistor, and the second region is used to form a PMOS transistor; the first doped ions are P-type ions, and the second doped ions are N-type ions; the N-type ions comprise phosphorus ions or arsenic ions, and the P-type ions comprise boron ions; the material of the third fin portion comprises silicon germanium or silicon.
Optionally, the first region is used to form a PMOS transistor, and the second region is used to form an NMOS transistor; the first doped ions are N-type ions, and the second doped ions are P-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions.
Optionally, the material of the third fin portion comprises a compound composed of III-V group elements or silicon; the compound of III-V group elements comprises indium gallium arsenic.
Optionally, the material of the first mask layer includes silicon nitride or silicon oxynitride.
Optionally, the semiconductor structure further includes: a first gate structure crossing the first fin portion; the first source-drain doped regions are respectively positioned in the first fin parts on two sides of the first grid structure, first source-drain ions are arranged in the first source-drain doped regions, and the conductivity types of the first source-drain ions and the first doped ions are opposite; a second gate structure spanning the second fin portion, the third fin portion and the fourth fin portion; and the second source-drain doped regions are respectively positioned in the fourth fin parts at two sides of the second grid structure, second source-drain ions are arranged in the second source-drain doped regions, and the conductivity types of the second source-drain ions and the second doped ions are opposite.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first doping layer is formed on the side wall of the first fin part, the first doping layer is internally provided with first doping ions, and the first doping ions are used for preventing the series connection between the first source drain doping regions formed in the first fin part subsequently. And forming a third fin part on the top of the second fin part after the first doping layer is formed. The third fin portion is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions. The second doped ions are used for preventing the second source drain doped regions formed in the fourth fin portion from being communicated with each other subsequently. In the process of forming the third fin portion, the side wall of the first fin portion is covered by the first doping layer, and the top of the first fin portion is covered by the first mask layer, so that second doping ions can be doped into the third fin portion only by an epitaxial growth process without an additional patterning process, and the second doping ions are not easily doped into the first fin portion. The method is beneficial to simplifying process steps and reducing process complexity.
Further, after forming the first preliminary doping layer and before forming the preliminary isolation layer, a stop layer is formed on the first preliminary doping layer. The stop layer is used for protecting the initial isolation layer on the side wall of the first opening when the first initial doping layer on the side wall of the first opening is removed subsequently.
In the semiconductor structure provided by the technical scheme of the invention, the semiconductor structure further comprises a first source drain doped region positioned in the first fin portion, and first source drain ions are arranged in the first source drain doped region. The bottom of the first fin part is provided with first doped ions, the first doped ions are positioned below the first region channel region, and the conductivity types of the first doped ions and the first source drain ions are opposite, so that the first doped ions can prevent the first source drain doped region from being communicated with each other, and the short channel effect of a first region device can be inhibited; also, the semiconductor device further includes: and the second source-drain doped region is positioned in the fourth fin portion, second source-drain ions are arranged in the second source-drain doped region, and the conductivity type of the second doped ions is opposite to that of the second source-drain ions, so that the second doped ions can inhibit the short channel effect of a second region device.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the process steps for suppressing short channel effects are complicated.
Fig. 1 to 2 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes an NMOS region and a PMOS region, and the substrate 100 in the NMOS region and the PMOS region has a fin 101 thereon; forming a first mask layer 102 on the PMOS area substrate 100; and performing first ion implantation on the NMOS region fin part 101 by taking the first mask layer 102 as a mask, and doping first doping ions 103 at the bottom of the NMOS region fin part 101.
Referring to fig. 2, the first mask layer 102 is removed; forming a second mask layer 104 on the NMOS area substrate 100; and performing second ion implantation on the PMOS region fin portion 101 by using the second mask layer 104 as a mask, and doping second doping ions 105 into the bottom of the PMOS region fin portion 101, wherein the conductivity type of the second doping ions 105 is opposite to the conductivity type of the first doping ions 103.
After doping the second dopant ions 105 into the PMOS region fin 101, the method further includes: forming a first gate structure crossing the NMOS region fin portion 101; forming first source-drain doped regions in the fin portions 101 on two sides of the first gate structure respectively, wherein first source-drain ions are arranged in the first source-drain doped regions, and the conductivity type of the first source-drain ions is opposite to that of the first doped ions 103; forming a second gate structure crossing the PMOS region fin portion 101; and second source-drain doped regions are respectively formed in the fin parts 101 on two sides of the second gate structure, second source-drain ions are arranged in the second source-drain doped regions, and the conductivity type of the second source-drain ions is opposite to that of the second doped ions 105.
In the method, the conductivity type of the first doped ion 103 is opposite to the conductivity type of the first source drain ion, so that the first doped ion 103 can prevent a series-pass effect between the first source drain doped regions, so that a device in an NMOS region is not easy to leak electricity, and the performance of the device in the NMOS region is improved. Correspondingly, the conductivity type of the second doped ions 105 is opposite to that of the second source drain ions, so that the second doped ions 105 can prevent a series-pass effect between the second source drain doped regions, so that the PMOS region device is not easy to leak electricity, and the performance of the PMOS region device is improved.
However, since the conductivity types of the first doping ions 103 and the second doping ions 105 are opposite, a first patterning process is required to dope the first doping ions 103 into the NMOS region partial fin 101, but not dope the first doping ions 103 into the PMOS region partial fin 101. The first patterning process comprises the following steps: forming a first mask layer 102 on the PMOS area substrate 100; performing first ion implantation on the fin part 101 in the NMOS region by taking the first mask layer 102 as a mask, and doping first doping ions 103 at the bottom of the fin part 101 in part of the NMOS region; after doping first doping ions 103 at the bottom of the PMOS region fin part 101, removing the first mask layer 102; after the first mask layer 102 is removed, the semiconductor device is cleaned by a first cleaning process. Therefore, the first patterning process is used to dope the first dopant ions 103 into the portion of the fin 101 in the NMOS region, which is a complicated process.
Similarly, a second patterning process is performed to dope the second dopant ions 105 into the bottom of the portion of the fin 101 in the PMOS region, but not to dope the second dopant ions 105 into the bottom of the portion of the fin 101 in the NMOS region. The second patterning process is similar to the first patterning process, and thus, the second patterning process has many process steps and a complex process.
In summary, in order to dope the first doping ions 103 at the bottom of the NMOS region part of the fin portion 101 and dope the second doping ions 105 at the bottom of the PMOS region part of the fin portion 101, a first patterning process and a second patterning process are required, so that the method has more process steps and more complex processes.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: the top of the first fin portion is provided with a first mask layer, and a first doping layer is formed on the side wall of the first fin portion before a third fin portion is formed on the top of the second fin portion. Since the side wall of the first fin portion is covered by the first doping layer and the top of the first fin portion is covered by the mask layer, second doping ions can be doped into the third fin portion only through an epitaxial process without the aid of a patterning process, and the second doping ions are not easy to be doped into the first fin portion. The method is beneficial to reducing the complexity of the process.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, where the substrate 200 includes a first region a and a second region B, the first region a has a first fin 201 on the substrate 200, a first mask layer 250 is disposed on a top surface of the first fin 201, and the second region B has a second initial fin 230 on the substrate.
In this embodiment, the steps of forming the substrate 200, the first fin 201 and the second initial fin 230 include: providing an initial substrate, wherein the initial substrate is provided with a first mask layer 250, and the first mask layer 250 exposes a part of the top surface of the initial substrate; and etching the initial substrate by taking the first mask layer 250 as a mask to form a substrate 200, a first fin portion 201 positioned on the substrate 200 of the first region A and a second initial fin portion 230 positioned on the substrate 200 of the second region B.
In this embodiment, the initial substrate is made of silicon, and correspondingly, the base 200, the first fin 201, and the second initial fin 230 are made of silicon. In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator, and accordingly, the materials of the substrate, the first fin portion and the second initial fin portion comprise: germanium, silicon on insulator or germanium on insulator.
The material of the first mask layer 250 includes: silicon nitride or silicon oxynitride.
The first mask layer 250 functions include: in one aspect, the first mask layer 250 is used to form masks for the substrate 200, the first fin 201, and the second initial fin 230; on the other hand, when the first mask layer 250 is used for forming a third fin portion subsequently, the top surface of the first fin portion 201 is protected, the first fin portion 201 is prevented from being contaminated, and improvement of performance of a device in the first region a is facilitated.
In this embodiment, the top surface of the second initial fin 230 also has a first mask layer 250.
In this embodiment, the first region a is used for NMOS transistors and the second region B is used for forming PMOS transistors.
In other embodiments, the first region is for PMOS transistors and the second region is for forming NMOS transistors.
After the first fin 201 and the second initial fin 230 are formed, the method includes: forming a first doping layer on the sidewall of the first fin portion 201; forming an initial isolation layer on the substrate 200, wherein the top of the initial isolation layer exposes the top surface of the first mask layer 250 and covers the first doping layer and the sidewalls of the second initial fin 230; after the initial isolation layer is formed, a portion of the second initial fin 230 is removed to form a second fin, where the initial isolation layer on the second fin has a first opening therein. The steps of forming the first doping layer, the initial isolation layer and the second fin portion refer to fig. 4 to 9.
Referring to fig. 4, a first doped film 202 is formed on the substrate 200, on the sidewalls and the top surface of the second initial fin 230, and on the sidewalls and the top surface of the first fin 201, wherein the first doped film 202 has first doped ions therein.
The conductivity type of the first doped ions is opposite to the conductivity type of the first source/drain ions in the first source/drain doped region formed in the first fin portion 201, so that the first doped ions can prevent the first source/drain doped region from being connected in series, and the short channel effect of the first region a device can be inhibited. The conductivity type of the first source-drain ions is related to the type of the transistor, and therefore, the conductivity type of the first doped ions is related to the conductivity type of the transistor.
In this embodiment, the first region a is used for forming an NMOS transistor, and thus, the first doping ions are P-type ions. In other embodiments, the first region is used to form a PMOS transistor, and thus, the first dopant ions are N-type ions.
The atomic percentage concentration of the first dopant ions in the first doped film 202 is: 5.0E19atoms/cm3～8.0E21atoms/cm3The first doped film 202 is used for forming a first initial doped layer on the sidewalls of the first fin 201 and the second initial fin 230, so that the concentration of the first doped ions in the first doped film 202 determines the concentration of the first doped ions in the first initial doped layer.
In this embodiment, the material of the first doped film 202 is silicon oxide, the first doping ions are boron ions, the forming process of the first doped film 202 is an atomic layer deposition process, and the parameters of the atomic layer deposition process include: the temperature is 80-300 ℃, and the boron source precursor comprises B2H6The flow rate of the boron source precursor is 5-500 standard ml/min, the pressure is 5-20 mTorr, and the cycle time is 5-80 times.
Referring to fig. 5, the substrate 200, the first doped film 202 on the top of the first fin 201 and the second initial fin 230 are removed, and a first initial doped layer 203 is formed on the sidewalls of the first fin 201 and the second initial fin 230.
The process of removing the first doped film 202 on top of the substrate 200, the first fin 201 and the second initial fin 230 includes: one or two of the dry etching process and the wet etching process are combined.
The first doped film 202 on the first fin portion 201 is removed, so that when annealing is performed subsequently, the first doped ions can be effectively prevented from entering the channel of the first region a device and affecting the stability of the first region a device.
The first doped film 202 on the second initial fin 230 is removed, so that the first doped ions can be effectively prevented from entering the channel of the second region B device and affecting the stability of the second region B device during the subsequent annealing process.
The material of the first initially doped layer 203 includes: silicon oxide, the atomic percentage concentration of the first doping ions in the first initial doping layer 203 is determined by the atomic percentage concentration of the first doping ions in the first doping film 202, so that the atomic percentage concentration of the first doping ions in the first initial doping layer 203 is: 5.0E19atoms/cm3～8.0E21atoms/cm3。
In this embodiment, the first region a is used for forming an NMOS transistor, and the first doping ions in the first initial doping layer 203 are P-type ions. In other embodiments, the first region is used to form a PMOS transistor, and the first dopant ions in the first preliminary doped layer are N-type ions.
In this embodiment, the first doping ions are boron ions.
Referring to fig. 6, a stop layer 204 is formed on the sidewall of the first initially doped layer 203.
In this embodiment, the stop layer 204 also covers the top surfaces of the substrate 200, the first fin 201, and the second initial fin 230. In other embodiments, the stop layer covers only the sidewalls of the first initially doped layer.
The material of the stop layer 204 includes: silicon nitride, the forming process of the stop layer 204 includes: a chemical vapor deposition process or an atomic layer deposition process.
The material of the stop layer 204 is different from the material of the first initially doped layer 203, and the stop layer 204 and the first initially doped layer 203 have different etching selectivity ratios. The second region B first initially doped layer 203 is subsequently removed, and the stop layer 204 is used to protect the subsequently formed initial isolation layer.
Referring to fig. 7, a film of isolation material (not shown) is formed on the substrate 200 and the stop layer 204; the isolation material film is planarized until the top surface of the first mask layer 250 is exposed, forming an initial isolation layer 205.
The material of the release material film includes: silicon oxide, the forming process of the isolating material film comprises the following steps: a fluid chemical vapor deposition process, the film of barrier material being used to form the initial barrier layer 205.
The process of planarizing the film of isolation material includes: and (5) carrying out a chemical mechanical polishing process.
In the present embodiment, the process of planarizing the isolation material film further includes removing the stop layer 204 on top of the first fin 201 and the second initial fin 230. In other embodiments, the first fin portion and the second fin portion have no stop layer on top thereof, and thus, the step of planarizing the isolation material film does not include removing the stop layer on top of the first fin portion and the second initial fin portion.
The material of the initial isolation layer 205 includes: silicon oxide.
The role of the initial isolation layer 205 includes: in one aspect, the initial isolation layer 205 is used for the subsequent formation of isolation layers for electrical isolation between different devices of the semiconductor; on the other hand, the initial isolation layer 205 and the first mask layer 250 are used as masks for forming a third fin portion later, and are used for limiting the appearance of the third fin portion.
Referring to fig. 8, after the initial isolation layer 205 is formed, a portion of the second initial fin 230 is removed to form a second fin 231, the second fin 231 has a first opening 232 in the initial isolation layer 205, and a portion of the first initial doping layer 203 is exposed on a sidewall of the first opening 232.
The forming steps of the second fin 231 and the first opening 232 include: forming a first pattern layer (not shown) on the initial isolation layer 205 and the first mask layer 250 of the first region a; the second fin portion 231 and the first opening 232 are formed by using the first pattern layer as a mask.
The first graphics layer comprises: and the first pattern layer is used for protecting the first mask layer 250 and the first fin portion 201 in the first region a, and preventing the first mask layer 250 and the first fin portion 201 in the first region a from being removed when a part of the second initial fin portion 230 is subsequently removed.
Before removing the second initial fin 2230, the method further includes: the first mask layer 250 on top of the second initial fin 230 is removed.
Removing the first mask layer 250 on top of the second initial fin 230 facilitates exposing the top surface of the second initial fin 230, thereby facilitating subsequent removal of a portion of the second initial fin 230 to form the second fin 231 and the first opening 232.
The process of removing the first mask layer 250 on top of the second initial fin 230 includes: one or two of the dry etching process and the wet etching process are combined.
The removal amount of the second preliminary fin 230 is: 500 to 1000 angstroms, the amount of removal of the second initial fin 230 is selected to have a meaning: if the removal of the second initial fin 230 is less than 500 angstroms, then subsequent third fins are not favored; if the removal amount of the second initial fin portion 230 is greater than 1000 angstroms, the thickness of the subsequently formed third fin portion is relatively thick, which increases the process difficulty and complexity.
In this embodiment, the material of the second fin portion 231 is silicon, and in other embodiments, the material of the second fin portion includes: germanium or silicon germanium.
The sidewalls of the first opening 232 expose a portion of the first initial doping layer 203, which is beneficial for removing the first initial doping layer 203 on the sidewalls of the first opening 232.
Referring to fig. 9, after the second fin 231 and the first opening 232 are formed, the first initially doped layer 203 (see fig. 8) on the sidewall of the first opening 232 is removed, and a first doped layer 273 is formed on the sidewall of the first fin 201 and the second fin 231.
The first doping ions in the first initial doping layer 203 cannot block the subsequent second source-drain doping regions from being connected in series, so that the first initial doping layer 203 on the side wall of the first opening 232 is removed, the subsequent formation of the second doping layer is facilitated, the second doping layer is provided with the second doping ions, the second doping ions can inhibit the second source-drain doping regions from being connected in series, the short channel effect of the second region B device is facilitated to be inhibited, the electric leakage is prevented, and the performance of the second region B device is improved.
The process of removing the first initially doped layer 203 at the sidewall of the first opening 232 includes: one or two of the dry etching process and the wet etching process are combined.
In the process of removing the first initially doped layer 203 at the sidewall of the first opening 232, since the material of the first initially doped layer 203 is different from that of the stop layer 204, the first initially doped layer 203 and the stop layer 204 have different etch selectivity, and the stop layer 204 serves as a stop layer for removing the first initially doped layer 203 at the sidewall of the first opening 232, which can prevent the initial isolation layer 205 from being removed.
The material of the first doped layer 273 includes: silicon oxide, the atomic percentage concentration of the first doping ions in the first doping layer 273 is: 5.0E19atoms/cm3～8.0E21atoms/cm3. The conductivity type of the first doped ions is opposite to that of the first source-drain ions in the first source-drain doped region formed subsequently, so that the first doped ions can prevent the first source-drain doped region from being communicated with each other, and the short channel effect of the first region A device can be inhibited.
Referring to fig. 10, with the first mask layer 250 and the initial isolation layer 205 on the sidewall of the first opening 232 as masks, a third fin portion 208 is formed on the second fin portion 231 at the bottom of the first opening 232 by an epitaxial process, wherein the third fin portion 208 has second doping ions therein, and the conductivity type of the second doping ions is opposite to that of the first doping ions; a fourth fin 209 is formed on the third fin 208, and a top of the fourth fin 209 is exposed from a top surface of the initial isolation layer 205.
After forming the first opening 232 and the second fin portion 231, and before forming the third fin portion 208, the method further includes: and removing the first graphic layer.
The process for removing the first graphic layer comprises the following steps: and (5) ashing.
In the present embodiment, in the process of forming the third fin portion 208, the stop layer 204 on the sidewall of the first opening 232 also serves as a mask in addition to the first mask layer 250 and the initial isolation layer 205 on the sidewall of the first opening 232.
In other embodiments, in the process of forming the third fin portion, only the first mask layer and the initial isolation layer on the sidewall of the first opening are used as masks to limit the profile of the third fin portion.
The first openings 232 are used to limit the profile of the third fin 208. The conductivity type of the second doped ions is opposite to the conductivity type of the second source drain ions in a second source drain doped region formed in the fourth fin portion subsequently, so that the second doped ions can prevent the second source drain doped region from being connected in series, and the short channel effect of a device in the second region B can be inhibited. The conductivity type of the second source-drain ions is related to the type of the transistor, so that the conductivity type of the second doped ions is related to the type of the transistor, specifically, the transistor is an NMOS transistor, and the second doping is a P-type ion; the transistor is a PMOS transistor, and the second doped ions are N-type ions.
In this embodiment, the second region B is used to form a PMOS transistor, and thus, the second doping ions are N-type ions. In this embodiment, the second doping ions are phosphorus ions. In other embodiments, the second region is also used to form a PMOS transistor, and the second dopant ions include: arsenic ions.
In this embodiment, the concentration of the second doping ion is: 5.0E19atoms/cm3～5.0E21atoms/cm3The concentration of the second dopant ions is chosen in the sense that: if the concentration of the second doping ions is less than 5.0E19atoms/cm3The blocking capability of the second doped ions to the second source drain ions in the subsequently formed second source drain doped region is not enough, so that the second source drain doped region is easy to be communicated with the second source drain doped region, and the short channel effect of the second region B device is still serious; if the concentration of the second doping ions is more than 5.0E21atoms/cm3And part of the second doping ions are easy to diffuse to the channel region of the device in the second region B, so that the stability of the device is influenced.
In this embodiment, the second region B is used to form a PMOS transistor, and the third fin portion 208 is made of silicon germanium or silicon.
In other embodiments, the second region is used to form an NMOS transistor, and the material of the second doped layer comprises: a compound of group III-V elements or silicon, and a compound of group III-V elements including indium gallium arsenic.
The forming process of the third fin portion 208 includes: and (5) an epitaxial growth process.
In this embodiment, the third fin portion 208 is made of silicon germanium, and the parameters of the epitaxial growth process include: the reaction gas comprises silicon source gas, germanium source gas, hydrogen chloride and hydrogen gas, and the silicon source gas comprises SiH4Or SiH2Cl2The germanium source gas comprises GeH4The flow rates of the silicon source gas, the germanium source gas and the hydrogen chloride gas are all 1-2000 standard ml/min, and the flow rate of the hydrogen gas is 0.1-50 standard liters per minute; the process of doping the third fin portion 208 with the second dopant ions includes: an in-situ doping process; when the second doping ions are phosphorus ions, the parameters of the in-situ doping process comprise: the dopant source comprises a phosphorus source comprising PH3The flow rate of the doping source is 1 standard milliliter per minute to 2000 standard milliliter per minute.
In the process of forming the third fin portion 208, since the sidewall of the first fin portion 201 is covered by the first doping layer 273 and the top of the first fin portion 201 is covered by the first mask layer 250, the second doping ions may be doped into the third fin portion 208 only by using an epitaxial growth process, and the second doping ions are not easily doped into the first fin portion 201. Therefore, the second doping ions can inhibit the short channel effect of the second region B device, and cannot affect the performance of the first region A device.
The material of the fourth fin 209 includes: silicon germanium. The forming process of the fourth fin portion 209 includes: and (5) an epitaxial growth process.
The first openings 232 (see fig. 9) also serve to limit the topography of the fourth fins 209 during the formation of the fourth fins 209.
Referring to fig. 11, a portion of the initial isolation layer 205 (see fig. 10) is removed, and an isolation layer 233 is formed, wherein a top surface of the isolation layer 233 is lower than top surfaces of the fourth fin 209 and the first fin 201, and a top surface of the isolation layer 205 is higher than or flush with a top surface of the third fin 208; after the isolation layer 233 is formed, the stop layer 204 exposed from the sidewalls of the first fin 201 and the fourth fin 209 is removed; after removing the stop layer 204 exposed on the sidewalls of the first fin 201 and the fourth fin 209, removing the first doping layer 273 exposed on the sidewall of the first fin 201; after removing the first doping layer 273 exposed from the sidewall of the first fin 201, an annealing process is performed to make the first doping ions enter the first fin 201.
During the formation of the isolation layer 233, the first mask layer 250 on top of the first fin 201 is also removed.
The process of removing a portion of the initial isolation layer 205 includes: one or two of the dry etching process and the wet etching process are combined.
The isolation layer 233 is used to electrically isolate different devices of the semiconductor.
The top surface of the isolation layer 233 is lower than the top surface of the fourth fin portion 209, and the top surface of the isolation layer 233 is higher than or flush with the top surface of the third fin portion 208, so that a subsequently formed second gate structure spanning the fourth fin portion 209, the third fin portion 208 and the second fin portion 230 covers a portion of the fourth fin portion 209, does not cover the third fin portion 208, and is located below a channel region of the second gate structure. The second doped ions are opposite to the conduction type of the second source drain ions in the subsequently formed second source drain doped region, and the second doped ions can prevent the second source drain doped region from being communicated with each other, so that the short channel effect of a device B in the second region can be inhibited, and electric leakage can be prevented.
The process of removing the stop layer 204 exposed by the first fin 201 and the fourth fin 209 includes: one or two of the dry etching process and the wet etching process are combined.
Removing the stop layer 204 on the sidewall of the first fin 201 is beneficial to exposing the first doping layer 273 on the sidewall of the first fin 201, and further beneficial to subsequently removing the first doping layer 273 exposed on the sidewall of the first fin 201, so that the subsequently formed first gate structure crossing the first fin 201 covers part of the sidewall and the top surface of the first fin 201, but does not cover the first doping layer 273. And the remaining first doping layer 273 is located on the sidewall of the first fin 201 under the first gate structure. And subsequently, the first doping ions are diffused to the lower part of the channel region of the first grid structure through annealing treatment. The conductivity type of the first doped ions is opposite to that of the subsequently formed first source-drain ions, so that the first doped ions can prevent the first source-drain doped region from being communicated with each other, and the short channel effect of the first region A device can be inhibited.
The annealing treatment process comprises the following steps: spike annealing process or laser annealing process; the parameters of the spike annealing process include: the temperature is 900 ℃ to 1050 ℃.
The annealing process causes first dopant ions to enter the bottom of the first fin 201, and specifically, the first dopant ions are located in the first fin 201 below a subsequently formed channel region of a first gate structure that spans the first fin 201. The first doped ions have opposite conductivity types with the subsequently formed first doped ions, so that the first doped ions can prevent the first source-drain doped region from being communicated with each other, thereby being beneficial to inhibiting the short channel effect of the first region A device and preventing electric leakage.
Referring to fig. 12-14, fig. 13 is a cross-sectional view taken along line C-C1 of fig. 12, and fig. 14 is a cross-sectional view taken along line D-D1 of fig. 12, illustrating formation of a first gate structure 255 of the first fin 201; a second gate structure 235 is formed across the second, third and fourth fins 231, 208, 209.
The first gate structure 255 includes: a first gate dielectric layer (not shown) and a first gate layer (not shown) over the first gate dielectric layer.
The material of the first gate dielectric layer comprises: silicon oxide, the material of the first gate layer comprising: silicon.
The second gate structure 235 includes: a second gate dielectric layer (not shown) and a first gate layer (not shown) on the second gate dielectric layer.
The material of the second gate dielectric layer comprises: silicon oxide, the material of the second gate layer comprising: silicon.
Referring to fig. 15, first source-drain doped regions 236 are formed in the first fin portion 201 on two sides of the first gate structure 255, and first source-drain ions are provided in the first source-drain doped regions 236, and the conductivity type of the first source-drain ions is opposite to the conductivity type of the first doped ions.
Fig. 15 is a schematic configuration diagram based on fig. 13.
The forming step of the first source-drain doped region 236 includes: forming first source-drain openings in the first fin portions 201 on two sides of the first gate structure 255; forming a first epitaxial layer in the first source drain opening; and doping first source-drain ions into the first epitaxial layer.
The forming process of the first source drain opening comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The material of the first epitaxial layer and the conductivity type of the first source-drain ions are related to the type of the transistor. In this embodiment, the first region a is used to form an NMOS transistor, and therefore, the material of the first epitaxial layer includes: silicon carbide or silicon, and specifically, the material of the first epitaxial layer is germanium carbide. Silicon carbide can provide tensile stress to the channel of the NMOS transistor formed, thereby increasing the mobility rate of carriers in the channel of the NMOS transistor. The first source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions. Correspondingly, the first doping ions are P-type ions, such as: boron ions.
In other embodiments, the first region is used to form a PMOS transistor, and thus, the material of the first epitaxial layer includes: silicon germanium or silicon. The first source-drain ions are P-type ions, such as: boron ions. Correspondingly, the first doping ions are N-type ions, such as: phosphorus ions or arsenic ions.
The conductivity type of the first doped ions is opposite to that of the first source-drain ions, and the first doped ions can block the first source-drain doped region 236 from being connected in series, so that the short channel effect of the first region a device can be inhibited, and electric leakage can be prevented.
Referring to fig. 16, a second source/drain doped region 237 is formed in the fourth fin portion 209 at two sides of the second gate structure 235, the second source/drain doped region 237 has second source/drain ions therein, and the conductivity type of the second source/drain ions is opposite to the conductivity type of the second doped ions.
Fig. 16 is a schematic configuration diagram based on fig. 14.
The forming step of the second source/drain doped region 237 is the same as the forming step of the first source/drain doped region 236, and is not described herein again.
In this embodiment, the second region B is used for forming a PMOS transistor, and therefore, the material of the second epitaxial layer includes: silicon germanium or silicon, and particularly, the material of the second epitaxial layer is silicon germanium. The silicon germanium can provide compressive stress to the channel of the PMOS transistor formed, thereby improving the channel carrier mobility rate. The second source-drain ions are P-type ions, such as: boron ions. Correspondingly, the second doping ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the second region is used to form an NMOS transistor, and thus, the material of the second epitaxial layer includes: silicon carbide or silicon. The second source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions. Correspondingly, the second doping ions are P-type ions, such as: boron ions.
The second doped ions have opposite conductivity types to the second source/drain ions, and the second doped ions can block the second source/drain doped regions 237 from being connected in series, thereby being beneficial to inhibiting the short channel effect of the second region B device and preventing electric leakage.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, with continued reference to fig. 11, including:
a substrate 200, wherein the substrate 200 includes a first region a and a second region B, the first region a has a first fin 201 on the substrate 200, the first fin 201 has first doped ions therein, and a first mask layer 250 is disposed on a top of the first fin 201 (see fig. 10);
a first doping layer 253 located on a partial sidewall of the first fin 201;
a second fin portion 231 located on the substrate 200 in the second region B, the second fin portion 231 having a third fin portion 208 and a fourth fin portion 209 located on the third fin portion 208, the third fin portion 208 having a second doped ion therein, the second doped ion having a conductivity type opposite to that of the first doped ion;
an isolation layer 233 is located on the substrate 200, a top of the isolation layer 233 is lower than top surfaces of the first fin 201 and the fourth fin 209, and a top surface of the isolation layer 233 is higher than or flush with top surfaces of the first doping layer 253 and the third fin 208.
The material of the first doping layer 253 includes: silicon oxide; the atomic percentage concentration of the first dopant ions in the first fin portion 201 is: 5.0E19atoms/cm3～8.0E21atoms/cm3。
The atomic percentage concentration of the second dopant ions in the third fin portion 208 is: 5.0E19atoms/cm3～5.0E21atoms/cm3。
The first area A is used for forming an NMOS transistor, and the second area A is used for forming a PMOS transistor; the first doped ions are P-type ions, and the second doped ions are N-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions. The material of the third fin 208 includes silicon germanium or silicon.
The first area A is used for forming PMOS transistors, and the second area B is used for forming NMOS transistors; the conductivity type of the first doped ions is N-type ions, and the conductivity type of the second doped ions is P-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions. The material of the third fin portion 208 includes a compound composed of a group iii-v element or silicon; the compound composed of III-V group elements comprises indium gallium arsenic;
the material of the first mask layer 250 includes silicon nitride or silicon oxynitride.
The semiconductor structure further includes: a first gate structure spanning the first fin 201; the first source-drain doped regions are positioned in the first fin portions 201 on two sides of the first gate structure, first source-drain ions are arranged in the first source-drain doped regions, and the conductivity types of the first source-drain ions and the first doped ions are opposite; a second gate structure spanning the second fin 231, the third fin 208, and the fourth fin 209; and second source-drain doped regions located in the fourth fin portions 209 on two sides of the second gate structure, wherein the second source-drain doped regions have second source-drain ions, and the conductivity types of the second source-drain ions and the second doped ions are opposite.
The first doped ions and the first source drain ions have opposite conduction types, so that the first doped ions can prevent the first source drain doped regions from being communicated with each other, the short channel effect of the first region A device can be inhibited, and electric leakage can be prevented.
The second doped ions have opposite conductivity types to the second source-drain ions, so that the second doped ions can prevent the second source-drain doped regions from being communicated with each other, thereby being beneficial to inhibiting the short channel effect of the second region B device and preventing electric leakage.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the first area is provided with a first fin part on the substrate, the top surface of the first fin part is provided with a first mask layer, and the second area is provided with a second initial fin part on the substrate;
forming a first initial doping layer on the side walls of the first fin part and the second initial fin part, wherein the first initial doping layer is internally provided with first doping ions;
forming an initial isolation layer on the substrate, the first fin part and the second initial fin part and on the side wall of the first initial doping layer, wherein the initial isolation layer exposes the top surface of the first mask layer and covers the side walls of the first initial doping layer and the second initial fin part;
after the initial isolation layer is formed, removing part of the second initial fin part to form a second fin part, wherein the initial isolation layer on the second fin part is internally provided with a first opening;
removing the first initial doping layer on the side wall of the first opening, and forming a first doping layer on the side walls of the first fin portion and the second fin portion;
forming a third fin part on the second fin part by using the first mask layer and the initial isolation layer on the side wall of the first opening as masks and adopting an epitaxial process, wherein the third fin part is provided with second doped ions, and the conductivity type of the second doped ions is opposite to that of the first doped ions;
forming a fourth fin portion on the third fin portion, wherein the top surface of the fourth fin portion is exposed out of the top surface of the initial isolation layer;
removing part of the initial isolation layer to form an isolation layer, wherein the top surface of the isolation layer is lower than the top surface of the first fin portion and lower than the top surface of the fourth fin portion, and the top surface of the isolation layer is higher than or flush with the top surface of the third fin portion;
after the isolation layer is formed, removing the first doping layer exposed out of the side wall of the first fin part;
and after the first doping layer exposed on the side wall of the first fin part is removed, annealing treatment is carried out, so that the first doping ions enter the first fin part.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the first doped layer comprises: silicon oxide; the concentration of the first doping ions in the first doping layer is as follows: 5.0E19atoms/cm3~8.0E21atoms/cm3。
3. The method of forming a semiconductor structure of claim 1, wherein after forming the first initial doping layer and before forming the initial isolation layer, the method further comprises: forming a stop layer on the surface of the side wall of the first initial doping layer; the material of the stop layer comprises: silicon nitride.
4. The method of claim 1, wherein a concentration of the second dopant ions in the third fin portion is: 5.0E19atoms/cm3~5.0E21atoms/cm3。
5. The method of forming a semiconductor structure of claim 1, wherein the first region is used to form an NMOS transistor and the second region is used to form a PMOS transistor; the first doped ions are P-type ions, and the second doped ions are N-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.
6. The method of claim 5, wherein a material of the third fin comprises silicon germanium or silicon; the forming process of the third fin part comprises an epitaxial growth process; when the third fin portion is made of silicon germanium, the parameters of the epitaxial growth process include: a silicon source gas comprising SiH, a germanium source gas, hydrogen chloride and hydrogen4Or SiH2Cl2The germanium source gas comprises GeH4The flow rates of the silicon source gas, the germanium source gas and the hydrogen chloride gas are all 1-2000 standard milliliters/minute, and the flow rate of the hydrogen gas is 0.1-50 standard liters per minute; the process for doping the second doping ions in the third fin portion comprises an in-situ doping process; when the second doping ions are phosphorus ions, the parameters of the in-situ doping process include: the dopant source comprises a phosphorus source comprising PH3The flow rate of the doping source is 1 standard milliliter per minute to 2000 standard milliliters per minute.
7. The method of forming a semiconductor structure of claim 1, wherein the first region is used to form a PMOS transistor and the second region is used to form an NMOS transistor; the first doped ions are N-type ions, and the second doped ions are P-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.
8. The method of claim 7, wherein a material of the third fin portion comprises a compound of a group III-V element or silicon; the compound of III-V group elements comprises indium gallium arsenic.
9. The method of forming a semiconductor structure of claim 1, wherein the annealing process comprises: spike annealing process or laser annealing process; the parameters of the spike annealing process include: the temperature is 900-1050 ℃.
10. The method of claim 1, wherein the material of the first mask layer comprises silicon nitride or silicon oxynitride.
11. The method of forming a semiconductor structure of claim 1, wherein after forming the isolation layer, the method of forming further comprises: forming a first gate structure crossing the first fin portion; forming first source-drain doped regions in the first fin portions on two sides of the first gate structure respectively, wherein the first source-drain doped regions are internally provided with first source-drain ions, and the conductivity type of the first source-drain ions is opposite to that of the first doped ions; forming a second gate structure crossing the second fin portion, the third fin portion and the fourth fin portion; and forming second source-drain doped regions in the fourth fin parts on two sides of the second gate structure respectively, wherein second source-drain ions are arranged in the second source-drain doped regions, and the conductivity type of the second source-drain ions is opposite to that of the second doped ions.
12. A semiconductor structure, comprising:
the substrate comprises a first area and a second area, wherein the first area is provided with a first fin part on the substrate, and the bottom of the first fin part is provided with first doped ions;
the second fin portion is located on the second region substrate, the first doping layer is located on the bottom side wall of the first fin portion and the side wall of the second fin portion, a third fin portion and a fourth fin portion located on the third fin portion are arranged on the second fin portion and a part of the first doping layer on the side wall of the second fin portion, second doping ions are arranged in the third fin portion, and the conductivity type of the second doping ions is opposite to that of the first doping ions;
the top of the isolation layer is lower than the top surface of the first fin portion and lower than the top surface of the fourth fin portion, and the top surface of the isolation layer is higher than or flush with the top surface of the first doping layer and higher than or flush with the top surface of the third fin portion.
13. The semiconductor structure of claim 12, wherein the material of the first doped layer comprises: silicon oxide; the concentration of the first doping ions in the first fin part is as follows: 5.0E19atoms/cm3~8.0E21atoms/cm3。
14. The semiconductor structure of claim 12, wherein said trench comprises a polysilicon layerThe concentration of the second doping ions in the third fin part is as follows: 5.0E19atoms/cm3~5.0E21atoms/cm3。
15. The semiconductor structure of claim 12, wherein the first region is used to form an NMOS transistor and the second region is used to form a PMOS transistor; the first doped ions are P-type ions, and the second doped ions are N-type ions; the N-type ions comprise phosphorus ions or arsenic ions, and the P-type ions comprise boron ions or indium ions; the material of the third fin portion comprises silicon germanium or silicon.
16. The semiconductor structure of claim 12, wherein the first region is used to form a PMOS transistor and the second region is used to form an NMOS transistor; the first doped ions are N-type ions, and the second doped ions are P-type ions; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.
17. The semiconductor structure of claim 16, wherein a material of the third fin comprises a compound of a group iii-v element or silicon; the compound of III-V group elements comprises indium gallium arsenic.
18. The semiconductor structure of claim 12, further comprising: a first gate structure crossing the first fin portion; the first source-drain doped regions are respectively positioned in the first fin parts on two sides of the first grid structure, first source-drain ions are arranged in the first source-drain doped regions, and the conductivity types of the first source-drain ions and the first doped ions are opposite; a second gate structure spanning the second fin portion, the third fin portion and the fourth fin portion; and the second source-drain doped regions are respectively positioned in the fourth fin parts at two sides of the second grid structure, second source-drain ions are arranged in the second source-drain doped regions, and the conductivity types of the second source-drain ions and the second doped ions are opposite.
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