CN109786270B - Packaging device and manufacturing method thereof - Google Patents
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- CN109786270B CN109786270B CN201811504669.9A CN201811504669A CN109786270B CN 109786270 B CN109786270 B CN 109786270B CN 201811504669 A CN201811504669 A CN 201811504669A CN 109786270 B CN109786270 B CN 109786270B
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Abstract
The invention provides a manufacturing method of a packaged device, which comprises the following steps: providing a device chip to be packaged, wherein the device chip to be packaged comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area; depositing a filling layer covering the functional area above the functional area; depositing and forming a first sealing layer covering the device chip to be packaged and the filling layer on the device chip to be packaged; forming a plurality of through holes on the first sealing layer to expose the filling layer, and removing the filling layer through the plurality of through holes; and depositing a second sealing layer on the first sealing layer to seal the through holes to form the packaged device. Correspondingly, the invention further provides a packaging device. The implementation of the invention is beneficial to simplifying the packaging process flow, reducing the production cost and improving the packaging efficiency.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging device and a manufacturing method thereof.
Background
In the prior art, in order to prevent external adverse factors from affecting a device chip (such as an FBAR device chip, etc.), the device chip is generally protected by a package. The packaging based on the bonding process is one of the most widely used device chip packaging methods at present, and the specific implementation method is to tightly combine the device chip to be packaged and the cap wafer by a physical method or a chemical method. The disadvantages of this packaging approach are:
(1) the bonding process has strict requirements on surface cleanliness, surface roughness and the like of the device chip and the cap wafer, but many device chips (such as FBAR device chips and the like) are difficult to provide effective cleaning treatment for the surface of the device chip due to the limitation of materials, so that the bonding difficulty is increased. In addition, the repeatability of the bonding process is difficult to ensure, and the detection means after bonding is rare. Overall, the control difficulty of the bonding process is high.
(2) The bonding process requires the use of a capping wafer to package the device chips, wherein the use of the capping wafer results in increased packaging costs.
(3) Since the bonding process is basically a single-chip operation, the packaging efficiency is low, and the productivity is low.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a packaged device, the method comprising:
providing a device chip to be packaged, wherein the device chip to be packaged comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area;
depositing a filling layer covering the functional area above the functional area;
depositing and forming a first sealing layer covering the device chip to be packaged and the filling layer on the device chip to be packaged;
forming a plurality of through holes on the first sealing layer to expose the filling layer, and removing the filling layer through the plurality of through holes;
and depositing a second sealing layer on the first sealing layer to seal the through holes to form the packaged device.
According to one aspect of the present invention, in the manufacturing method, the functional region includes a first cavity disposed on the substrate, and a lower electrode layer, a piezoelectric layer, and an upper electrode layer disposed on the cavity in this order from bottom to top; or the functional area comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the substrate from bottom to top.
According to another aspect of the present invention, in the manufacturing method, in a case where the functional region includes a first cavity, a lower electrode layer, a piezoelectric layer, and an upper electrode layer, the cavity is filled with a sacrificial layer.
According to still another aspect of the present invention, in the manufacturing method, the step of depositing a filling layer covering the functional region over the functional region includes: depositing a covering layer covering the substrate, the functional area, the metal contact point and the sealing ring on the device chip to be packaged; forming a first photoresist layer on the covering layer, and performing patterning operation on the first photoresist layer to only reserve a part above the functional region; removing the part, which is not covered by the first photoresist layer, of the covering layer in an etching mode so as to form a filling layer covering the functional region above the functional region; and removing the first photoresist layer.
According to yet another aspect of the present invention, in the method of manufacturing, the cap layer is formed by PECVD deposition at a temperature in the range of 200 ℃ to 400 ℃.
According to still another aspect of the present invention, in the manufacturing method, a material of the cover layer is phosphosilicate glass or undoped silicate glass.
According to another aspect of the present invention, in the manufacturing method, in a case where the functional region includes a cavity, a lower electrode layer, a piezoelectric layer, and an upper electrode layer, and the cavity is filled with a sacrificial layer, a material of the cover layer is the same as a material of the sacrificial layer.
According to still another aspect of the present invention, in the manufacturing method, the thickness of the filling layer is more than 3 μm.
According to still another aspect of the present invention, in the manufacturing method, the plurality of through holes are uniformly distributed over the filling layer.
According to yet another aspect of the present invention, in the manufacturing method, an aspect ratio of the through-hole is greater than 3: 1.
According to still another aspect of the present invention, in the manufacturing method, a ratio between a sum of open area of the plurality of through holes and an area of an upper surface of the filling layer ranges from 20% to 80%.
According to still another aspect of the present invention, before forming the packaged device after removing the filling layer through the plurality of through holes and after depositing a second sealing layer on the first sealing layer to seal the plurality of through holes, the manufacturing method further includes: and heating the device chip to be packaged to release gas in the device chip to be packaged.
According to a further aspect of the invention, the material of the first sealing layer is α -Si, formed by PECVD deposition at a deposition temperature in the range of 200 ℃ to 400 ℃, a deposition pressure of less than 1Torr, a stress requirement of less than 100MPa and a thickness of more than 3 μm, and/or the material of the second sealing layer is α -Si, formed by PECVD deposition at a deposition temperature in the range of 200 ℃ to 400 ℃, a deposition pressure of less than 1Torr, a stress requirement of less than 100MPa and a thickness in the range of 2 μm to 10 μm.
The present invention also provides a packaged device, comprising:
the device chip comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area;
a first sealing layer disposed on the device chip and having a plurality of via holes at a portion located above the functional region;
a second sealing layer disposed on the first sealing layer, filling the plurality of through holes;
the device chip, the first sealing layer and the second sealing layer form a closed second cavity above the functional region.
According to one aspect of the invention, in the packaged device, the functional region comprises a first cavity arranged on the substrate, and a lower electrode layer, a piezoelectric layer and an upper electrode layer which are arranged on the cavity in sequence from bottom to top; or the functional area comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the substrate from bottom to top.
According to one aspect of the invention, in the packaged device, the depth of the second cavity is greater than 3 μm.
According to an aspect of the invention, in the packaged device, the plurality of through holes are uniformly distributed over the functional region.
According to one aspect of the invention, the packaged device has an aspect ratio of the via greater than 3: 1.
According to one aspect of the invention, in the packaged device, the ratio of the sum of the open area of the plurality of through holes to the area of the upper surface of the second cavity is in the range of 20% to 80%
According to one aspect of the invention, the material of the first encapsulant layer is α -Si with a stress requirement of less than 100MPa and a thickness of greater than 3 μm, and/or the material of the second encapsulant layer is α -Si with a stress requirement of less than 100MPa and a thickness in the range of 2 μm to 10 μm.
The manufacturing method of the packaging device provided by the invention realizes the packaging of the device chip through the existing deposition process. On one hand, the deposition process is simple to operate and has smaller process control difficulty, and the bonding process is complex to operate and has larger process control difficulty, so that compared with the mode of realizing packaging through the bonding process in the prior art, the implementation of the method can effectively simplify the packaging process flow and reduce the control difficulty of the packaging process; on the other hand, the deposition process avoids using a cap sealing wafer like a bonding process, so compared with the mode of realizing packaging through the bonding process in the prior art, the method can greatly reduce the packaging cost; in another aspect, the deposition process can be performed on a plurality of wafers, and the bonding process is performed on a single wafer, so that compared with the prior art in which the packaging is performed by the bonding process, the present invention can effectively improve the packaging efficiency and thus the productivity. Accordingly, the packaging device provided by the invention has the characteristics of simple manufacturing process, low cost and high productivity.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a flow chart of a method of manufacturing a packaged device according to an embodiment of the present invention;
FIGS. 2(a) through 2(k), 2(m), and 2(n) are schematic cross-sectional views of stages in the manufacture of a packaged device according to the flow shown in FIG. 1;
fig. 2(l) is a schematic top view of the structure shown in fig. 2 (k).
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
For a better understanding and explanation of the present invention, reference will now be made in detail to the present invention as illustrated in the accompanying drawings.
The invention provides a method for manufacturing a packaged device. Referring to fig. 1, fig. 1 is a flow chart illustrating a method for manufacturing a packaged device according to an embodiment of the invention. As shown, the manufacturing method includes:
in step S100, providing a device chip to be packaged, where the device chip to be packaged includes a substrate, a functional region on the substrate, and a metal contact and a sealing ring on the substrate and surrounding the functional region;
in step S101, depositing a filling layer covering the functional region above the functional region;
in step S102, depositing and forming a first sealing layer covering the device chip to be packaged and the filling layer on the device chip to be packaged;
forming a plurality of through holes on the first sealing layer to expose the filling layer, and removing the filling layer through the plurality of through holes in step S103;
in step S104, depositing a second sealing layer on the first sealing layer to seal the plurality of through holes, thereby forming the packaged device.
Next, the above steps S100 to S104 will be described in detail.
Specifically, in step S100, a device chip to be packaged is provided. It should be noted that all the device chips packaged by the bonding process in the prior art are suitable for the manufacturing method provided by the present invention, for example, cavity type FBAR (film Bulk Acoustic resonator) device chips (including air cavity type FBAR filter, FBAR duplexer, FBAR sensor, etc.), bragg reflection layer type FBAR device chips (including lagrange reflection layer type FBAR filter, FBAR duplexer, FBAR sensor, etc.), etc. It will be appreciated by those skilled in the art that for the sake of brevity, a list of all device chips suitable for use with the present invention is not provided herein.
In the embodiment, the device chip to be packaged comprises a substrate, a functional region, a metal contact point and a sealing ring. The substrate is usually made of a semiconductor material such as silicon or germanium. The functional region is disposed on the substrate and is a portion for realizing the function of the device chip. The FBAR device chip of the air cavity type and the FBAR device chip of the bragg reflector type are still exemplified for explanation. The functional areas of the air cavity type FBAR device chip and the Bragg reflection layer type FBAR device chip are used for realizing conversion of electric energy-sound energy-electric energy, wherein the functional areas of the air cavity type FBAR device chip comprise a cavity arranged on a substrate, and a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the cavity from bottom to top. The functional region of the Bragg reflection layer type FBAR device chip comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on a substrate from bottom to top. It will be understood by those skilled in the art that the FBAR device chip of the air cavity type and the FBAR device chip of the bragg reflector type are only schematic examples, and for the sake of brevity, the functional region structures of other device chips suitable for the present invention will not be described one by one. The metal contact and the sealing ring are disposed on the substrate in a manner surrounding the functional region. The arrangement modes of the metal contact point and the sealing ring comprise two modes, one mode is that the metal contact point is arranged on the outer side of the functional area and surrounds the functional area, and the sealing ring is arranged on the outer side of the metal contact point and surrounds the metal contact point and the functional area; another way is that the sealing ring is arranged outside the functional area, forming a surround for the functional area, and the metal contact point is arranged outside the sealing ring, forming a surround for the sealing ring and the functional area. Among them, the metal contact is preferably implemented using a metal material such as gold (Au), aluminum (Al), copper (Cu), nickel (Ni), high temperature tin-lead alloy, and the seal ring is preferably implemented using a metal material such as copper (Cu), gold (Au).
Hereinafter, the following steps will be described by taking the FBAR device chip of the air cavity type as an example in conjunction with fig. 2(a) to 2 (n). As shown in fig. 2(a), the FBAR device of the air cavity type includes a substrate 100, a stacked structure 101 on the substrate 100, a metal contact 103 surrounding the stacked structure 101, and a seal ring 104 surrounding the metal contact 103. The stacked structure 101 includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer from bottom to top, and the lower electrode layer, the piezoelectric layer, and the upper electrode layer are not distinguished in the figure, but are represented as a whole by the stacked structure 101. A cavity (hereinafter, referred to as a first cavity) is disposed between the stacked structure 101 and the substrate 100, and the stacked structure 101 and the first cavity constitute a functional region of the air cavity type FBAR device chip. In this embodiment, the first cavity is filled with a sacrificial layer 105. It will be appreciated by those skilled in the art that in other embodiments, the first cavity may not be filled with any material. Further, the stacked-layer structure 101 is provided with a through-hole (hereinafter referred to as a first through-hole) 102, and the sacrificial layer 105 can be removed through the first through-hole 102.
In step S101, a filling layer covering the functional region is deposited and formed over the functional region. In this embodiment, the filling layer is formed as follows: first, as shown in fig. 2(b), a cover material is deposited on the device chip to be packaged and planarized to form a cover layer 106 covering the substrate 100, the functional region, the metal contact point 103, and the seal ring 104. The capping layer 106 is preferably deposited by low temperature PECVD (plasma Enhanced Chemical Vapor deposition) at a temperature in the range of 200 ℃ to 400 ℃, wherein the low temperature PECVD deposition is beneficial to reduce the impact on device performance. The material of the cap layer 106 includes, but is not limited to, phosphosilicate glass, undoped silicate glass. Preferably, the material of the capping layer 106 is the same as the material of the sacrificial layer 105. More preferably, the portion of the capping layer 106 over the functional region has a thickness greater than 3 μm. Next, a first photoresist layer 107 is formed on the capping layer as shown in fig. 2(c), and patterning of the first photoresist layer 107 is performed to leave only a portion above the functional region as shown in fig. 2 (d). That is, the first photoresist layer 107 after the patterning operation covers only the portion of the covering layer 106 above the functional region of the chip to be packaged. Of these, positive photoresist is preferably used for the first photoresist layer 107. In addition, the thickness of the first photoresist layer 107 ranges from 3 μm to 10 μm. Then, as shown in fig. 2(e), the portion of the capping layer 106 not covered by the first photoresist layer 107 is removed by etching to form a filling layer 108 over the functional region. In order to ensure that a good profile is formed, in this embodiment, a dry etching method is used to remove a portion of the capping layer 106 that is not covered by the first photoresist layer 107. The thickness of the fill layer 108 (shown as L)1Represented) is the thickness of the portion of the cap layer 106 over the functional region. Furthermore, if the material of the metal contact 103 is gold, the selection ratio between the dry-etched cap layer 106 and the metal contact 103 is set to be greater than 20: 1. Finally, as shown in fig. 2(f), the first photoresist layer 107 is removed. Preferably, the first photoresist layer 107 may be removed by a multi-step photoresist removal process to ensure sufficient photoresist removal.
In step S102, as shown in fig. 2(g), a sealing material is deposited on the device chip to be packaged and planarized to form the first sealing layer 109 covering the device chip to be packaged and the filling layer 108. in the present embodiment, the first sealing layer 109 is preferably deposited by using a low temperature PECVD method, the deposition temperature ranges from 200 ℃ to 400 ℃, the deposition pressure is less than 1Torr, and the stress requirement is less than 100 mpa. the material of the first sealing layer 109 includes, but is not limited to, α -Si., and preferably, the thickness of the portion of the first sealing layer 109 above the filling layer 108 is greater than 3 μm.
In step S103, first, as shown in fig. 2(h), a second photoresist layer 110 is formed on the first sealing layer 109. Next, as shown in fig. 2(i), the second photoresist layer 110 is patterned to expose a portion of the first sealing layer 109 above the filling layer 108, wherein the exposed portion of the first sealing layer 109 is in the shape of a plurality of holes. The second photoresist layer 110 is preferably a positive photoresist. In addition, the thickness of the second photoresist layer 110 ranges from 3 μm to 10 μm. Then, as shown in fig. 2(j), the portions of the first sealing layer 109 not covered by the second photoresist layer 110 are removed by etching to form a plurality of through holes 112 (hereinafter referred to as second through holes) penetrating through the second photoresist layer 110 above the filling regions 108. In order to ensure that a good profile is formed, in this embodiment, the first sealing layer 109 is etched by using a dry etching method, wherein a selection ratio between the etched first sealing layer 109 and the filling layer 108 is set to be greater than 2: 1. Next, as shown in fig. 2(k), the second photoresist layer 110 is removed. Preferably, the second photoresist layer 110 may be removed by a multi-step photoresist removal to ensure sufficient photoresist removal. Finally, as shown in fig. 2(m), the filling layer 108 and the sacrificial layer 105 are removed through the second via 112, so that the first cavity 113 between the stacked structure 101 and the substrate 100 is released, and a second cavity 114 is formed between the stacked structure 101 and the first sealing layer 109. In the case that the material of the sacrificial layer 105 and the filling layer 108 is phosphosilicate glass, the material can be removed by hydrofluoric acid etching, wherein the concentration range of hydrofluoric acid is 5% to 10%, the etching time is longer than 1 hour, and after the etching is finished, isopropyl alcohol (IPA) is used for dehydration and drying. In the case where the material of the sacrificial layer 105 and the filling layer 108 is undoped silicate glass, hydrogen fluoride etching may be used for removal. It should be noted that, if the materials of the sacrificial layer 105 and the filling layer 108 are the same, the filling layer 108 and the sacrificial layer 105 can be removed at one time without being separately removed twice, so that the packaging steps are effectively reduced, and the packaging process is further effectively simplified.
Referring to fig. 2(l), fig. 2(l) is a schematic top view of the structure shown in fig. 2 (k). As shown in fig. 2(l), in the present embodiment, the opening shape of the second through hole 112 is circular. It will be understood by those skilled in the art that the opening shape of the second through hole 112 is not limited in any way, and in other embodiments, the opening shape of the second through hole 112 may be triangular, rectangular, etc. It should be noted that in the present embodiment, the opening shapes of all the second through holes 112 are the same, and in other embodiments, the opening shapes of the second through holes 112 may also be different. In the present embodiment, the plurality of second through holes 112 are uniformly distributed over the filling layer 108, wherein the uniform distribution of the second through holes 112 is more favorable for well removing the filling layer 108 and the sacrificial layer 105. It will be appreciated by those skilled in the art that in other embodiments, the plurality of second through holes 112 may be distributed non-uniformly or randomly over the filling layer 108. In addition, the aspect ratio of the second through hole 112 is preferably greater than 3:1, so that the performance of the device chip is not affected by the sealing material entering the second cavity 114 due to the small aspect ratio when the second through hole 112 is sealed later. It should be noted here that the aspect ratio of the through hole is defined as the ratio between the depth of the through hole and the width of the through hole. For the second through hole 112 being circular, the aspect ratio refers to the ratio between the depth of the second through hole 112 (i.e. the thickness of the portion of the first sealing layer 109 above the filling layer 108) and the diameter of the second through hole 112. Moreover, the second through holes 112 need to have a certain opening density, which may otherwise affect the removal efficiency of the filling layer 108 and the sacrificial layer 105, in the present embodiment, the ratio between the sum of the opening areas of the plurality of second through holes 112 and the upper surface area of the filling layer 108 is set to be in a range of 20% to 80%, for example, 20%, 30%, 40%, 50%, 60%, 70%, 80%, etc.
In step S104, as shown in fig. 2(n), a sealing material is deposited on the first sealing layer 109 and planarized to form a second sealing layer 115 covering the first sealing layer 109, wherein the second sealing layer 115 is filled into the second through hole 112 to seal the second through hole 112, so that the first cavity 113 and the second cavity 114 form a closed cavity, and thus the packaged device is completed.
Preferably, after removing the filling layer 108 through the plurality of second through holes 112 and before forming the packaged device after depositing the second sealing layer 113 on the first sealing layer 109 to seal the plurality of second through holes 112, the method for manufacturing the packaged device further includes: the device chip to be packaged is subjected to a heating process to release gas inside the device chip to be packaged, that is, to release residual gas (such as water vapor, process gas used for etching the filling layer 108 and the sacrificial layer 105, and the like) in the first cavity 113 and the second cavity 114, so as to avoid the residual gas from affecting the performance of the device chip.
According to the manufacturing method of the packaging device, the filling layer is formed above the chip functional area of the device to be packaged, the first sealing layer is deposited on the device to be packaged to cover the device to be packaged, the through hole is formed in the first sealing layer, the filling layer is removed through the through hole, and the second sealing layer is deposited on the first sealing layer to seal the through hole, so that the packaging device is formed. On one hand, the manufacturing method provided by the invention mainly uses a deposition mode for packaging, and as the deposition process is simple to operate and has smaller process control difficulty, and the bonding process is complex to operate and has larger process control difficulty, compared with the mode of realizing packaging through the bonding process in the prior art, the manufacturing method provided by the invention can effectively simplify the packaging process flow and reduce the control difficulty of the packaging process; on the other hand, the deposition process avoids using a cap sealing wafer like a bonding process, so compared with the mode of realizing packaging through the bonding process in the prior art, the method can greatly reduce the packaging cost; in another aspect, the deposition process can be performed on a plurality of wafers, and the bonding process is performed on a single wafer, so that compared with the prior art in which the packaging is performed by the bonding process, the present invention can effectively improve the packaging efficiency and thus the productivity.
Accordingly, the present invention also provides a packaged device comprising:
the device chip comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area;
a first sealing layer disposed on the device chip and having a plurality of via holes at a portion located above the functional region;
a second sealing layer disposed on the first sealing layer, filling the plurality of through holes;
the device chip, the first sealing layer and the second sealing layer form a closed second cavity above the functional region.
Next, each component of the above-described packaged device will be described in detail.
Specifically, the packaged device provided by the invention comprises a device chip. It should be noted that all the device chips packaged by using the bonding process in the prior art are suitable for the packaged device provided by the present invention, such as cavity type FBAR device chips (including air cavity type FBAR filters, FBAR duplexers, FBAR sensors, etc.), bragg reflective layer type FBAR device chips (including lagrangian reflective layer type FBAR filters, FBAR duplexers, FBAR sensors, etc.), and so on. It will be appreciated by those skilled in the art that for the sake of brevity, a list of all device chips suitable for use with the present invention is not provided herein.
In the present embodiment, the device chip includes a substrate, a functional region, a metal contact, and a seal ring. The substrate is usually made of a semiconductor material such as silicon or germanium. The functional region is disposed on the substrate and is a portion for realizing the function of the device chip. The FBAR device chip of the air cavity type and the FBAR device chip of the bragg reflector type are still exemplified for explanation. The functional areas of the air cavity type FBAR device chip and the Bragg reflection layer type FBAR device chip are used for realizing conversion of electric energy-sound energy-electric energy, wherein the functional areas of the air cavity type FBAR device chip comprise a cavity arranged on a substrate, and a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the cavity from bottom to top. The functional region of the Bragg reflection layer type FBAR device chip comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on a substrate from bottom to top. It will be understood by those skilled in the art that the FBAR device chip of the air cavity type and the FBAR device chip of the bragg reflector type are only schematic examples, and for the sake of brevity, the functional region structures of other device chips suitable for the present invention will not be described one by one. The metal contact and the sealing ring are disposed on the substrate in a manner surrounding the functional region. The arrangement modes of the metal contact point and the sealing ring comprise two modes, one mode is that the metal contact point is arranged on the outer side of the functional area and surrounds the functional area, and the sealing ring is arranged on the outer side of the metal contact point and surrounds the metal contact point and the functional area; another way is that the sealing ring is arranged outside the functional area, forming a surround for the functional area, and the metal contact point is arranged outside the sealing ring, forming a surround for the sealing ring and the functional area. Among them, the metal contact is preferably made of a metal material such as gold, aluminum, copper, nickel, high temperature tin-lead alloy, and the seal ring is preferably made of a metal material such as copper, gold, and the like.
Hereinafter, the packaged device provided by the present invention will be described by taking an FBAR device chip of an air cavity type as an example. As shown in fig. 2(n), the FBAR device of the air cavity type includes a substrate 100, a stacked structure 101 on the substrate 100, a metal contact 103 surrounding the stacked structure 101, and a seal ring 104 surrounding the metal contact 103. The stacked structure 101 includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer from bottom to top, and the lower electrode layer, the piezoelectric layer, and the upper electrode layer are not distinguished in the figure, but are represented as a whole by the stacked structure 101. A first cavity 113 is disposed between the stacked structure 101 and the substrate 100, and the stacked structure 101 and the first cavity 113 form a functional region of an air cavity FBAR device chip. Typically, the stacked structure 101 is further provided with a first through hole 102, and the first through hole 102 is used for removing the filling material filled in the first cavity 113 during the manufacturing process of the packaged device.
The packaged device provided by the invention further comprises a first sealing layer 109, wherein the first sealing layer 109 is arranged on the device chip and covers the device chip, the first sealing layer 109 and the device chip form a second cavity 114 above a functional region of the device chip, in the embodiment, the depth of the second cavity 114 is more than 3 μm, and the thickness of the part, above the second cavity 114, of the first sealing layer 109 is more than 3 μm.
The portion of the first encapsulation layer 109 above the functional region has a plurality of second vias 112, and the second vias 112 are used to remove the filling material filled in the second cavities 114 during the manufacturing process of the packaged device. In the present embodiment, the opening shape of the second through hole 112 is circular. It will be understood by those skilled in the art that the opening shape of the second through hole 112 is not limited in any way, and in other embodiments, the opening shape of the second through hole 112 may be triangular, rectangular, etc. It should be noted that in the present embodiment, the opening shapes of all the second through holes 112 are the same, and in other embodiments, the opening shapes of the second through holes 112 may also be different. In the present embodiment, the plurality of second through holes 112 are uniformly distributed over the filling layer 108, wherein the uniform distribution of the second through holes 112 is more favorable for the good removal of the filling material filled in the second cavity 114. It will be appreciated by those skilled in the art that in other embodiments, the plurality of second through holes 112 may be distributed non-uniformly or randomly over the filling layer 108. In addition, the aspect ratio of the second through hole 112 is preferably greater than 3:1, so that when the second through hole 112 is sealed in the manufacturing process of the packaged device, the performance of the device chip is not affected by the fact that the sealing material enters the second cavity 114 due to the small aspect ratio. Furthermore, the second through holes 112 need to have a certain hole density, otherwise, the removal efficiency of the filling material is affected, and in the embodiment, the ratio of the sum of the hole areas of the plurality of second through holes 112 to the upper surface area of the second cavity 114 is set to be in the range of 20% to 80%.
The packaged device provided by the invention further comprises a second sealing layer 115, wherein the second sealing layer 115 is arranged on the first sealing layer 109, the second sealing layer 115 fills the plurality of through holes 112 in the first sealing layer 109, so that the first cavity 113 and the second cavity 114 form a closed cavity, in the embodiment, the material of the second sealing layer 115 comprises, but is not limited to, α -Si, the stress requirement is less than 100MPa, and the thickness is in a range from 2 μm to 10 μm.
In the packaging device provided by the invention, the sealing layer part is formed in a deposition mode, so that on one hand, the deposition process is simple to operate, the process control difficulty is low, the bonding process is complex to operate, and the process control difficulty is high, so that compared with the packaging device formed by the bonding process in the prior art, the packaging device provided by the invention has the characteristics of simple packaging process flow and low packaging process control difficulty; on the other hand, because the deposition process avoids using a cap sealing wafer like a bonding process, compared with a packaging device formed by the bonding process in the prior art, the packaging device provided by the invention has lower packaging cost; in another aspect, since the deposition process can be performed with multiple chips, and the bonding process is performed substantially with a single chip, the packaged device provided by the present invention has higher packaging efficiency and thus higher throughput than the packaged device formed by the bonding process in the prior art.
The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, and means described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, or means.
Claims (20)
1. A method of manufacturing a packaged device, the method comprising:
providing a device chip to be packaged, wherein the device chip to be packaged comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area;
depositing a filling layer covering the functional area above the functional area;
depositing and forming a first sealing layer covering the device chip to be packaged and the filling layer on the device chip to be packaged;
forming a plurality of through holes on the first sealing layer to expose the filling layer, and removing the filling layer through the plurality of through holes;
and depositing a second sealing layer on the first sealing layer to seal the through holes to form the packaged device.
2. The manufacturing method according to claim 1, wherein:
the functional area comprises a first cavity arranged on the substrate, and a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the cavity from bottom to top; or
The functional area comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the substrate from bottom to top.
3. The manufacturing method according to claim 2, wherein:
aiming at the condition that the functional area comprises a first cavity, a lower electrode layer, a piezoelectric layer and an upper electrode layer, the cavity is filled with a sacrificial layer.
4. The manufacturing method according to any one of claims 1to 3, the step of depositing a filling layer over the functional region to form a layer covering the functional region comprising:
depositing a covering layer covering the substrate, the functional area, the metal contact point and the sealing ring on the device chip to be packaged;
forming a first photoresist layer on the covering layer, and performing patterning operation on the first photoresist layer to only reserve a part above the functional region;
removing the part, which is not covered by the first photoresist layer, of the covering layer in an etching mode so as to form a filling layer covering the functional region above the functional region;
and removing the first photoresist layer.
5. The method of manufacturing of claim 4, wherein the cap layer is formed using PECVD deposition at a temperature in a range of 200 ℃ to 400 ℃.
6. The manufacturing method according to claim 4, wherein a material of the cover layer is phosphosilicate glass or undoped silicate glass.
7. The manufacturing method according to claim 4, wherein:
aiming at the condition that the functional area comprises a cavity, a lower electrode layer, a piezoelectric layer and an upper electrode layer, and a sacrificial layer is filled in the cavity, the material of the covering layer is the same as that of the sacrificial layer.
8. The manufacturing method according to claim 4, wherein: the thickness of the filling layer is more than 3 μm.
9. The manufacturing method according to any one of claims 1to 3, wherein the plurality of through holes are uniformly distributed over the filling layer.
10. The manufacturing method according to any one of claims 1to 3, wherein an aspect ratio of the through-hole is greater than 3: 1.
11. The manufacturing method according to claim 10, wherein a ratio between a sum of open area of the plurality of through holes and an area of an upper surface of the filling layer ranges from 20% to 80%.
12. The manufacturing method according to any one of claims 1to 3, further comprising, after removing the filling layer through the plurality of through holes and before forming the packaged device after depositing a second sealing layer on the first sealing layer to seal the plurality of through holes:
and heating the device chip to be packaged to release gas in the device chip to be packaged.
13. The manufacturing method according to any one of claims 1to 3, wherein:
the first sealing layer is made of α -Si and is formed by PECVD deposition, the deposition temperature range is 200-400 ℃, the deposition pressure is less than 1Torr, the stress requirement is less than 100MPa, the thickness is more than 3 μm, and/or
The second sealing layer is made of α -Si and is formed by PECVD deposition, the deposition temperature range is 200-400 ℃, the deposition pressure is less than 1Torr, the stress requirement is less than 100MPa, and the thickness range is 2-10 μm.
14. A packaged device, comprising:
the device chip comprises a substrate, a functional area positioned on the substrate, and a metal contact point and a sealing ring which are positioned on the substrate and arranged around the functional area;
a first sealing layer disposed on the device chip and having a plurality of via holes at a portion located above the functional region;
a second sealing layer disposed on the first sealing layer, filling the plurality of through holes;
the device chip, the first sealing layer and the second sealing layer form a closed second cavity above the functional region.
15. The packaged device of claim 14, wherein:
the functional area comprises a first cavity arranged on the substrate, and a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the cavity from bottom to top; or
The functional area comprises a Bragg reflection layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer which are sequentially arranged on the substrate from bottom to top.
16. The packaged device of claim 14 or 15, wherein the depth of the second cavity is greater than 3 μ ι η.
17. The packaged device of claim 14 or 15, wherein the plurality of vias are evenly distributed over the functional region.
18. The packaged device of claim 14 or 15, wherein the aspect ratio of the via is greater than 3: 1.
19. The packaged device of claim 18, wherein a ratio between a sum of open area of the plurality of vias and an upper surface area of the second cavity ranges from 20% to 80%.
20. The packaged device of claim 14 or 15, wherein:
the first sealing layer is made of α -Si with stress requirement less than 100MPa and thickness more than 3 μm, and/or
The material of the second sealing layer is α -Si, the stress requirement is less than 100MPa, and the thickness range is 2-10 μm.
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| CN112039490B (en) * | 2020-03-31 | 2022-07-12 | 中芯集成电路（宁波）有限公司 | Thin film piezoelectric acoustic wave filter and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229913C (en) * | 2001-03-01 | 2005-11-30 | 安捷伦科技有限公司 | Improved method for mfg. thin film sound resonator and thin film sound resonator structure of carrying out said method |
| CN104202010A (en) * | 2014-08-28 | 2014-12-10 | 中国工程物理研究院电子工程研究所 | Hollow cavity-type film bulk acoustic resonator and production method for same |
| CN105763169A (en) * | 2015-01-06 | 2016-07-13 | 珠海越亚封装基板技术股份有限公司 | Film bulk acoustic resonator filter |
| CN107181472A (en) * | 2016-03-10 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | FBAR, semiconductor devices and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110041179A (en) * | 2009-10-15 | 2011-04-21 | 한국전자통신연구원 | Structure for packaging |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1229913C (en) * | 2001-03-01 | 2005-11-30 | 安捷伦科技有限公司 | Improved method for mfg. thin film sound resonator and thin film sound resonator structure of carrying out said method |
| CN104202010A (en) * | 2014-08-28 | 2014-12-10 | 中国工程物理研究院电子工程研究所 | Hollow cavity-type film bulk acoustic resonator and production method for same |
| CN105763169A (en) * | 2015-01-06 | 2016-07-13 | 珠海越亚封装基板技术股份有限公司 | Film bulk acoustic resonator filter |
| CN107181472A (en) * | 2016-03-10 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | FBAR, semiconductor devices and its manufacture method |
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