CN109755308A - The manufacturing method of semiconductor structure and high electron mobility transistor - Google Patents
The manufacturing method of semiconductor structure and high electron mobility transistor Download PDFInfo
- Publication number
- CN109755308A CN109755308A CN201711090586.5A CN201711090586A CN109755308A CN 109755308 A CN109755308 A CN 109755308A CN 201711090586 A CN201711090586 A CN 201711090586A CN 109755308 A CN109755308 A CN 109755308A
- Authority
- CN
- China
- Prior art keywords
- etching
- manufacturing
- gallium nitride
- etch step
- nitride semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
The manufacturing method of semiconductor structure includes that gallium nitride semiconductor layer is formed on the substrate, insulating layer containing silicon is formed on gallium nitride semiconductor layer, it is depressed in insulating layer containing silicon by the formation of the first etch step, wherein the first etch step using fluorine-containing etching agent and applies the first substrate bias power, and extended to recess in gallium nitride semiconductor layer by the second etch step, wherein the second etch step is using fluorine-containing etching agent and is applied more than the second substrate bias power of the first substrate bias power.In addition, also providing the manufacturing method of high electron mobility transistor.The present invention can promote the reliability and production efficiency of semiconductor device.
Description
Technical field
The embodiment of the present invention is about semiconductor processing technology, and particularly with regard to semiconductor structure and high electron mobility
The manufacturing method of transistor.
Background technique
Gallium nitride (GaN-based) semiconductor material has many outstanding material properties, such as high heat resistance, wide energy
Gap (band-gap), high electron saturation velocities.Therefore, gallium nitride semiconductor material is suitably applied the operation of high speed with high temperature
Environment.In recent years, gallium nitride semiconductor material be widely used in light emitting diode (light emitting diode,
LED) element, high-frequency element, such as high electron mobility transistor (the high electron with heterogeneous interface structure
Mobility transistor, HEMT).
With the development of gallium nitride semiconductor material, these use the photoelectric cell application of gallium nitride semiconductor material
In more harsh working environment, such as higher frequency or at higher temperature.Therefore, with the semiconductor element of gallium nitride semiconductor material
Process conditions also face many new challenges.
Summary of the invention
Some embodiments of the present invention provide the manufacturing method of semiconductor structure, and the method includes that nitridation is formed on the substrate
Gallium based semiconductor layer, forms insulating layer containing silicon on gallium nitride semiconductor layer, is depressed in and is contained by the formation of the first etch step
In silicon insulating layer, wherein the first etch step is using fluorine-containing etching agent and applies the first substrate bias power, and pass through the second etching
Step extends to recess in gallium nitride semiconductor layer, contains wherein the second etch step use is identical with the first etch step
Fluorine etching agent and the second substrate bias power for being applied more than the first substrate bias power.
Some embodiments of the present invention provide the manufacturing method of high electron mobility transistor, and the method is included in substrate
It is rectangular at gallium nitride semiconductor layers, aluminum gallium nitride semiconductor layer is formed on gallium nitride semiconductor layers, in aluminum gallium nitride semiconductor
Insulating layer containing silicon is formed on layer, the first recess and second is formed by the first etch step and is depressed in insulating layer containing silicon, wherein
First etch step using fluorine-containing etching agent and apply the first substrate bias power, and by the second etch step by first recess and
Second recess extends in aluminum gallium nitride semiconductor layer, wherein the second etch step use is identical with the first etch step fluorine-containing
Etching agent and the second substrate bias power for being applied more than the first substrate bias power.The method is also included in the first recess and the second recess
It is respectively formed source contact and drain contacts, and forms gate contact between source contact and drain contacts
Part.
The present invention can promote the reliability and production efficiency of semiconductor device.
Detailed description of the invention
Cooperate institute's accompanying drawings by described in detail below and example, can more understand the embodiment of the present invention.In order to make figure
Formula clearly shows that each different element may be drawn not according to ratio in schema, in which:
Figure 1A to Fig. 1 E is according to some embodiments of the present invention, to illustrate each centre for the method to form semiconductor structure
The diagrammatic cross-section in stage.
Fig. 2 is according to some embodiments of the present invention, to illustrate the flow chart for the method to form semiconductor structure.
Fig. 3 is according to some embodiments of the present invention, to show fluorine-containing etching agent to the etching speed of gallium nitride semiconductor layer
The curve graph of rate and the substrate bias power of application.
Fig. 4 A to Fig. 4 E is other embodiments according to the present invention, the method for illustrating to form high electron mobility transistor
Each intermediate stage diagrammatic cross-section.
Fig. 5 is the diagrammatic cross-section of high electron mobility transistor according to another embodiment of the present invention.
Drawing reference numeral
100~semiconductor structure；
101,201~substrate；
102~gallium nitride semiconductor layer；
104,208~insulating layer containing silicon；
106,210~mask layer；
107~opening；
108,108 '~recess；
200,300~high electron mobility transistor；
202~buffer layer；
204~gallium nitride semiconductor layers；
206~aluminum gallium nitride semiconductor layer；
212~the first openings；
214~the second openings；
216, the 216 '~the first recess；
218, the 218 '~the second recess；
220~source contact；
222~drain contacts；
224~passivation layer；
226~third recess；
228~gate contact；
500,510~etching technics；
The etch step of 500A, 510A~first；
The etch step of 500B, 510B~second；
501~etching apparatus；
502~etching cavity；
503~air supply system；
504~substrate bias power generating source；
505~chip microscope carrier；
506~sprinkler head；
507~etching terminal detector；
600~manufacturing method；
602,604,606~step；
D1~depth；
T1~thickness.
Specific embodiment
It is described below to provide many different embodiments or example, for implementing the different components of the embodiment of the present invention.
The concrete example of component and configuration to be described below, to simplify the embodiment of the present invention.Certainly, these are only example, are not anticipated
The figure limitation embodiment of the present invention.For example, if referring in narration, the first component is formed on second component, may include shape
The embodiment directly contacted at the first and second components, it is also possible to comprising additional component be formed in the first and second components it
Between, so that the embodiment that the first and second components will not be contacted directly.In addition, the embodiment of the present invention may weigh in many examples
The label and/or letter of multiple reference.These duplicate purposes are itself to be not intended to indicate various realities in order to simplified and clear
Apply example and/or the configuration that is discussed between relationship.
Furthermore spatially related wording can be used in the following description, such as " ... under ", " ... lower section ",
" lower section ", " in ... top ", " top " and other similar term, with simplify an element or component and other elements or
The statement of relationship as shown in the figure between other component.This space correlation wording is in addition to also wrapping comprising the discribed direction of schema
Different direction containing device in use or operation.Device can be positioned towards other directions and (be rotated by 90 ° or in other directions),
And space correlation description as used herein can be interpreted correspondingly according to this.
Figure 1A to Fig. 1 E is according to some embodiments of the present invention, to illustrate to be formed semiconductor structure 100 shown in Fig. 1 E
The diagrammatic cross-section in each intermediate stage of method.Each step shown in Figure 1A to Fig. 1 E is also schematically reflected in shown in Fig. 2
In each step of the flow chart of the manufacturing method 600 of semiconductor structure 100.With reference to Figure 1A, substrate 101 is provided, in substrate 101
Form gallium nitride (GaN-based) semiconductor layer 102.Then, insulating layer containing silicon is formed on gallium nitride semiconductor layer 102
104, and patterned mask layer 106 is formed in insulating layer containing silicon 104.Patterned mask layer 106 has opening 107,
Opening 107 exposes a part of the upper surface of insulating layer containing silicon 104.This individual step manufacturing method 600 shown in Fig. 2
In step 602 explanation.
In some embodiments of the invention, substrate 101 can be (such as being mixed with p-type or N-type dopant for doping
It is miscellaneous) or undoped semiconductor base, such as silicon base, silicon-Germanium base, GaAs substrate or similar semiconductor base.Some
In embodiment, substrate 101 can be the substrate that semiconductor is located on insulator, such as silicon-on-insulator (silicon on
Insulator, SOI) substrate.In some embodiments, substrate 101 can be silicon carbide (SiC) substrate or sapphire substrates.Base
Selecting for bottom 101 can be depending on the type according to the semiconductor device of 100 subsequent applications of semiconductor structure.
In some embodiments of the invention, the material of gallium nitride (GaN-based) semiconductor layer 102 can be GaN,
AlxGa1-xN(0<x<1)、InxGa1-xN(0<x<1)、InxAlyGa1-x-yN (0 < x+y < 1), combination above-mentioned, multilayer knot above-mentioned
Structure or similar gallium nitride semiconductor material, and gallium nitride semiconductor layer 102 can be by epitaxial growth (epitaxial
Growth) technique is formed, such as Metallo-Organic Chemical Vapor deposits (metal organic chemical vapor
Deposition, MOCVD), hydride vapour phase epitaxy method (hydride vapor phase epitaxy, HVPE), outside molecular beam
Prolong method (molecular beam epitaxy, MBE), combination above-mentioned or the like.In some embodiments, gallium nitride
Semiconductor layer 102 can have dopant, such as N-shaped or p-type dopant, and can be by epitaxial growth process along with implantation in situ
Dopant forms the gallium nitride semiconductor layer 102 with dopant.
In some embodiments of the invention, the material of insulating layer containing silicon 104 can be silica, silicon nitride, nitrogen oxidation
Silicon, combination above-mentioned or similar material, and insulating layer containing silicon 104 can be by thermal oxidation method (thermal oxideation), change
Learn vapor deposition (chemical vapor deposition, CVD), plasma auxiliary chemical vapor deposition (plasma
Enhanced CVD, PECVD), atomic layer deposition (atomic layer deposition, ALD) or the like formed.
In some embodiments of the invention, mask layer 106 can be photoresist layer, hard mask layer (such as nitride layer)
Or combination above-mentioned.In some embodiments, bottom antireflective coating (bottom can be initially formed in insulating layer containing silicon 104
Anti-reflective coating, BARC) (not shown), mask layer is formed on bottom antireflective coating (BARC) later
106 material layer.The material layer of mask layer 106 once being formed is formed in the material layer of mask layer 106 using photolithographic techniques
Opening 107, opening 107 expose a part of the upper surface of insulating layer containing silicon 104.
With reference to Figure 1B, will have gallium nitride semiconductor layer 102, insulating layer containing silicon 104 and mask layer 106 to be formed thereon
Substrate 101 be placed in etching apparatus 501, implement etching technics 500.In some embodiments of the invention, pass through mask
The opening 107 of layer 106 etches the gallium nitride semiconductor layer 102 of insulating layer containing silicon 104 and lower section, to form (the display of recess 108
In Fig. 1 D) in insulating layer containing silicon 104 and gallium nitride semiconductor layer 102.In some embodiments, etching technics 500 can be with
It is dry etch process, such as reactive ion etching (reactive ion etch, RIE), electron cyclotron resonance
(electron cyclotron resonance, ERC) etching, inductive coupling type plasma (inductively-coupled
Plasma, ICP) it etches or similar to dry etch process.
In some embodiments, as shown in Figure 1B, etching apparatus 501 includes etching cavity 502, air supply system 503, bias
Power generating source (bias power generator) 504, chip microscope carrier 505, sprinkler head 506 and etching terminal detector (end
point detector)507。
The air supply system 503 of etching apparatus 501 can provide etching agent used in etching technics 500, and pass through sprinkler head
506 can be uniformly dispersed etching agent into etching cavity 502.
The substrate bias power generating source 504 of etching apparatus 501 can be biased power to etching cavity 502, to generate bias
Electric field etching apparatus 501 top electrode (not showing, be generally disposed at the top of etching cavity 502) and lower electrode (do not show,
It is generally disposed inside chip microscope carrier 505) between.Etching agent is biased the acceleration of electric field in etching cavity 502, and towards
The direction of chip microscope carrier 505 carries out anisotropy to the gallium nitride semiconductor layer 102 of insulating layer containing silicon 104 and lower section
(anisotrpic) it etches.
The etching terminal detector 507 of etching apparatus 501 can in etching technics removal desired by immediately monitoring material
The etching signal of layer.When etching terminal detector 507 detect wish remove material layer etching terminal when, lower section it is another
Material layer starts exposed from the material layer for wishing to remove.Etching technics is examined since etching to etching terminal detector 507
It is referred to as main etching during measuring etching terminal.In general, in order to remove completely the material layer of top, in the main etching of etching technics
The over etching for implementing a period of time sustainable later.For example, the time for implementing over etching can be about the 5% of the main etching time
To 30%.
With reference to Fig. 1 C, will have gallium nitride semiconductor layer 102, insulating layer containing silicon 104 and mask layer 106 to be formed in it
On substrate 101 be placed on the chip microscope carrier 505 of etching apparatus 501 after, implement etching technics 500 the first etch step
500A.Step 604 explanation in this individual step manufacturing method 600 shown in Fig. 2.In some embodiments of the present invention
In, recess 108 ' is formed in insulating layer containing silicon 104 by the first etch step 500A.First etch step 500A, which can be used, to be contained
Fluorine etching agent, such as CF4、CHF3、CH2F2、CH3F or combination above-mentioned, and can be applied to about 100 watts (W) to about 500 watts it
Between the first substrate bias power to etching cavity 502.It is noted that when the first substrate bias power was set less than 100 watt-hours, fluorine-containing quarter
Erosion agent can not etch insulating layer containing silicon 104.When the setting of the first substrate bias power is greater than 500 watt-hours, since fluorine-containing etching agent is to containing
The etch rate of silicon insulating layer 104 is too big, may result in the first etch step 500A of etching technics 500 to insulating layer containing silicon
104 etching homogeneity is bad, this will be unfavorable for subsequent the second etch step carried out to gallium nitride semiconductor layer 102
500B。
With reference to Fig. 1 D, after the first etch step 500A of etching technics 500, implement the second quarter of etching technics 500
Lose step 500B.Step 606 explanation in this individual step manufacturing method 600 shown in Fig. 2.In some realities of the invention
It applies in example, the first etch step 500A and the second etch step 500B in identical etching cavity 502 (in-situ) in situ are real
It applies.In other words, after the first etch step 500A terminates, substrate 101 is not to move out etching cavity 502, and continues incessantly
The second etch step 500B is carried out in etching cavity 502.In some embodiments, as shown in figure iD, it is walked by the second etching
Rapid 500B 108 ' (being shown in Fig. 1 C) that will be recessed extend in gallium nitride semiconductor layer 102, and generate recess 108.Second quarter
Step 500B use fluorine-containing etching agent identical with the first etch step 500A is lost, and is applied more than the second of the first substrate bias power
Substrate bias power is to etching cavity 502.
It is according to some embodiments of the present invention, to show fluorine-containing etching agent to gallium nitride semiconductor layer with reference to Fig. 3, Fig. 3
The curve graph of 102 etch rate and the substrate bias power of application.As shown in figure 3, when the second substrate bias power is set in 0 to 1000 watt
Between when, fluorine-containing etching agent is almost 0 to the etch rate of gallium nitride semiconductor layer 102.When the second substrate bias power is set in
When between 1000 watts to 1350 watts, fluorine-containing etching agent is to the etch rate of gallium nitride semiconductor layer 102 with the second bias function
Rate increases and is gradually increasing.When substrate bias power setting is greater than 1350 watt-hours, since fluorine-containing etching agent is to gallium nitride semiconductor layer
102 etch rate is too big, may cause the second etch step 500B of etching technics 500 to gallium nitride semiconductor layer 102
Etching homogeneity it is bad, and the lattice structure on surface that gallium nitride semiconductor layer 102 is exposed by recess 108 may
It is destroyed by fluorine-containing etching agent.Therefore, in some embodiments of the invention, the second substrate bias power of the second etch step 500B can
Between about 1000 watts to about 1350 watts.
According to some embodiments of the present invention, in the first etch step 500A, insulating layer containing silicon 104 and gallium nitride half
The etching selection ratio of conductor layer 102 is greater than 10 and less than 1000.Therefore, in some embodiments, in the first etch step 500A
It may include that over etching is implemented to insulating layer containing silicon 104.In this embodiment, the first etch step 500A can remove completely silicon insulation
Layer 104, and hardly etch the gallium nitride semiconductor layer 102 of lower section.
In some embodiments, the first etch step 500A does not implement over etching to insulating layer containing silicon 104.Due to the second quarter
The range of first substrate bias power of the range greater than the first etch step 500A of the second substrate bias power of step 500B is lost, therefore,
In this embodiment, the remainder of insulating layer containing silicon 104 not removed by the main etching of the first etch step 500A can be the
It is removed in two etch step 500B.In this embodiment, it since the first etch step 500A can not implement over etching, can contract
The activity duration of short etching technics 500 promotes the production efficiency of semiconductor structure 100.
In addition, the second etching of progress can be connected incessantly in some embodiments, after the first etch step 500A
Step 500B.In further embodiments, between the first etch step 500A and the second etch step 500B, etching technics
500 can extraly implement slow lifting step (ramping step), such as substrate bias power is set between the first substrate bias power
With the numerical value between the second substrate bias power.
With reference to Fig. 1 E, after the second etch step 500B of etching technics 500, implementable ashing (ash) technique is removed
Mask layer 106 in insulating layer containing silicon 104 forms semiconductor structure 100.In embodiments of the present invention, semiconductor structure 100 wraps
Containing substrate 101, gallium nitride semiconductor layer 102 in substrate 101, the siliceous insulation on gallium nitride semiconductor layer 102
Layer 104, and the recess 108 in insulating layer containing silicon 104 and gallium nitride semiconductor layer 102.It is worth noting that, of the invention
Embodiment utilizes the first etch step 500A and the second etch step 500B of etching technics 500, in identical etching cavity 502
It is middle using identical etching agent and different substrate bias powers, sequentially by 102 quarter of insulating layer containing silicon 104 and gallium nitride semiconductor layer
Erosion, to form recess 108.
In known lithographic method, the etching technics of gallium nitride semiconductor layer be using etching agent containing chlorine, such as
Cl2, and the etching technics of insulating layer containing silicon is then using fluorine-containing etching agent, such as CF4.Therefore, in known lithographic method,
Etching insulating layer containing silicon and etch nitride gallium based semiconductor layer needs carry out respective etching work respectively in two etching apparatus
Skill.
According to embodiments of the present invention, the second etch step 500B use of etching technics 500 and the first etch step 500A
Identical fluorine-containing etching agent, and it is applied more than the second substrate bias power of the first substrate bias power, carry out etch nitride gallium based semiconductor layer
102, allow etching insulating layer containing silicon 104 and etch nitride gallium based semiconductor layer 102 in identical etching cavity 502 according to
Sequence is implemented.Therefore, etching insulating layer containing silicon in situ through the embodiment of the present invention is partly led with gallium nitride semiconductor layer to be formed
The method of body structure can promote the production efficiency of the semiconductor device containing this semiconductor structure.
In addition, forming undesirable primary oxygen during the embodiment of the present invention also be can avoid between twice etching technique
Compound (native oxide) is on the surface of gallium nitride semiconductor layer 102 the problem that.Therefore, real through the invention
The etching technics in situ for etching insulating layer containing silicon and gallium nitride semiconductor layer of example is applied to form semiconductor structure, can be promoted and be contained
There is the reliability of the semiconductor device of this semiconductor structure.
Embodiment shown in Figure 1A to Fig. 1 E is an example, and the embodiment of the present invention is not limited thereto.Except above-mentioned Figure 1A
To other than embodiment shown in Fig. 1 E, the method for the embodiment of the present invention is equally applicable for other semiconductor structures.
Fig. 4 A to Fig. 4 E is other embodiments according to the present invention, illustrates to form high electron mobility as shown in Figure 4 E
The section in each intermediate stage of the method for transistor (high electron mobility transistor, HEMT) 200 shows
It is intended to.With reference to Fig. 4 A, substrate 201 is provided.Substrate 201 can be similar to the substrate 101 of earlier figures 1A to Fig. 1 E.
Then, buffer layer 202 is formed in substrate 201.Buffer layer 202 can be helped to slow down and is subsequently formed in buffer layer 202
The strain (strain) of the gallium nitride semiconductor layers 204 of top, and prevent defect be formed in top gallium nitride semiconductor layers 204
In, this strain is caused by the mismatch between gallium nitride semiconductor layers 204 and substrate 201.In some embodiments of the present invention
In, the material of buffer layer 202 can be AlN, GaN, AlxGa1-xN (1 < x < 1), combination above-mentioned or similar material.Buffer layer
202 can be formed by epitaxial growth process, such as Metallo-Organic Chemical Vapor deposits (MOCVD), hydride vapour phase epitaxy method
(HVPE), molecular beam epitaxy (MBE), combination above-mentioned or the like.Although in embodiment as shown in Figure 4 A, buffering
Layer 202 is single layer structure, however buffer layer 202 is also possible to multilayered structure.
Then, gallium nitride (GaN) semiconductor layer 204 is formed on buffer layer 202, and in gallium nitride semiconductor layers 204
Upper formation aluminum gallium nitride (AlxGa1-xN, wherein 0 < x < 1) semiconductor layer 206.Gallium nitride semiconductor layers 204 are partly led with aluminum gallium nitride
There is heterogeneous interface between body layer 206, two-dimensional electron gas (two-dimensional electron gas, 2DEG) can be made (not
Display) it is formed on this heterogeneous interface, therefore, high electron mobility transistor 200 as shown in Figure 4 E can utilize Two-dimensional electron
Gas is as conducting currier.In some embodiments of the invention, gallium nitride semiconductor layers 204 and aluminum gallium nitride semiconductor layer 206
Can be formed by epitaxial growth process, for example, Metallo-Organic Chemical Vapor deposition (MOCVD), hydride vapour phase epitaxy method (HVPE),
Molecular beam epitaxy (MBE), combination above-mentioned or the like.In some embodiments, gallium nitride semiconductor layers 204 and nitridation
Gallium aluminum semiconductor layer 206 can have dopant, such as n-type dopant or p-type dopant.
Then, insulating layer containing silicon 208 is formed on aluminum gallium nitride semiconductor layer 206.In some embodiments of the invention,
It is thin that insulating layer containing silicon 208 can be the high-quality formed using atomic layer deposition (ALD), thermal oxidation technology or similar depositing operation
Film, material can be silica, silicon nitride, silicon oxynitride, combination above-mentioned or similar material.In aluminum gallium nitride semiconductor layer
The insulating layer containing silicon 208 that high quality thin film is formed on 206, can prevent source contact 220, the drain contacts being subsequently formed
222 and gate contact 228 (being shown in Fig. 4 E) leakage current.
With continued reference to Fig. 4 A, the material layer of mask layer 210 is formed in insulating layer containing silicon 208, and utilize light lithography skill
Art forms the first opening 212 and the second opening 214, the first opening 212 and the second opening 214 in the material layer of mask layer 208
Expose a part of the upper surface of insulating layer containing silicon 208.
Then, will have buffer layer 202, gallium nitride semiconductor layers 204, aluminum gallium nitride semiconductor layer 206, insulating layer containing silicon
208 and the substrate 201 formed thereon of mask layer 210 be placed in etching apparatus 501 as shown in Figure 1B, implement etching technics
510.With reference to Fig. 4 B and Fig. 4 C, in an embodiment of the present invention, etching technics 510 includes the first etch step 510A and the second quarter
Step 510B is lost, and the first etch step 510A and the second etch step 510B of etching technics 510 can be with earlier figures 1C and figures
The the first etch step 500A and the second etch step 500B of etching technics 500 shown in 1D are similar.
In embodiments of the present invention, pass through the 214 siliceous insulation of etching of the first opening 212 of mask layer 210 and the second opening
Layer 208 and aluminum gallium nitride semiconductor layer 206, to form the first recess 216 and the second recess 218 as shown in Figure 4 C.
Specifically, as shown in Figure 4 B, by the first etch step 510A of etching technics 510 in insulating layer containing silicon 208
It is middle to form the first recess 216 ' and the second recess 218 '.First etch step 510A of etching technics 510 can be used and earlier figures
The identical etching agent and bias power range of first etch step 500A of etching technics 500 shown in 1C.Then, such as Fig. 4 C
It is shown, the first recess 216 ' and the second recess 218 ' are extended to by nitridation by the second etch step 510B of etching technics 510
In gallium aluminum semiconductor layer 206, and generate the first recess 216 and the second recess 218.Second etch step of etching technics 510
The identical etching agent and bias function with the second etch step 500B of etching technics 500 shown in earlier figures 1D can be used in 510B
Rate range.
In some embodiments, as shown in Figure 4 C, the first recess 216 and the second recess 218 are in aluminum gallium nitride semiconductor layer
Extend a distance D1 in 206, distance D1 can be between about 5% to about the 100% of the thickness T1 of aluminum gallium nitride semiconductor layer 206.
Distance D1 can be according to the carrier concentration and carrier transport factor of the two-dimensional electron gas (2DEG) for high electron mobility transistor 200
Depending on.
With reference to Fig. 4 D, after etching technics 510, implementable cineration technics removes the mask layer in insulating layer containing silicon 208
210。
With reference to Fig. 4 E, then, source contact 220 and drain electrode are respectively formed in the first recess 216 and the second recess 218
Contact 222.Source contact 220 and drain contacts 222 are located on aluminum gallium nitride semiconductor layer 206, and and aluminum gallium nitride
Semiconductor layer 206 is in electrical contact.In some embodiments, it is recessed can not to fill up first for source contact 220 and drain contacts 222
216 and second recess 218 are fallen into, but is formed along the side wall and bottom surface of the first recess 216 and the second recess 218, and is extended to
On the surface of part insulating layer containing silicon 208.In some embodiments, the material of source contact 220 and drain contacts 222 can
To be conductive material, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, combination above-mentioned or similar material
Material, and source contact 220 and drain contacts 222 can be by atomic layer depositions (ALD), chemical vapor deposition (CVD), physics gas
Mutually deposition (physical vapor deposition, PVD), sputtering or similar technique are formed.In some embodiments, source electrode
Contact 220 and drain contacts 222 can be formed together in identical depositing operation.
Then, passivation layer 224 is formed on source contact 220 and drain contacts 222, passivation layer 224 covers source electrode
Contact 220 and drain contacts 222.In some embodiments of the invention, the material of passivation layer 224 can be silicon nitride,
Silica, silicon oxynitride, combination above-mentioned or similar material.In some embodiments, passivation layer 224 can be by chemical vapor deposition
(CVD), plasma auxiliary chemical vapor deposition (PECVD), atomic layer deposition (ALD) or the like formation.
With continued reference to Fig. 4 E, third recess 226 is formed in passivation layer 224 using photolithographic techniques and etching technics, the
Three recess 226 are between source contact 220 and drain contacts 222.Then, grid is formed in third recess 226 to connect
Contact element 228, to form high electron mobility transistor 200.In some embodiments, gate contact 228 is located at siliceous insulation
On layer 208, and between source contact 220 and drain contacts 222.In some embodiments, gate contact 228 can
Third recess 226 is not filled up, but is formed along the side wall and bottom surface of third recess 226, and extend to portion of the passivating layer 224
On surface.In some embodiments, the material of gate contact 228 can be conductive material, for example, Au, Ni, Pt, Pd, Ir,
Ti、Cr、W、Al、Cu、TaN、TiN、WSi2, combination above-mentioned or similar material, and gate contact 228 can be by atomic layer deposition
(ALD), chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), sputtering or similar technique are formed.220 He of source contact
Drain contacts 222 can be finally electrically connected via the metal layer (not shown) for passing through passivation layer 224 with external circuit.
With reference to Fig. 5, embodiment shown in fig. 5 is with embodiment shown in Fig. 4 E the difference is that high electronics shown in fig. 5 moves
Third recess 226 in shifting rate transistor 300 extends in insulating layer containing silicon 208 and aluminum gallium nitride semiconductor layer 206.Such as scheming
Embodiment shown in 5, passivation layer 224 are siliceous insulating materials, and the with etching technics 500 shown in earlier figures 1C can be used
The similar etch step of one etch step 500A etches passivation layer 224 and insulating layer containing silicon 208.Then, can be used with it is aforementioned
The similar etch step of the second etch step 500B of etching technics 500 shown in Fig. 1 D is by 206 quarter of aluminum gallium nitride semiconductor layer
Erosion, to form third recess 226.In this embodiment, gate contact 228 is formed in third recess 226, and gate contact
The bottom surface of part 228 can directly be contacted with aluminum gallium nitride semiconductor layer 206, to form high electron mobility transistor 300.
In addition, in further embodiments, the manufacturing method of high electron mobility transistor 300 can be additionally included in form grid
Before pole contact 228, formed gate structure (not shown) in third recess 226 in and insertion aluminum gallium nitride semiconductor layer 206
In.Later, gate contact 228 is formed in the remainder of third recess 226, and gate contact 228 is set to grid
In structure.In some embodiments, gate structure can be the gallium nitride semiconductor layers of doping, such as the gallium nitride of N-type is partly led
The gallium nitride semiconductor layers of body layer or p-type, and can be formed by epitaxial growth process, such as Metallo-Organic Chemical Vapor deposition
(MOCVD), hydride vapour phase epitaxy method (HVPE), molecular beam epitaxy (MBE), combination above-mentioned or the like.
In conclusion the embodiment of the present invention is depressed in insulating layer containing silicon using the first etch step formation of etching technics
In, and using the second etch step of etching technics extended to recess in gallium nitride semiconductor layer, wherein the second etching
Step use fluorine-containing etching agent identical with the first etch step, and be applied more than the first substrate bias power of the first etch step
Second substrate bias power, allow etching insulating layer containing silicon and etch nitride gallium based semiconductor layer in identical etching cavity according to
Sequence is implemented.Therefore, etching insulating layer containing silicon in situ through the embodiment of the present invention is partly led with gallium nitride semiconductor layer to be formed
The method of body structure can promote the production efficiency of the semiconductor device containing this semiconductor structure.
The foregoing general description component of some embodiments, allows in the technical field of the invention that related technical personnel are more
Add the viewpoint for understanding the embodiment of the present invention.Related technical personnel are, it is to be appreciated that they can be light in the technical field of the invention
Easily using based on the embodiment of the present invention, other techniques or structure are designed or modified, with the reality for reaching with introducing herein
Apply the identical purpose of example and/or advantage.Related technical personnel are it will also be appreciated that such equivalent knot in the technical field of the invention
Structure does not simultaneously depart from spirit and scope of the invention, and in the case where without departing from the spirit and scope, can do herein
Various change, substitution and replacements.Therefore, subject to protection scope of the present invention ought be defined depending on claim.
Claims (20)
1. a kind of manufacturing method of semiconductor structure characterized by comprising
A gallium nitride semiconductor layer is formed in a substrate；
An insulating layer containing silicon is formed on the gallium nitride semiconductor layer；
It forms one by one first etch step to be depressed in the insulating layer containing silicon, wherein first etch step is fluorine-containing using one
Etching agent and one first substrate bias power of application；And
The recess is extended in the gallium nitride semiconductor layer by one second etch step, wherein second etch step makes
With the fluorine-containing etching agent and it is applied more than one second substrate bias power of first substrate bias power.
2. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the gallium nitride semiconductor layer includes
GaN, AlGaN or InGaN.
3. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the insulating layer containing silicon includes oxidation
Silicon, silicon nitride, silicon oxynitride or combination above-mentioned.
4. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that first substrate bias power is at 100 watts
To between 500 watts.
5. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that second substrate bias power is at 1000 watts
To between 1350 watts.
6. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the fluorine-containing etching agent includes CF4、
CHF3、CH2F2、CH3F or combination above-mentioned.
7. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that, should in first etch step
Insulating layer containing silicon and an etching selection ratio of the gallium nitride semiconductor layer are greater than 10.
8. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that first etch step and this second
Etch step is implemented in situ in an identical etching cavity.
9. the manufacturing method of semiconductor structure as claimed in claim 8, which is characterized in that after first etch step
It connects incessantly and carries out second etch step.
10. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that further include formed this it is siliceous absolutely
After edge layer, and before implementing first etch step, a mask layer is formed in the insulating layer containing silicon.
11. a kind of manufacturing method of high electron mobility transistor characterized by comprising
A gallium nitride semiconductor layers are formed above a substrate；
An aluminum gallium nitride semiconductor layer is formed on the gallium nitride semiconductor layers；
An insulating layer containing silicon is formed on the aluminum gallium nitride semiconductor layer；
It forms one first recess and one second by one first etch step to be depressed in the insulating layer containing silicon, wherein first quarter
Step is lost using a fluorine-containing etching agent and applies one first substrate bias power；
By one second etch step by this first be recessed and this second recess extend in the aluminum gallium nitride semiconductor layer, wherein
Second etch step is using the fluorine-containing etching agent and is applied more than one second substrate bias power of first substrate bias power；
A source contact and a drain contacts are respectively formed in first recess and second recess；And
A gate contact is formed between the source contact and the drain contacts.
12. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the insulating layer containing silicon
Including silica, silicon nitride or silicon oxynitride or combination above-mentioned.
13. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the first bias function
Rate is between 100 watts to 500 watts.
14. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the second bias function
Rate is between 1000 watts to 1350 watts.
15. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the fluorine-containing etching agent
Including CF4、CHF3、CH2F2、CH3F or combination above-mentioned.
16. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that in first etching
In step, an etching selection ratio of the insulating layer containing silicon and the aluminum gallium nitride semiconductor layer is greater than 10.
17. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the first etching step
Suddenly implement in situ in an identical etching cavity with second etch step.
18. the manufacturing method of high electron mobility transistor as claimed in claim 17, which is characterized in that in first etching
Second etch step is carried out continuously after step incessantly.
19. the manufacturing method of high electron mobility transistor as claimed in claim 17, which is characterized in that when first etching
When step is carried out to an etching terminal of the insulating layer containing silicon, over etching is not implemented to the insulating layer containing silicon.
20. the manufacturing method of high electron mobility transistor as claimed in claim 11, which is characterized in that the gate contact
It is set in the aluminum gallium nitride semiconductor layer and is contacted with the aluminum gallium nitride semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711090586.5A CN109755308B (en) | 2017-11-08 | 2017-11-08 | Semiconductor structure and method for manufacturing high electron mobility transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711090586.5A CN109755308B (en) | 2017-11-08 | 2017-11-08 | Semiconductor structure and method for manufacturing high electron mobility transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109755308A true CN109755308A (en) | 2019-05-14 |
| CN109755308B CN109755308B (en) | 2022-04-29 |
Family
ID=66401469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711090586.5A Active CN109755308B (en) | 2017-11-08 | 2017-11-08 | Semiconductor structure and method for manufacturing high electron mobility transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109755308B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289310A (en) * | 2019-06-29 | 2019-09-27 | 厦门市三安集成电路有限公司 | Transistor, gate structure and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060202272A1 (en) * | 2005-03-11 | 2006-09-14 | Cree, Inc. | Wide bandgap transistors with gate-source field plates |
| US20080194075A1 (en) * | 2007-02-13 | 2008-08-14 | Hsin-Chang Wu | Process of manufacturing a shallow trench isolation and process of treating bottom surface of the shallow trench for avoiding bubble defects |
| CN102237361A (en) * | 2010-04-23 | 2011-11-09 | 英特赛尔美国股份有限公司 | GaN based power devices with integrated protection devices: strucutres and methods |
| CN103227198A (en) * | 2012-01-27 | 2013-07-31 | 富士通半导体股份有限公司 | Compound semiconductor device and method of manufacturing the same |
| CN106711038A (en) * | 2015-11-12 | 2017-05-24 | 意法半导体股份有限公司 | Method for manufacturing an HEMT transistor and HEMT transistor with improved electron mobility |
-
2017
- 2017-11-08 CN CN201711090586.5A patent/CN109755308B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060202272A1 (en) * | 2005-03-11 | 2006-09-14 | Cree, Inc. | Wide bandgap transistors with gate-source field plates |
| US20080194075A1 (en) * | 2007-02-13 | 2008-08-14 | Hsin-Chang Wu | Process of manufacturing a shallow trench isolation and process of treating bottom surface of the shallow trench for avoiding bubble defects |
| CN102237361A (en) * | 2010-04-23 | 2011-11-09 | 英特赛尔美国股份有限公司 | GaN based power devices with integrated protection devices: strucutres and methods |
| CN103227198A (en) * | 2012-01-27 | 2013-07-31 | 富士通半导体股份有限公司 | Compound semiconductor device and method of manufacturing the same |
| CN106711038A (en) * | 2015-11-12 | 2017-05-24 | 意法半导体股份有限公司 | Method for manufacturing an HEMT transistor and HEMT transistor with improved electron mobility |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289310A (en) * | 2019-06-29 | 2019-09-27 | 厦门市三安集成电路有限公司 | Transistor, gate structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109755308B (en) | 2022-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103137476B (en) | There is the GaN high pressure HFET of passivation and gate-dielectric sandwich construction | |
| CN106486543A (en) | Semiconductor device and its manufacture method | |
| CN103545360A (en) | High electron mobility transistor and method of forming the same | |
| TW201242015A (en) | Compound semiconductor device, method for producing the same, and power supply | |
| CN103165445A (en) | In situ grown gate dielectric and field plate dielectric | |
| CN112531025B (en) | High electron mobility transistor | |
| CN108305918A (en) | Nitride semiconductor photogenerator and preparation method thereof | |
| JP4876927B2 (en) | Method for forming a semiconductor device | |
| US20050159000A1 (en) | Method for fabricating nitride-based compound semiconductor element | |
| JP2014241436A (en) | Schottky barrier diode and process of manufacturing the same | |
| TW530329B (en) | Nitride compound based semiconductor device and manufacturing method of same | |
| TW202022951A (en) | Semiconductor devices and methods for forming the same | |
| CN106257686A (en) | Semiconductor device and manufacture method thereof | |
| US11682713B2 (en) | Methods of fabricating semiconductor structures with two-step etching | |
| JP2019114581A (en) | Compound semiconductor device and manufacturing method thereof | |
| CN109755308A (en) | The manufacturing method of semiconductor structure and high electron mobility transistor | |
| TWI693716B (en) | Semiconductor devices and methods for fabricating the same | |
| CN106549049B (en) | A kind of method that electrochemical etching p-type nitride realizes enhanced HEMT | |
| CN102640258B (en) | Method of manufacturing nitride semiconductor device | |
| WO2015027654A1 (en) | Method for preparing gallium nitride-based high-voltage light-emitting diode | |
| JP2013016786A (en) | Power element and method for manufacturing the same | |
| TWI653683B (en) | Methods for fabricating semiconductor structures and high electron mobility transistors | |
| Li et al. | Implementation of slow and smooth etching of GaN by inductively coupled plasma | |
| JP2010212495A (en) | Method of manufacturing hfet composed of group-iii nitride semiconductor | |
| CN109326522B (en) | Preparation method of diamond heterojunction diode device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |