CN109753013B - Novel programmable chip circuit - Google Patents
Novel programmable chip circuit Download PDFInfo
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- CN109753013B CN109753013B CN201711067133.0A CN201711067133A CN109753013B CN 109753013 B CN109753013 B CN 109753013B CN 201711067133 A CN201711067133 A CN 201711067133A CN 109753013 B CN109753013 B CN 109753013B
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Abstract
A novel programmable chip circuit comprising: a back bias constant circuit and a back bias adjustable circuit, wherein the back bias constant circuit is coupled to the back bias adjustable circuit, comprising: a configuration module, a global signal generation module and a dedicated I/O module, wherein: the configuration module is suitable for downloading the configuration file and configuring the parameters; the global signal generation module is adapted to generate a global signal, and the global signal includes: a global power signal, a global voltage signal, and a global ground signal; the adjustable back bias circuit comprises: the back bias adjustable function module is suitable for generating a back bias signal and adjusting the working mode of the back bias adjustable function module based on the back bias signal. By applying the circuit, the back bias adjustable circuit can generate a back bias signal and adjust the working mode of the back bias adjustable functional module based on the back bias signal.
Description
Technical Field
The embodiment of the invention relates to the field of circuits, in particular to a novel programmable chip circuit.
Background
For a Programmable Device (PD) formed by transistors, after the processing is completed, the threshold of the transistor can be modulated secondarily by using different bias voltages, i.e. threshold voltage adjustment. Through threshold voltage adjustment, the working mode of the programmable chip can be dynamically adjusted, namely the programmable chip is adjusted to be in a high-power-consumption or low-power-consumption working mode.
In the existing programmable chip products composed of transistors, a body bias adjustment technology is mostly adopted, that is, the working mode of the programmable chip is dynamically adjusted based On a bulk silicon or thick film Silicon On Insulator (SOI) process. However, the main purpose of the body bias adjustment technology is to be consistent with a nominal value, and alleviate systematic parameter fluctuation caused by process fluctuation, lithography errors and the like, so that the adjustment voltage range is small, the adjustment effect on the working mode of the programmable chip is poor, and the application of the programmable chip in a commercial chip is limited.
Disclosure of Invention
The technical problem solved by the embodiment of the invention is how to provide a novel programmable chip circuit capable of dynamically adjusting the working mode of a chip.
To solve the above technical problem, an embodiment of the present invention provides a novel programmable chip circuit, including: back bias constant circuit and back bias adjustable circuit, wherein: the back bias constant circuit is coupled with the back bias adjustable circuit and comprises: a configuration module, a global signal generation module and a dedicated I/O module, wherein: the configuration module is suitable for downloading the configuration file and configuring the parameters; the global signal generation module is adapted to generate a global signal, and the global signal includes: a global power signal, a global voltage signal, and a global ground signal; the adjustable back bias circuit comprises: the back bias adjustable function module is suitable for generating a back bias signal and adjusting the working mode of the back bias adjustable function module based on the back bias signal.
Optionally, the back bias adjustable function module includes: the back bias signal generation submodule is suitable for generating a back bias signal and adjusting the working mode of the functional submodule based on the back bias signal and the global signal.
Optionally, adjacent back bias adjustable functional modules share one back bias signal generation submodule.
Optionally, the back bias signal generating sub-module includes: a generation submodule, a first control submodule and a second control submodule, wherein: the generation submodule is suitable for generating a negative voltage signal with a value opposite to that of the global voltage signal, and the negative voltage signal, the global ground signal and the global voltage signal are jointly used as back bias signals; the first control sub-module is suitable for setting the back bias voltage of an NMOS (N-channel metal oxide semiconductor) tube of the functional sub-module to be the global voltage signal and setting the back bias voltage of a PMOS (P-channel metal oxide semiconductor) tube of the functional sub-module to be the negative voltage signal when the functional sub-module needs high performance, and adjusting the functional sub-module to be in a high-power-consumption working mode; and the second control sub-module is suitable for setting the back bias voltage of the NMOS tube of the functional sub-module to be the negative voltage signal and setting the back bias voltage of the PMOS tube of the functional sub-module to be the global voltage signal when the functional sub-module needs low performance, and adjusting the functional sub-module to be in a low-power-consumption working mode.
Optionally, the global voltage signal is at least one of: I/Q voltage signals, core voltage signals.
Optionally, the back bias adjustable function module further includes: an enabling sub-module adapted to turn on or off the back bias generation sub-module according to an enabling signal.
Optionally, the enabling sub-module comprises: and the setting submodule is suitable for setting the back bias voltage of the NMOS tube and the back bias voltage of the PMOS tube of the functional submodule to be the global signal when the enabling submodule closes the back bias generation submodule, and adjusting the functional submodule to a static waiting working mode.
Optionally, the back bias adjustable circuit includes: the back bias adjustable logic module, the back bias adjustable special-purpose module and the back bias adjustable I/O module are coupled with each other, wherein the back bias adjustable logic module, the back bias adjustable special-purpose module and the back bias adjustable I/O module are independent back bias adjustable functional modules.
Optionally, the back bias adjustable function module further includes: an identification submodule and a selection submodule, wherein: the identification submodule is suitable for identifying the back bias signals in a target circuit and placing program codes corresponding to the back bias adjustable functional modules corresponding to the same back bias signals into the same back bias adjustable logic modules; and the selection submodule is suitable for selecting the corresponding back bias signal according to the performance requirement of the back bias adjustable functional module.
Optionally, the back bias constant circuit further comprises: and the setting module is suitable for setting the back bias voltage of the NMOS tube and the back bias voltage of the PMOS tube of the back bias constant circuit to be the global ground signal.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the novel programmable chip circuit provided by the embodiment of the invention comprises: the back bias constant circuit and the back bias adjustable circuit can generate a back bias signal through the back bias adjustable circuit, adjust the working mode of the back bias adjustable functional module based on the back bias signal, and realize the dynamic adjustment of the working mode of the programmable chip circuit through minor modification on the existing chip architecture.
Furthermore, the global voltage signal and the global ground signal are used as back bias signals, so that the generation and maintenance of non-power supply signals can be reduced, the occupied area of a capacitor can be reduced, and the hardware cost can be saved.
Drawings
Fig. 1 is a schematic structural diagram of a novel programmable chip circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a novel programmable chip circuit board according to an embodiment of the present invention.
Detailed Description
In the existing programmable chip product formed by transistors, the working mode of the programmable chip is dynamically adjusted by adopting a body bias adjusting technology. The voltage range adjusted by the body bias adjusting technology is small, so that the adjusting effect on the working mode of the programmable chip is poor, and the application of the programmable chip in a commercial chip is limited.
The embodiment of the invention provides a novel programmable chip circuit, which comprises: the back bias constant circuit and the back bias adjustable circuit can generate a back bias signal through the back bias adjustable circuit, adjust the working mode of the back bias adjustable functional module based on the back bias signal, and realize the dynamic adjustment of the working mode of the programmable chip circuit through minor modification on the existing chip architecture.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a novel programmable chip circuit, including: a back bias constant circuit 10 and a back bias adjustable circuit 11, wherein:
the back bias constant circuit 10 is coupled to the back bias adjustable circuit 11, and may include: a configuration module 101, a global signal generation module 102, and an Input/Output (I/O) module 103. The configuration module 101 is adapted to download a configuration file and perform parameter configuration; the global signal generating module 102 is adapted to generate a global signal, where the global signal includes: a global power signal, a global voltage signal, and a global ground signal; the dedicated I/O module 103 is adapted for dedicated interfaces, such as power supply interfaces, high speed interfaces, etc.
In a specific implementation, the global voltage signal may include: global I/O voltage signal VddioAnd a global core voltage signal VddcIn which V isddioAnd VddcIs a global positive voltage signal.
In a specific implementation, the back bias constant circuit 10 may further include: and a setting module (not shown) adapted to set both the back bias signal corresponding to the NMOS transistor and the back bias signal corresponding to the PMOS transistor of the back bias constant circuit 10 to be the global ground signal.
The back bias adjustable circuit 11 may include: the back bias adjustable functional module 111 is adapted to generate a back bias signal (back gate bias voltage signal, back bias signal for short), and adjust a working mode of the back bias adjustable functional module 111 based on the back bias signal.
In a specific implementation, the back bias adjustable circuit 11 may further include a plurality of back bias adjustable functional modules 111 coupled to each other, and the embodiment of the back bias adjustable functional module 111 shown in fig. 1 does not limit the scope of the present invention.
In an embodiment of the present invention, when the back bias adjustable circuit 11 includes a plurality of back bias adjustable functional modules 111 coupled to each other, the back bias adjustable circuit 11 may include: a back bias adjustable logic module, a back bias adjustable application specific module and a back bias adjustable I/O module (not shown) coupled to each other, wherein:
the back bias adjustable logic module is suitable for realizing the functions of generating logic gates and storing in a distributed mode.
The special module with adjustable back bias is suitable for realizing the function of block storage.
The back bias adjustable I/O module is suitable for realizing the input/output function of a user interface.
The back bias adjustable logic module, the back bias adjustable special module and the back bias adjustable I/O module are all the independent back bias adjustable functional module 111.
In a specific implementation, the back bias adjustable function module 111 may include: a back bias signal generation sub-module 1110 and a function sub-module 1111 coupled to each other, wherein:
the back bias signal generating sub-module 1110 is adapted to generate a back bias signal and adjust the operation mode of the function sub-module 1111 based on the back bias signal and the global signal;
the function sub-module 1111 is adapted to perform different programmable circuit functions, such as input/output functions, programmable logic functions, or dedicated logic functions.
In an implementation, to better adjust the operation mode of the function sub-module 1111, each of the back bias adjustable function modules 111 may include a separate back bias signal generation sub-module 1110 for adjusting the operation mode of the function sub-module 1111.
In a specific implementation, in order to save hardware cost, the back bias adjustable functional modules 111 adjacent to each other may share one back bias signal generating sub-module 1110, so as to adjust an operation mode of the functional sub-module 1111.
In a specific implementation, the more the back bias signal generated by the back bias signal generation sub-module 1110 is, the more the adjustment level of the function sub-module 1111 is, but the generation and maintenance of the non-power source signal require a relatively large capacitor device, which also results in a relatively large hardware cost. For example, if the back bias signal is from-2V to +2V and each step is 0.2V, 20 back bias signal paths are required and the area occupied by the capacitor will be very large. In order to reduce the hardware cost, the number of the back bias signals generated by the back bias signal generation sub-module 1110 needs to be simplified.
In an embodiment of the present invention, the global voltage signal and the global ground signal may be directly adopted as a part of the back bias signal. The back bias signal generating sub-module 1110 generates a negative voltage signal having a value opposite to that of the global voltage signal based on the global voltage signal, and uses the negative voltage signal as another part of the back bias signal. By reducing the number of back bias signals generated by the back bias signal generation sub-module 1110, the area of the capacitor can be effectively reduced, thereby reducing the hardware cost.
In particular implementations, the global voltage signal may be one or both of an I/Q voltage signal, a core voltage signal.
In an embodiment of the present invention, the back bias signal may include: vddio、Vgndand-Vddiowherein-VddioGenerating sub-module 1110, the generated AND V, for the back bias signalddioAnd negative voltage signals with opposite values.
In another embodiment of the present invention, the back bias signal may include: vddc、Vgndand-Vddcwherein-VddcGenerating sub-module 1110, the generated AND V, for the back bias signalddcAnd negative voltage signals with opposite values.
In another embodiment of the present invention, the back bias signal may include: vddio、Vgnd、Vddc、-Vddioand-Vddcwherein-VddioGenerating sub-module 1110, the generated AND V, for the back bias signalddioNegative voltage signal, -V with opposite valueddcGenerating sub-module 1110, the generated AND V, for the back bias signalddcAnd negative voltage signals with opposite values.
Due to Vddc、VgndAnd VddioAll can be straightBy applying, only two negative biases-Vddioand-VddcThe additional generation is needed, so the area of the capacitor device can be effectively reduced, and the hardware cost is reduced.
In a specific implementation, the functional sub-module 1111 may be adjusted to be in different operation modes by inputting different back bias signals.
In particular, to avoid p-to-n junction leakage, it is desirable that the Back gate Bias voltage to the n-well (n-well Back Bias, nbb) be greater than or equal to the Back gate Bias voltage to the p-well (p-well Back Bias, pbb). Nbb and pbb can be set to V at the same timegndOr nbb is set to the global voltage signal and pbb is set to the negative voltage signal generated by the back bias signal generation sub-module 1110.
In a specific implementation, V is set relative to both nbb and pbbgndWhen nbb is the most positive and pbb is the most negative, the adjusting effect on the device and the circuit is the strongest, the performance of the functional sub-module reaches the best when Forward Back Bias (FBB) is performed, the signal delay is the smallest, the worst when Reverse Back Bias (RBB) is performed, the signal delay is the largest, and the conduction current of the device is the lowest. Therefore, when high performance is required, the back gate bias voltage of the NMOS transistor of the functional sub-module 1111 (referred to as back bias voltage of the NMOS transistor for short) is set to correspond to nbb, which is the global voltage signal, and the back gate bias voltage of the PMOS transistor (referred to as back bias voltage of the PMOS transistor for short) corresponds to pbb, which is the negative voltage signal; when low performance is required, the back bias voltage of the NMOS transistor of the functional sub-module 1111 is set to pbb as the negative voltage signal, and the back bias voltage of the PMOS transistor is set to nbb as the global voltage signal.
In an embodiment of the present invention, the back bias signal generating sub-module 1110 may include: a generation sub-module (not shown), a first control sub-module (not shown) and a second control sub-module (not shown), wherein:
the generation submodule is suitable for generating a negative voltage signal with a value opposite to that of the global voltage signal, and the negative voltage signal, the global ground signal and the global voltage signal are jointly used as back bias signals.
The first control sub-module is suitable for setting back bias voltage of an NMOS (N-channel metal oxide semiconductor) tube of the function sub-module to be the global voltage signal and setting back bias voltage of a PMOS (P-channel metal oxide semiconductor) tube of the function sub-module to be the negative voltage signal when the function sub-module needs high performance, and adjusting the function sub-module to be in a high-power-consumption working mode.
And the second control sub-module is suitable for setting the back bias voltage of the NMOS tube of the functional sub-module to be the negative voltage signal and setting the back bias voltage of the PMOS tube of the functional sub-module to be the global voltage signal when the functional sub-module needs low performance, and adjusting the functional sub-module to be in a low-power-consumption working mode.
In a specific implementation, the performance requirements may be divided into: the system comprises a high performance and a low performance, wherein the high performance corresponds to higher power consumption and shorter time delay, the low performance corresponds to lower power consumption and longer time delay, and the system can be divided into more performance requirement grades and more working mode grades according to the grades of the power consumption and the time delay. It is understood that the performance requirements and the operation modes may also be referred to by other names, which are similar or identical in meaning, and are within the protection scope of the embodiments of the present invention.
In a specific implementation, since the overall power consumption of the circuit device is composed of dynamic power consumption and static power consumption, and the circuit with the back bias signal needs to consider the power consumption consumed in the back bias signal generating circuit, when the functional module 1111 is in the static waiting state, the back bias generating sub-module 1110 may be considered to be turned off, so as to save power consumption.
In an embodiment of the present invention, the back bias adjustable function module 111 may further include: an enable sub-module 1112 adapted to turn on or off the back bias generation sub-module 1110 according to an enable signal. When the enable signal is invalid, the back bias signal generation submodule 1110 is turned off, and when the enable signal is valid, the back bias signal generation submodule 1110 is turned on.
In an implementation, when the enable signal is disabled, the back bias signal generation submodule 1110 is turned off, and nbb and pbb can be simultaneously set to Vgnd。
In an embodiment of the invention, to save power consumption, the enabling sub-module 1112 may include: a setting sub-module (not shown) adapted to set both the back bias voltage of the NMOS transistor and the back bias voltage of the PMOS transistor of the functional sub-module 1111 to the global signal, i.e. both settings nbb and pbb, when the enable sub-module 1112 turns off the back bias generation sub-module 1110, adjusting the functional sub-module 1111 to a static standby mode of operation.
In a specific implementation, the back bias adjustable function module 111 may further include: an identification sub-module (not shown) and a selection sub-module (not shown), wherein:
the identification submodule is adapted to identify the back bias signal in the target circuit, and place the program code corresponding to the back bias adjustable functional module 111 corresponding to the same back bias signal in the same back bias adjustable logic module.
The selection submodule is adapted to select the corresponding back bias signal according to the performance requirement of the back bias adjustable function module 111.
In a specific implementation, the identifier sub-module and the selection sub-module may be implemented by computer language coding, for example, by C + + language coding.
By applying the novel programmable chip circuit, a back bias signal can be generated through the back bias adjustable circuit, the working mode of the back bias adjustable functional module is adjusted based on the back bias signal, and the dynamic adjustment of the working mode of the programmable chip circuit is realized through minor modification on the existing chip framework.
To enable those skilled in the art to better understand and implement the present invention, a schematic diagram of a novel programmable chip circuit board is provided in the embodiment of the present invention, as shown in fig. 2.
Referring to fig. 2, the novel programmable chip circuit board comprises: the system comprises a global signal generation module, a special I/O module, a configuration module, a back bias adjustable logic module, a back bias adjustable special module and a back bias adjustable I/O module, wherein the global signal generation module, the special I/O module and the configuration module belong to a back bias constant circuit, and the back bias adjustable logic module, the back bias adjustable special module and the back bias adjustable I/O module belong to a back bias adjustable functional circuit.
For the back bias adjustable logic module, the back bias adjustable functional module and the back bias adjustable I/O module, a back bias signal can be generated, and the working mode of the back bias adjustable logic module, the back bias adjustable functional module and the back bias adjustable I/O module can be adjusted based on the back bias signal.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A novel programmable chip circuit, comprising: back bias constant circuit and back bias adjustable circuit, wherein:
the back bias constant circuit is coupled with the back bias adjustable circuit and comprises: a configuration module, a global signal generation module and a dedicated I/O module, wherein: the configuration module is suitable for downloading the configuration file and configuring the parameters; the global signal generation module is adapted to generate a global signal, and the global signal includes: a global power signal, a global voltage signal, and a global ground signal;
the adjustable back bias circuit comprises: the back bias adjustable function module is suitable for generating a back bias signal and adjusting the working mode of the back bias adjustable function module based on the back bias signal.
2. The novel programmable chip circuit of claim 1, wherein the back bias adjustable function module comprises: the back bias signal generation submodule is suitable for generating a back bias signal and adjusting the working mode of the functional submodule based on the back bias signal and the global signal.
3. The novel programmable chip circuit of claim 2, wherein adjacent ones of the back bias adjustable functional modules share one of the back bias signal generation submodules.
4. The novel programmable chip circuit of claim 2, wherein the back bias signal generation submodule comprises: a generation submodule, a first control submodule and a second control submodule, wherein: the generation submodule is suitable for generating a negative voltage signal with a value opposite to that of the global voltage signal, and the negative voltage signal, the global ground signal and the global voltage signal are jointly used as the back bias signal;
the first control sub-module is suitable for setting the back bias voltage of an NMOS (N-channel metal oxide semiconductor) tube of the functional sub-module to be the global voltage signal and setting the back bias voltage of a PMOS (P-channel metal oxide semiconductor) tube of the functional sub-module to be the negative voltage signal when the functional sub-module needs high performance, and adjusting the functional sub-module to be in a high-power-consumption working mode;
and the second control sub-module is suitable for setting the back bias voltage of the NMOS tube of the functional sub-module to be the negative voltage signal and setting the back bias voltage of the PMOS tube of the functional sub-module to be the global voltage signal when the functional sub-module needs low performance, and adjusting the functional sub-module to be in a low-power-consumption working mode.
5. The novel programmable chip circuit of claim 4, wherein the global voltage signal is at least one of: I/Q voltage signals, core voltage signals.
6. The novel programmable chip circuit of claim 2, wherein the back bias adjustable function module further comprises: and the enabling submodule is suitable for opening or closing the back bias signal generating submodule according to an enabling signal.
7. The novel programmable chip circuit of claim 6, wherein the enable sub-module comprises: and the setting submodule is suitable for setting the back bias voltage of the NMOS tube and the back bias voltage of the PMOS tube of the functional submodule to be the global signal when the enabling submodule closes the back bias signal generating submodule, and adjusting the functional submodule to a static waiting working mode.
8. The novel programmable chip circuit of any of claims 1 to 7, wherein the back bias adjustable circuit comprises: the back bias adjustable logic module, the back bias adjustable special-purpose module and the back bias adjustable I/O module are coupled with each other, wherein the back bias adjustable logic module, the back bias adjustable special-purpose module and the back bias adjustable I/O module are independent back bias adjustable functional modules.
9. The novel programmable chip circuit of claim 8, wherein the back bias adjustable function module further comprises: an identification submodule and a selection submodule, wherein:
the identification submodule is suitable for identifying the back bias signals in a target circuit and placing program codes corresponding to the back bias adjustable functional modules corresponding to the same back bias signals into the same back bias adjustable logic modules;
and the selection submodule is suitable for selecting the corresponding back bias signal according to the performance requirement of the back bias adjustable functional module.
10. The novel programmable chip circuit of claim 1, wherein said back bias constant circuit further comprises: and the setting module is suitable for setting the back bias voltage of the NMOS tube and the back bias voltage of the PMOS tube of the back bias constant circuit to be the global ground signal.
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| CN205121468U (en) * | 2015-11-26 | 2016-03-30 | 济南大学 | System resets based on programmable logic chip |
| CN106707888A (en) * | 2017-02-16 | 2017-05-24 | 山东仕脉机器人技术有限公司 | Programmable control module, system provided with same and control method |
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| CN1776909A (en) * | 2004-10-14 | 2006-05-24 | 美国博通公司 | Integrated circuit chip programmable and operation method |
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