CN109740244A - A kind of multicore interconnection verification method of the irredundant uniform fold of excitation space - Google Patents
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Abstract
The invention discloses a kind of multicore interconnection verification methods of the irredundant uniform fold of excitation space, belong to chip emulation verifying field.Aiming at the problem that redundancy and uneven covering in the input stimulus space of processor existing in the prior art verifying, the present invention provides a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space, the multicore interconnection module abstracts excitation model based on oriented bipartite graph is initially set up；Originally then flat unordered excitation space is converted to 3 layers of excitation space tree using EP equivalence class partition algorithm；Then the leaf node collection of excitation space tree is traversed using optimization depth-first ODFT algorithm, obtains the irredundant all standing leaf node sequence comprising high-level excitation information；Each leaf node is converted into the input stimulus of actual bus interconnection finally by the relevant BusSti of bus protocol (LeafNode) transfer function.It may be implemented to realize excitation space irredundant uniform fold on the basis of guaranteeing to verify coverage rate.
Description
Technical field
The present invention relates to simulating, verifying algorithm fields, more specifically to a kind of irredundant uniform fold of excitation space
Multicore interconnection verification method.
Background technique
With the emergence and development of the information processing technologies such as artificial intelligence, big data and cloud computing, to electronic product performance
Requirement it is also higher and higher.And after 2003, increase the factors such as violent, single core processor as dominant frequency promotes limited and power consumption
The growth of performance obviously slows down, and multi-processor system-on-chip is at inexorable trend.Multicore interconnection is in multicore SoC in addition to kernel in structure
Except most important component, basic role be realize data interaction between internuclear and kernel and peripheral hardware in difference, therefore its
The correctness of function is that entire multiple nucleus system function is correctly basic.Multicore interconnection generally has bus type and network-on-chip
(Network on Chip, NoC) two different implementations of formula, relative to the asynchronous communication and complex network agreement of NoC,
Bus type interconnection uses synchronous communication mode, realizes simply, therefore when nucleus number is not especially big, is that multiple nucleus system is most common mutually
Connection mode.
With the continuous growth of processor scale and nucleus number, therewith it is adjoint be flow success rate for the first time decline.According to
It counts current functional verification and has accounted for 70% or so in the extensive IC design R&D cycle, and simulating, verifying is current
Most important functional verification means, effect and quality directly depend on its input stimulus.Commonly used simulation excitation at present
Generation strategy is based on random algorithm, and arbitrary excitation can many times help to generate some unexpected Corner
Case, so as to trigger some design defect for being difficult to expect.But it is more and more deep with studying, the drawbacks of arbitrary excitation
It is more and more obvious, maximum problem is the redundancy and unevenly covering, and design scale to be verified in input stimulus space
Bigger, this inhomogeneities is more serious.
Therefore the verifying for multicore interconnection module, how excitation sky is realized on the basis of guaranteeing to verify coverage rate
Between irredundant uniform fold have become the hot spot and difficult point of research.
Summary of the invention
1. technical problems to be solved
Aiming at the problem that redundancy and uneven covering in the input stimulus space of processor existing in the prior art verifying,
The present invention provides a kind of multicore interconnection verification methods of the irredundant uniform fold of excitation space, it may be implemented guaranteeing
The irredundant uniform fold of excitation space is realized on the basis of verifying coverage rate.
2. technical solution
The purpose of the present invention is achieved through the following technical solutions.
A kind of multicore interconnection verification method of the irredundant uniform fold of excitation space, steps are as follows:
Step 1 establishes the abstract excitation model of the multicore interconnection based on oriented bipartite graph；
Originally flat unordered excitation space is converted into 3 layers of excitation space tree by step 2；
Step 3 optimizes depth-first ODFT traversal to excitation space tree, obtains comprising high-level excitation information
Irredundant all standing leaf node sequence；
It is mutual to be converted into actual bus by the relevant BusSti transfer function of bus protocol by step 4 for each leaf node
The input stimulus of connection.
Further, the abstract excitation model of the multicore interconnection in step 1 be oriented bipartite model DBG=<
BVh,BVs, BE >, wherein principal point collection BVhIn point and be integrated in bus main equipment and correspond；From point set BVsIn point with
It is integrated in bus from equipment and corresponds；BE is directed edge collection.
Further, it is BV that BE, which is directed edge collection,hMiddle vertex v hiTo BVsMiddle vertex v siBetween there are directed edge eij
=< vhi,vsj> necessary and sufficient condition be vhiThe accessible vs of excitation that corresponding main equipment is initiatediIt is corresponding from equipment.
Further, the excitation space in step 2, which divides, uses the EP algorithm based on equivalence class partition.
Further, the EP algorithm based on equivalence class partition is divided into 3 sub-steps；
A, to divide to entire excitation space, the obtained excitation in each level-one subspace is having the same active
Main equipment number；
B, the excitation initiation having the same in each second level subspace to obtain to level-one subspace further division
The main equipment set of bus excitation；
C, the excitation principal and subordinate having the same in each three-level subspace to obtain to second level subspace further division
Device drives corresponding relationship.
Further, excitation space tree ergodic algorithm is optimization depth-first ODFT algorithm, using leaf node Si,j,k
Subscript triple<i, j, k>representated by indefinite system long number be incremented by realize: k first is incremented by since 1；When k progressively increases to big
In BSi,jSon node number when, be just incremented by j, and k returns to 1；When j progressively increases to being greater than BSiSon node number when, just pass i
Increase, and j returns to 1；When i progressively increases to the son node number for being greater than root node, entire ergodic algorithm terminates, and i, j, k are natural number.
Further, the input stimulus of actual bus interconnection is that the leaf node of excitation space tree passes through bus protocol phase
The BusSti transfer function of pass generates: the function is first to the principal point collection BV for including in leaf nodehIt is traversed and is enlivened
Main equipment；Then main equipment vh is enlivened for eachi, obtained by directed edge function BE corresponding from equipment BE (vhi)；
Then it is randomly provided from equipment BE (vhi) in offset address, data flow direction, byte is enabled and writes the detailed information of data；
Finally the bus driver function of the bottom is called to complete the initiation of bus excitation according to all excitation informations.
3. beneficial effect
Compared with the prior art, the present invention has the advantages that
(1) present invention is one independently of specific bus protocol and the expansible excitation generation side unrelated with integrated equipment number
Method.This method is then based on model and carries out abstract excitation generation, finally just pass through bus and assist first by bus abstract at mathematical model
It discusses relevant transfer function and generates actual input stimulus.
(2) present invention can be realized the irredundant uniform fold of excitation space, since the strategy passes through abstract and equivalence class
The excitation space of script flattening is converted to hierarchical tree excitation space by the method for division, then passes through time of structuring
Going through algorithm ensures the irredundant uniform fold of excitation space under specific coverage rate.
(3) present invention can efficiently solve tradition based on the random difficult extension of multicore bus bar verifying, redundancy and dead
The problem of angle etc. unevenly covers, there is good practical application value.
Detailed description of the invention
Fig. 1 is bus system structure chart；
Fig. 2 is the oriented bipartite model of bus；
Fig. 3 is the excitation space tree ISST of bus；
Fig. 4 is that optimization depth-first traversal ODFT is realized；
The relationship of Fig. 5 difference incentive program downlink coverage rate and excitation number.
Specific embodiment
With reference to the accompanying drawings of the specification and specific embodiment, the present invention is described in detail.
Embodiment 1
Present solution provides a kind of multicore interconnections of the irredundant uniform fold of excitation space to verify excitation generation strategy,
Include the following steps:
Step 1 is established and is based on oriented bipartite graph (Directed Bipartite Graph, DBG=< BVh,BVs,BE>)
The abstract excitation model of multicore interconnection；Wherein principal point collection BVhIn point and be integrated in bus main equipment and correspond；From
Point set BVsIn point and be integrated in bus from equipment correspond；BVhMiddle vertex v hiTo BVsMiddle vertex v siBetween there are
To side eij=< vhi,vsj> necessary and sufficient condition be vhiThe accessible vs of excitation that corresponding main equipment is initiatediIt is corresponding from equipment.
Step 2, using the EP algorithm based on equivalence class partition by the excitation space of script flattening be converted into 3 layers swash
Encourage space tree.Wherein EP algorithm is divided into 3 sub-steps: the first step is to divide to entire excitation space, each of obtains one
Excitation in grade subspace having the same enlivens main equipment number；Second step is to obtain to level-one subspace further division
The excitation main equipment set having the same for initiating bus excitation in each second level subspace；Third step is to second level subspace
Further division, the obtained excitation in each three-level subspace master-slave equipment having the same drive corresponding relationship.
Step 3 traverses the leaf node collection of excitation space tree using optimization depth-first ODFT algorithm, obtains
Irredundant all standing leaf node sequence comprising high-level excitation information.Wherein ODFT algorithm uses leaf node Si,j,kSubscript
Triple<i, j, k>representated by indefinite system long number be incremented by realize: k first is incremented by since 1；When k progressively increases to being greater than
BSi,jSon node number when, be just incremented by j, and k returns to 1；When j progressively increases to being greater than BSiSon node number when, just make i be incremented by,
And j returns to 1；When i progressively increases to the son node number for being greater than root node, entire ergodic algorithm terminates.
Each leaf node is converted by step 4 using bus protocol relevant BusSti (LeafNode) transfer function
The input stimulus of actual bus interconnection.The function is first to the principal point collection BV for including in leaf nodehIt is traversed and is enlivened
Main equipment；Then main equipment vh is enlivened for eachi, obtained by directed edge function BE corresponding from equipment BE (vhi)；
Then it is randomly provided from equipment BE (vhi) in offset address, data flow direction, byte are enabled and write data and (need when write operation
Will) etc. detailed information；Finally the bus driver function of the bottom is called to complete the initiation of bus excitation according to all excitation informations.
Below in conjunction with specific embodiment, it is illustrated；
It is an exemplary multicore AXI bus type interconnection FooBus shown in Fig. 1, only there are two kernel CoreA in the system
And CoreB, an input equipment (UART), an output equipment (VGA is shown) and main memory Memory.Two kernels with it is other
Three non-core intermodules realize interconnection by bus FooBus, and assume that any kernel can be non-by FooBus access three
Any one of kernel module.For core interconnection FooBus, main equipment is two kernels CoreA and CoreB, from setting
3 are had, is UART, VGA and Memory respectively.
One, abstract work is first carried out:
Abstract excitation model BDBG=< BV of example bus FooBus is constructed firsth,BVs, BE >, specific abstraction rule is such as
Under:
1) principal point collection BVh: each main equipment (i.e. kernel) is abstracted into the set constituted behind vertex；
2) from point set BVs: each the set constituted behind vertex is abstracted into from equipment (i.e. peripheral hardware)；
3) directed edge collection BE:BVhMiddle vertex v hiTo BVsMiddle vertex v siBetween there are directed edge eij=< vhi,vsj> fill
Wanting condition is vhiCorresponding kernel motivates accessible vsiCorresponding peripheral hardware.
According to above-mentioned rule, DBG model such as Fig. 2 of above-mentioned example bus FooBus, thirdly element is respectively
BVh={ CoreA, CoreB }, BVs={ Memory, UART, VGA }
With
Two, division work is carried out after:
After obtaining DBG model, affairs are driven to be arranged to form all principals and subordinates with the EP algorithm based on equivalence class partition
Bus input stimulus space (ISS, Input Stimuli Space) divided, the ISS of former flattening is converted into tying
The input stimulus space tree (ISST, Input Stimuli Space Tree) of structure.Before introducing EP algorithm, 3 are first defined
A important parameter.
NHD (Number of Host Devices): all main equipment numbers；
NSD (Number of Slave Devices): all from number of devices；
NAH (Number of Active Host Devices): instantly active main equipment number.
Obviously there is lower relation of plane:
1≤NAH≤NHD (1)
3 steps of EP algorithm point, detailed process are as follows:
Step 1: dividing to entire ISS, the foundation of division is each subset NAH having the same.According to formula (1),
ISS is divided into NHD subset, i.e. EP (BISS)={ BS1,BS2…BSNHD, wherein subset BSiSubscript i indicate in it
All excitation numbers, value range are i (1≤i≤NHD)；
Step 2: for each set BSiIt is divided, the foundation of division is that the master of bus excitation is initiated in each subset
Cluster tool is determining.According to arrangement and combination, BSiIt is divided intoA subset (is chosen from NHD main equipment
I), i.e. EP (BSi)={ BSi,1,BSi,2..., wherein subset BSi,jThere are two subscripts: first i expression is to BSiDivision；
I (1≤i≤NHD), second j is feature number, and value range is
Step 3: for each set BSi,jIt is divided, the foundation of division is the master-slave equipment driving in each subset
Corresponding relationship is determining.Remember BSi,jThe occupied i main equipment of underexcitation be respectivelySince different masters set
The slave equipment of standby driving can be identical, then BSi,jIt is divided intoA subset (deg+
(v) out-degree of the midpoint DBG v is indicated), i.e. EP (BSi,j)={ BSi,j,1,BSi,j,2..., wherein subset BSi,j,kThere are three subscripts:
The first two i,jExpression is to BSi,jDivision；Third k is feature number, and value range is
By EP algorithm, the ISS of originally flattening is converted into 3 layers of ISST, and each leaf node of ISST is with regard to generation
One, table abstract excitation because which depict there is which main equipment being movable, and gives each movable main equipment and is driven
Dynamic slave equipment.To FooBus, due to NHD=2, NSD=3, ISST is as shown in Figure 3.
The wherein meaning of each node layer such as following table
Each node layer meaning of the ISST of table 1FooBus
| Node | Meaning |
| BS1 | Monokaryon hair excitation |
| BS2 | Double-core hair excitation |
| BS1,1 | CoreA hair excitation |
| BS1,2 | CoreB hair excitation |
| BS2,1 | CoreA and CoreB are concurrently motivated |
| BS1,1,1 | <CoreA,Memory> |
| BS1,1,2 | <CoreA,UART> |
| BS1,1,3 | <CoreA,VGA> |
| BS1,2,1 | <CoreB,Memory> |
| BS1,2,2 | <CoreB,UART> |
| BS1,2,3 | <CoreB,VGA> |
| BS2,1,1 | <CoreA,Memory>,<CoreB,Memory> |
| BS2,1,2 | <CoreA,UART>,<CoreB,Memory> |
| BS2,1,3 | <CoreA,VGA>,<CoreB,Memory> |
| BS2,1,4 | <CoreA,Memory>,<CoreB,UART> |
| BS2,1,5 | <CoreA,UART>,<CoreB,UART> |
| BS2,1,6 | <CoreA,VGA>,<CoreB,UART> |
| BS2,1,7 | <CoreA,Memory>,<CoreB,VGA> |
| BS2,1,8 | <CoreA,UART>,<CoreB,VGA> |
| BS2,1,9 | <CoreA,VGA>,<CoreB,VGA> |
Three, it traverses:
After obtaining excitation space tree ISST, the structuring followed by tree node is traversed, to realize excitation space
Irredundant uniform fold.Due in traditional computer algorithm to the traversal of tree node can using depth-first traversal (DFT,
Depth First Traversal), but due to only having leaf node to contain completely abstract excitation information in ISST, so
In order to reduce the traversal of unnecessary node, the invention proposes the ergodic algorithm ODFT of optimization.ODFT is odd number discrete fourier
Transformation.And according to EP algorithm, each leaf node Si,j,kCan be by its subscript triple<i, j, k>carry out unique index are determined, therefore
The traversal of leaf node is equivalent to again to<i, j, k>triple traversal.
The characteristics of ODFT, is order traversal and only traverses the leaf node of excitation space tree, specifically uses leaf node Si,j,k
Subscript triple<i, j, k>representated by indefinite system long number be incremented by realize.Only because each n omicronn-leaf in excitation space tree
The son node number of child node is not fixed and invariable, but dynamic differs.So long number<i herein, j, k>each not
It is the fixed system such as traditional 10 systems or 16 systems, but indefinite system, specific n-th radix depend on preceding n-1 position
Set current value.Algorithm is divided into following 4 step:
1) k is first incremented by since 1；
2) when k progressively increases to being greater than BSi,jSon node number when, be just incremented by j, and k returns to 1；
3) when j progressively increases to being greater than BSiSon node number when, be just incremented by i, and j returns to 1；
4) when i progressively increases to the son node number for being greater than ISST root node, entire ergodic algorithm terminates.
Algorithm implementation process is summarized as shown in Figure 4.
Four, it converts:
After obtaining the irredundant all standing leaf node sequence comprising high-level excitation information by ODFT, next adopt
Each leaf node is converted into multicore bus mould with the protocol-dependent BusSti of physical bus (LeafNode) transfer function
The actual input stimulus of block.It realizes that details is as follows:
1) first to the principal point collection BV for including in leaf nodehIt is traversed to obtain and enlivens main equipment；
2) main equipment vh then is enlivened for eachi, obtained by directed edge function BE corresponding from equipment BE
(vhi)；
3) it is then randomly provided from equipment BE (vhi) in offset address addr, data flow direction dir (read/write), byte
It enables wstrb/rstrb and writes the detailed information such as data wdata (needing when write operation)；
4) finally according to all excitation informations call following bottoms AXI bus driver function (write is called when writing,
Read is called when reading) complete the initiation that bus motivates.
In order to assess beneficial effects of the present invention, Experimental comparison 2 kinds of different incentive program (traditional arbitrary excitation, ODFT
Structuring excitation) under the row coverage value of FooBus and the relationship of excitation number, as a result such as Fig. 5.By result as it can be seen that compared to tradition with
Machine excitation, ODFT can be such that row coverage rate quickly restrains, and excitation number when convergence reduces 22.3%.
Schematically the invention and embodiments thereof are described above, description is not limiting, not
In the case where spirit or essential characteristics of the invention, the present invention can be realized in other specific forms.Institute in attached drawing
What is shown is also one of the embodiment of the invention, and actual structure is not limited to this, any attached in claim
Icon note should not limit the claims involved.So not departed from if those of ordinary skill in the art are inspired by it
In the case where this creation objective, frame mode similar with the technical solution and embodiment are not inventively designed, it should all
Belong to the protection scope of this patent.In addition, one word of " comprising " is not excluded for other elements or step, "one" word before the component
It is not excluded for including " multiple " element.The multiple element stated in claim to a product can also by an element by software or
Person hardware is realized.The first, the second equal words are used to indicate names, and are not indicated any particular order.
Claims (7)
1. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space, steps are as follows:
Step 1 establishes the abstract excitation model of the multicore interconnection based on oriented bipartite graph；
Originally flat unordered excitation space is converted into 3 layers of excitation space tree by step 2；
Step 3 optimizes depth-first ODFT traversal to excitation space tree, obtains including high-level excitation information without superfluous
Remaining all standing leaf node sequence；
Each leaf node is converted into actual bus interconnection by the relevant BusSti transfer function of bus protocol by step 4
Input stimulus.
2. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 1,
Be characterized in that: the abstract excitation model of multicore interconnection in step 1 is oriented bipartite model DBG=< BVh,BVs, BE >,
Wherein principal point collection BVhIn point and be integrated in bus main equipment and correspond；From point set BVsIn point and be integrated in bus
It is corresponded from equipment；BE is directed edge collection.
3. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 2,
Be characterized in that: BE is that directed edge collection is BVhMiddle vertex v hiTo BVsMiddle vertex v siBetween there are directed edge eij=< vhi,vsj>
Necessary and sufficient condition be vhiThe accessible vs of excitation that corresponding main equipment is initiatediIt is corresponding from equipment.
4. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 1,
Be characterized in that: the excitation space in step 2, which divides, uses the EP algorithm based on equivalence class partition.
5. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 4,
Be characterized in that: the EP algorithm based on equivalence class partition is divided into 3 sub-steps；
A, to divide to entire excitation space, the excitation active master having the same in obtained each level-one subspace is set
Standby number；
B, the excitation initiation bus having the same in each second level subspace to obtain to level-one subspace further division
The main equipment set of excitation；
C, the excitation master-slave equipment having the same in each three-level subspace to obtain to second level subspace further division
Drive corresponding relationship.
6. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 1,
Be characterized in that: excitation space tree ergodic algorithm is optimization depth-first ODFT algorithm, using leaf node Si,j,kSubscript triple <
I, j, k > representated by indefinite system long number be incremented by realize: k first is incremented by since 1；When k progressively increases to being greater than BSi,jSon section
When points, just it is incremented by j, and k returns to 1；When j progressively increases to being greater than BSiSon node number when, be just incremented by i, and j returns to 1；
When i progressively increases to the son node number for being greater than root node, entire ergodic algorithm terminates, and i, j, k are natural number.
7. a kind of multicore interconnection verification method of the irredundant uniform fold of excitation space according to claim 1,
It is characterized in that:
The input stimulus of actual bus interconnection is that the leaf node of excitation space tree passes through the relevant BusSti conversion of bus protocol
Function generates: the function is first to the principal point collection BV for including in leaf nodehIt is traversed to obtain and enlivens main equipment；Then for
Each enlivens main equipment vhi, obtained by directed edge function BE corresponding from equipment BE (vhi)；Then it is randomly provided from setting
Standby BE (vhi) in offset address, data flow direction, byte is enabled and writes the detailed information of data；Finally according to all excitations
Information calls the bus driver function of the bottom to complete the initiation that bus motivates.
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| CN110750957B (en) * | 2019-10-30 | 2024-05-24 | 南京宁麒智能计算芯片研究院有限公司 | Cache system verification method of high-efficiency multi-core RISC-V processor |
| CN111858217A (en) * | 2020-07-24 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Hierarchical verification method, platform, equipment and storage medium |
| CN111858217B (en) * | 2020-07-24 | 2022-07-15 | 浪潮(北京)电子信息产业有限公司 | Hierarchical verification method, platform, equipment and storage medium |
| CN114818560A (en) * | 2022-03-07 | 2022-07-29 | 江苏汤谷智能科技有限公司 | Chip development verification system platform based on simulation technology |
| CN114818560B (en) * | 2022-03-07 | 2024-02-13 | 江苏汤谷智能科技有限公司 | Chip development verification system platform based on simulation technology |
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Application publication date: 20190510 |