CN109728163B - Resistive random access memory and manufacturing method thereof - Google Patents
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Abstract
The embodiment of the application discloses a resistive random access memory and a manufacturing method thereof, wherein a substrate is provided, a metal plug is formed on the substrate as a lower electrode, a resistive random function layer, an upper electrode layer and an interconnection metal layer are formed on the lower electrode, and the interconnection metal layer, the upper electrode layer and the resistive random function layer are etched according to the position of the metal plug, so that the interconnection metal layer, the upper electrode layer, the resistive random function layer and the metal plug are aligned. In the embodiment of the application, the interconnection metal layer, the upper electrode layer and the resistance change function layer are etched at one time, so that the self alignment of the three film layers can be realized, in terms of technology, even if the area of the three film layers is larger than that of the metal plug, the realization of a device is not influenced, and compared with the prior art that the barrier layer is formed on the upper electrode layer, the barrier layer is etched to form a through hole aligned with the metal plug, and in terms of forming the interconnection metal layer in the through hole, the alignment requirement is lower, so that the yield is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a resistive random access memory and a method for fabricating the same.
Background
With the popularity of portable personal devices, nonvolatile memory has become a development focus in the semiconductor industry because of its advantages of maintaining a memory state and operating with low power consumption when no power is supplied. The Flash memory (Flash) is still the main stream of the non-volatile memory in the market at present, but the Flash memory has the defects of overlarge operation voltage, slow operation speed, insufficient durability, insufficient holding time due to continuous thinning of a tunneling oxide layer in the process of shrinking the size of a device and the like, so that the research and development focus of the prior art is gradually turned to a novel non-volatile memory capable of replacing the Flash memory.
Unlike the charge storage mechanism of conventional Flash, the resistive random access memory (Resistive Random Access Memory, RRAM) is a non-charge storage mechanism, so that the problem of charge leakage caused by thinning of the tunneling oxide layer in Flash can be solved, and the resistive random access memory has better scalability. The resistive random access memory has the advantages of low write operation voltage, short write and erase time, long memory time, nondestructive reading, multi-value storage, simple structure, high storage density and the like, so the resistive random access memory gradually becomes a research focus in the current novel nonvolatile memory device, is hopeful to replace DRAM, SRAM, flash and the like to become a general memory, and is a powerful competitor for the future new generation of memory technology.
The basic memory cell of the RRAM is a resistor with a Metal-Insulator-Metal (MIM) structure, and the resistance of the MIM structure can be switched between a high resistance state and a low resistance state by means of voltage or current pulses, so that 0 and 1 are stored, and data are written and erased. The insulator is a resistive layer material, which can be perovskite oxide, transition metal binary oxide, solid electrolyte material or organic material, etc.
In the preparation process of RRAM, MIM structure can be formed on the substrate, then the MIM structure is etched, through holes formed by etching are used for interconnection, along with the gradual reduction of the size of RRAM memory cells, the etching difficulty is increased, and once the etching is deviated, the device performance is deviated. Thus, it is more difficult to form a higher quality RRAM device in the prior art.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a resistive random access memory and a manufacturing method thereof, which provide convenience for the manufacturing process of the resistive random access memory and improve the yield of devices.
The embodiment of the application provides a manufacturing method of a resistance random access memory, which comprises the following steps:
providing a substrate, wherein a metal plug is formed on the substrate to serve as a lower electrode;
sequentially forming a resistance change function layer, an upper electrode layer and an interconnection metal layer on the lower electrode;
and etching the interconnection metal layer, the upper electrode layer and the resistance change function layer at one time according to the positions of the metal plugs so as to align the interconnection metal layer, the upper electrode layer, the resistance change function layer and the metal plugs.
Optionally, the resistorThe variable function layer comprises: hfO (HfO) 2 、Al 2 O 3 、TaO x 、TiO x At least one of them.
Optionally, the metal plug is a tungsten plug.
Optionally, the upper electrode layer is a titanium nitride layer.
Optionally, the interconnect metal layer is an aluminum layer.
Optionally, the forming a resistive function layer, an upper electrode layer and an interconnection metal layer on the lower electrode sequentially includes:
sequentially forming a resistive function layer and an upper electrode layer on the lower electrode;
etching the resistive function layer and the upper electrode layer on the interconnected metal plugs to comprise the interconnected metal plugs;
an interconnect metal layer is formed on the upper electrode layer and on the exposed metal plug.
Optionally, an MOS transistor is disposed on the substrate, the MOS transistor includes a source/drain, and the metal plug is formed by:
forming a keyhole above a source/drain electrode of the MOS device;
and filling a first electrode material into the bolt hole to form a metal plug serving as a first electrode.
Optionally, the filling the first electrode material into the plug hole to form a metal plug as the first electrode includes:
and filling a first electrode material into the bolt hole, and flattening the first electrode material to form a metal plug serving as a first electrode.
The embodiment of the application also provides a resistive random access memory, which comprises:
a metal plug formed on the substrate as a lower electrode;
the resistive function layer, the upper electrode layer and the interconnection metal layer are sequentially formed on the lower electrode; the resistive function layer, the upper electrode layer and the interconnection metal layer are etched at one time according to the position of the metal plug and aligned with the metal plug.
Optionally, the resistive function layer includes: hfO (HfO) 2 、Al 2 O 3 、TaO x 、TiO x At least one of them.
In the embodiment of the application, a substrate is provided, a metal plug is formed on the substrate as a lower electrode, a resistive function layer, an upper electrode layer and an interconnection metal layer are formed on the lower electrode, and the interconnection metal layer, the upper electrode layer and the resistive function layer are etched according to the position of the metal plug, so that the interconnection metal layer, the upper electrode layer, the resistive function layer and the metal plug are aligned. In the embodiment of the application, the interconnection metal layer, the upper electrode layer and the resistance change function layer are etched at one time, so that the self alignment of the three film layers can be realized, in terms of technology, even if the area of the three film layers is larger than that of the metal plug, the realization of a device is not influenced, and compared with the prior art that the barrier layer is formed on the upper electrode layer, the barrier layer is etched to form a through hole aligned with the metal plug, and in terms of forming the interconnection metal layer in the through hole, the alignment requirement is lower, so that the yield is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a flow chart of a method for manufacturing a resistive random access memory according to an embodiment of the present application;
fig. 2 to 7 are schematic structural diagrams corresponding to a manufacturing process of a resistive random access memory according to an embodiment of the present application;
fig. 8 is a schematic diagram of high-low resistance state distribution in a resistive random access memory according to an embodiment of the present application.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not to scale for the sake of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
In the conventional method for forming the resistive random access memory, a lower electrode may be formed on a substrate, wherein the lower electrode may be a metal plug, a resistive function layer and an upper electrode are formed on the lower electrode, then an insulating layer is formed on the upper electrode, and the insulating layer is etched to form a via aligned with the lower electrode, and an interconnection metal is formed in the via, so that the interconnection metal may be connected to an external circuit to supply power to the resistive random access memory.
However, the inventors have found that etching the insulating layer to form a via hole aligned with the lower electrode is technically difficult to achieve, and if an error occurs in the alignment between the via hole and the lower electrode, the device may fail, so that the yield of the device is low.
Based on this, in the embodiment of the application, there is provided a resistive random access memory and a manufacturing method thereof, by providing a substrate, forming a metal plug as a lower electrode on the substrate, forming a resistive function layer, an upper electrode layer and an interconnection metal layer on the lower electrode, and etching the resistive function layer, the upper electrode layer and the interconnection metal layer according to the position of the metal plug so as to align the interconnection metal layer, the upper electrode layer, the resistive function layer and the metal plug. In this embodiment of the present application, the interconnection metal layer, the upper electrode layer and the resistive function layer are etched once, so that self alignment of the three film layers can be achieved, in terms of technology, even if the area of the three film layers is larger than that of the metal plug, the implementation of the device is not affected, and therefore, compared with the prior art that the barrier layer is formed on the upper electrode, the barrier layer is etched to form a through hole aligned with the metal plug, and in terms of forming the interconnection metal layer in the through hole, the alignment requirement in this embodiment of the present application is lower, so that the yield is improved.
The following describes a resistive random access memory and a manufacturing method thereof in detail and exemplarily described with reference to the accompanying drawings, and referring to fig. 1, a flowchart of a manufacturing method of a resistive random access memory provided in an embodiment of the present application is shown, and the method includes:
s101, providing a substrate.
Referring to fig. 2, a schematic structure diagram corresponding to a manufacturing process of a resistive random access memory is shown, and a bottom electrode 111 is formed on a substrate 110, wherein the bottom electrode 111 may be a metal plug, and the metal plug may be a tungsten plug. The lower electrode 111 may be separated by a passivation layer 112, and the material forming the passivation layer 112 may be SiO 2 Other insulating materials are also possible.
In some possible embodiments, the base 110 may be a substrate commonly used in the art, such as a silicon substrate. Of course, in the present embodiment, the substrate 110 may further include, but is not limited to, other semiconductors or compound semiconductors, such as SiC, gaAs, etc. In practice, a passivation layer may be formed on the substrate 110, and then the passivation layer is etched to form a via, and a metal plug is formed in the via.
In some possible embodiments, a MOS device may be preset on the substrate 110, where the MOS device includes a source/drain, and when in implementation, a metal plug may be formed above the source/drain, where the formed metal plug is electrically connected to the source/drain of the MOS device, so as to control the formed resistive random access memory through the MOS device.
As an example, the invention may employ CMOS processes to form metal plugs over the source/drain of the MOS device. Specifically, a keyhole can be formed on the passivation layer above the source/drain electrode of the MOS device by photoetching and etching. The bolt hole penetrates from the upper surface of the MOS device to the upper surface of the source/drain electrode. That is, the peg holes penetrate the upper and lower surfaces of the passivation layer.
After the formation of the key hole, the key hole may be filled with a lower electrode metal material to form a metal plug, and the lower electrode metal material may be deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) so that the lower electrode metal material fills the entire key hole. In practice, the bottom electrode metal material may be formed outside the stud holes, and at this time, the excess bottom electrode metal material may be removed by chemical mechanical planarization, i.e., CMP, to form metal plugs. The metal plug is used as the bottom electrode of the resistive random access memory.
After the formation of the keyhole, a metal plug may be formed by a standard interconnect via process, and specifically, a diffusion barrier layer may be formed at the bottom and around the keyhole, and then the keyhole may be filled with a lower electrode material. The material of the diffusion barrier layer can be Ti or TiN, the thickness range of the diffusion barrier layer can be 3 nm-50 nm, the Ti can be formed by a physical vapor deposition method (Physical Vapor Deposition, PVD), and the TiN can be formed by a Metal-organic chemical vapor deposition method (Metal-organic Chemical Vapor Deposition, MOCVD). The bottom electrode material may be tungsten, filling the stud holes with tungsten by CVD deposition.
S102, a resistive function layer 120, an upper electrode layer 130, and an interconnection metal layer 140 are sequentially formed on the lower electrode 111, as shown with reference to fig. 3, 4, and 5.
Optionally, before the resistive function layer 120 is formed on the lower electrode 111, the surface of the film layer on the substrate 110 may be treated, so as to improve the quality of the contact surface between the resistive function layer 120 and the lower electrode 111. First, the surface of the film may be subjected to a degassing treatment, and specifically, the substrate 110 may be placed in an environment at a temperature of 150 to 350 degrees celsius for a duration of 0.5 to 2 minutes, so as to remove gas molecules attached to the surface of the film. The surface of the film may then be subjected to a Pre-clean process, specifically, by argon ions (Ar + ) And the film layer is entirely removed by a reverse sputtering mode to a certain thickness which can be 10 nanometers so as to remove the oxide layer on the surface of the metal plug.
Referring to FIG. 3, in an embodiment of the present application, the resistive switching layer 120 may be a transition metal binary oxide, such as HfO 2 、Al 2 O 3 、TaO x 、TiO x As an example, the resistive switching functional layer 120 may be HfO 2 Layer 121 and TaO x Layer 122.
Specifically, hfO 2 Layer 121 may have a thickness of 3-15 nanometers and may be formed by atomic layer deposition (Atomic layer deposition, ALD), hfO 2 The thickness of layer 121 can be precisely controlled according to the number of growth cycles of ALD. In practice, the deposition temperature may be 300 degrees celsius; chemical source 1 may be TEMAH of the formula: [ (CH) 3 )C 2 H 5 N] 4 Hf, source heating temperature 80 degrees Celsius; the chemical source 2 may be H 2 O liquid source (self vapor pressure, no carrier gas).
Specifically, taO x The layer 122 has a resistivity of about 0.7mΩ cm and a thickness of 10-70 nm and may be formed by physical vapor deposition (Physical Vapor Deposition, PVD) sputtering. The specific reaction sputtering deposition process conditions are as follows: ar:36sccm; o (O) 2 :4sccm; RF1power:400W; base bias RF power: 25W; pressure: 3mTorr.
In the embodiment of the present application, the material forming the upper electrode layer 130 may be at least one of the metal materials Pt, W, ru, al or the conductive metal compound TiN, taN, irO 2 At least one of ITO and IZO, the upper electrode layer 130 may be formed over the resistive functional layer 120 using any one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering methods. Taking TiN as an example of the upper electrode layer 130, the upper electrode layer 130 may be formed to have a thickness ranging from 10nm to 100nm.
After forming the upper electrode layer 130, the deposited thin film may be annealed to improve the quality of the thin film, wherein an annealing atmosphere may be in a helium atmosphere, an annealing pressure may be 50Torr, a susceptor temperature may be 400 ℃, and an annealing time may be 10 to 120 seconds.
Since the resistive function layer 120 is a function layer located between the upper electrode layer 130 and the lower electrode layer 111, at a position where interconnection of the upper electrode layer 130 and the lower electrode layer 111 is required, the resistive function layer 120 and the upper electrode layer 130 may also be etched to expose an interconnection metal plug at the position to connect the upper electrode layer 130 and the lower electrode layer 111 through the interconnection metal. Referring to fig. 4, since etching is only required to expose the lower electrode layer 111 of the interconnect, the etched area may be larger than the cross-sectional area of the metal plug. Of course, the area of the etched region can be smaller than the cross-sectional area of the plug and can be equal to the cross-sectional area of the metal plug, so that the requirements on photoetching and etching are lower, and the process difficulty can be reduced.
Referring to fig. 5, an interconnect metal layer 140 is deposited on the upper electrode layer 130, and the deposited interconnect metal layer 140 may cover over the upper electrode layer 130 and over the exposed lower electrode layer 111 and passivation layer 112. Specifically, interconnect metal layer 140 may be a standard aluminum interconnect metal layer structure.
And S103, etching the interconnection metal layer 140, the upper electrode layer 130 and the resistance change function layer 120 at one time according to the positions of the metal plugs so as to align the interconnection metal layer 140, the upper electrode layer 130, the resistance change function layer 120 and the metal plugs.
The interconnection metal layer 140, the upper electrode layer 130 and the resistive function layer 120 are etched at one time, and may be etched by photolithography. Referring to fig. 6, the interconnect metal layer 140, the upper electrode layer 130, and the resistive function layer 120 are etched at one time, and self-alignment of the interconnect metal 140, the upper electrode layer 130, and the resistive function layer 120 may be achieved.
Specifically, the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140, which are not over the metal plugs, may be etched to form trenches for separating the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140 of different memory cells, and the etched area may be smaller than the area of the passivation layer separating the metal plugs. That is, for the metal plugs that are not directly connected to the interconnect metal layer, the resistive function layer 120, the upper electrode layer 130, and the interconnect metal layer 140 remaining thereon may be the same in size and may be all larger than the cross-sectional area of the metal plug, and the effective area of the memory cell formed is based on the minimum cross-sectional area of the metal plug, without affecting the performance of the device.
Referring to fig. 7, after the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140 are etched to form a trench, a passivation layer 150 may be further formed in the trench, and the passivation layer 150 may be SiO2 and/or SiN.
In this embodiment of the present application, the passivation layer 150 is formed, that is, indicates that the preparation of the resistive random access memory is completed, in order to verify that the method for manufacturing the resistive random access memory provided in this embodiment of the present application is feasible, the test is further performed on the resistive random access memory formed by the preparation, and referring to fig. 8, the distribution of high and low resistance states of the resistive random access memory formed by the method for manufacturing the resistive random access memory provided in this embodiment of the present application is shown, where the abscissa is the number of test cycles of the resistive random access memory, and the ordinate is the resistance values of the high resistance state and the low resistance state of the resistive random access memory, and the high and low resistance states of the resistive random access memory have 10 times of the window, which indicates that the resistive random access memory has good performance.
In the embodiment of the application, a manufacturing method of a resistive random access memory is provided, a substrate is provided, a metal plug is formed on the substrate as a lower electrode, a resistive function layer, an upper electrode layer and an interconnection metal layer are formed on the lower electrode, and etching is performed on the resistive function layer, the upper electrode layer and the interconnection metal layer according to the position of the metal plug, so that the interconnection metal layer, the upper electrode layer, the resistive function layer and the metal plug are aligned. In this embodiment of the present application, the interconnection metal layer, the upper electrode layer and the resistive function layer are etched once, so that self alignment of the three film layers can be achieved, in terms of technology, even if the area of the three film layers is larger than that of the metal plug, the implementation of the device is not affected, and therefore, compared with the prior art that the barrier layer is formed on the upper electrode, the barrier layer is etched to form a through hole aligned with the metal plug, and in terms of forming the interconnection metal layer in the through hole, the alignment requirement in this embodiment of the present application is lower, so that the yield is improved.
Based on the above method for manufacturing the resistive random access memory, the embodiment of the present application further provides a resistive random access memory, and a schematic structure diagram of the resistive random access memory may be shown in fig. 7, including:
the metal plug formed on the substrate 110 serves as the lower electrode 111, and the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140 are sequentially formed on the lower electrode 111, wherein the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140 are etched at one time according to the position of the metal plug and aligned with the metal plug.
The substrate 110 may be provided with a MOS device in advance, where the MOS device includes a source/drain. The metal plug may be formed over the source/drain electrode, and the formed metal plug is electrically connected to the source/drain electrode of the MOS device so as to control the formed resistive random access memory through the MOS device.
The lower electrode 111 may be separated by a passivation layer 112, and the material forming the passivation layer 112 may be SiO 2 Other insulating materials are also possible.
The resistive switching functional layer 120 may be a transition metal binary oxide, such as HfO 2 、Al 2 O 3 、TaO x 、TiO x As an example, the resistive switching functional layer 120 may be HfO 2 Layer 121 and TaO x Layer 122. Since the resistive function layer 120 is a function layer located between the upper electrode layer 130 and the lower electrode layer 111, at a position where interconnection of the upper electrode layer 130 and the lower electrode layer 111 is required, a metal plug of the interconnection at the position may also be exposed to connect the upper electrode layer 130 and the lower electrode layer 111 through the interconnection metal.
The material forming the upper electrode layer 130 may be at least one of metal materials Pt, W, ru, al or conductive metal compound TiN, taN, irO 2 At least one of ITO and IZO.
An interconnect metal layer 140 may overlie the upper electrode layer 130 and overlie the exposed lower electrode layer 111 and passivation layer 112. Specifically, interconnect metal layer 140 may be a standard aluminum interconnect metal layer structure.
The resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140, which are not over the metal plugs, are etched to form trenches, thereby separating the resistive function layer 120, the upper electrode layer 130, and the interconnection metal layer 140 of different memory cells, and the etched area may be smaller than the area of the passivation layer separating the metal plugs. That is, for the metal plugs that are not directly connected to the interconnect metal layer, the resistive function layer 120, the upper electrode layer 130, and the interconnect metal layer 140 remaining thereon may be the same in size and may be all larger than the cross-sectional area of the metal plug, and the effective area of the memory cell formed is based on the minimum cross-sectional area of the metal plug, without affecting the performance of the device.
A passivation layer 150 is formed in the formed trench, the passivation layer 150 may be SiO2 and/or SiN, the SiO2 being formed higher than the upper electrode layer, the SiN being formed flush with the interconnect metal layer.
In the embodiment of the application, a resistive random access memory is provided, a metal plug formed on a substrate is used as a lower electrode, and a resistive function layer, an upper electrode layer and an interconnection metal layer are sequentially formed on the lower electrode, wherein the resistive function layer, the upper electrode layer and the interconnection metal layer are etched at one time according to the position of the metal plug and are aligned with the metal plug. In this embodiment of the present application, the interconnection metal layer, the upper electrode layer and the resistive function layer are etched once, so that self alignment of the three film layers can be achieved, in terms of technology, even if the area of the three film layers is larger than that of the metal plug, the implementation of the device is not affected, and therefore, compared with the prior art that the barrier layer is formed on the upper electrode, the barrier layer is etched to form a through hole aligned with the metal plug, and in terms of forming the interconnection metal layer in the through hole, the alignment requirement in this embodiment of the present application is lower, so that the yield is improved.
The references to "first" in the names of "first … …", "first … …", etc. in the embodiments of the present application are only used for name identification, and do not represent the first in sequence. The rule applies equally to "second" etc.
From the above description of embodiments, it will be apparent to those skilled in the art that all or part of the steps of the above described example methods may be implemented in software plus general hardware platforms. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a storage medium, such as a read-only memory (ROM)/RAM, a magnetic disk, an optical disk, or the like, including several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to perform the methods described in the embodiments or some parts of the embodiments of the present application.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the method embodiments and the apparatus embodiments, since they are substantially similar to the system embodiments, the description is relatively simple, and reference is made to the partial description of the system embodiments for relevant points. The above-described apparatus and system embodiments are merely illustrative, in which the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed across multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the scope of the present application. It should be noted that modifications and adaptations to the present application may occur to one skilled in the art without departing from the scope of the present application.
Claims (9)
1. A method of manufacturing a resistive random access memory, the method comprising:
providing a substrate, wherein a metal plug is formed on the substrate and used as a lower electrode, and the metal plug comprises a first interconnection metal plug and a second interconnection metal plug;
sequentially forming a resistance change function layer and an upper electrode layer on the lower electrode, etching the resistance change function layer and the upper electrode layer on the first interconnection metal plug to expose the first interconnection metal plug, and forming an interconnection metal layer on the upper electrode layer and the exposed first interconnection metal plug;
and etching the interconnection metal layer, the upper electrode layer and the resistance change function layer at one time according to the position of the second interconnection metal plug so as to align the interconnection metal layer, the upper electrode layer, the resistance change function layer and the second interconnection metal plug.
2. The method of claim 1, wherein the resistive-switching functional layer comprises: hfO (HfO) 2 、Al 2 O 3 、TaO x 、TiO x At least one of them.
3. The method of claim 1, wherein the metal plug is a tungsten plug.
4. The method of claim 1, wherein the upper electrode layer is a titanium nitride layer.
5. The method of claim 1, wherein the interconnect metal layer is an aluminum layer.
6. The method of any one of claims 1-5, wherein a MOS transistor is disposed on the substrate, the MOS transistor including a source/drain, the metal plug being formed by:
forming a keyhole above a source/drain electrode of the MOS device;
and filling a first electrode material into the bolt hole to form a metal plug serving as a first electrode.
7. The method of claim 1, wherein filling the keyhole with a first electrode material to form a metal plug as the first electrode comprises:
and filling a first electrode material into the bolt hole, and flattening the first electrode material to form a metal plug serving as a first electrode.
8. A resistive random access memory, comprising:
a metal plug formed on the substrate as a lower electrode, the metal plug including a first interconnect metal plug and a second interconnect metal plug;
the resistive function layer, the upper electrode layer and the interconnection metal layer are sequentially formed on the lower electrode, and the interconnection metal layer is formed on the upper electrode layer and the first interconnection metal plug; the resistive function layer, the upper electrode layer and the interconnection metal layer are etched at one time according to the position of the second interconnection metal plug and aligned with the second interconnection metal plug.
9. The resistive random access memory of claim 8, wherein the resistive functional layer comprises: is HfO 2 、Al 2 O 3 、TaO x 、TiO x At least one of them.
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