CN109710556B

CN109710556B - Slave device and method for serial communication

Info

Publication number: CN109710556B
Application number: CN201811501631.6A
Authority: CN
Inventors: 黄平
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2018-12-10
Filing date: 2018-12-10
Publication date: 2020-08-11
Anticipated expiration: 2038-12-10
Also published as: JP7212637B2; JP2021536043A; KR102289930B1; KR20200074917A; WO2020118950A1; CN109710556A

Abstract

Disclosed are a slave device and a method for serial communication, the method including: receiving a serial clock signal via a clock signal terminal; receiving data via a data input, the data comprising a plurality of successive bit data; shifting the data in synchronization with a system clock signal to obtain bit data; and latching the bit data in synchronization with the serial clock signal, and transmitting at least a portion of the latched bit data via a data output, wherein the serial clock signal and the system clock signal have a first clock period and a second clock period, respectively, the first clock period being greater than the second clock period. The method shifts bit data synchronously with a system clock signal, latches and sends the pre-shifted bit data synchronously with a serial clock signal, thereby transferring the preparation time of sending data to the front of a sending edge, leading the frequency ratio of the system clock/the serial clock signal to be lower, and improving the transmission rate.

Description

Slave device and method for serial communication

Technical Field

The invention relates to the technical field of data communication, in particular to slave equipment and a slave method for serial communication.

Background

In the prior art, a block diagram of a common design method for transmitting data from a device by using an SPI (Serial Peripheral Interface) is shown in fig. 1. The SPI slave device 100 receives the serial clock signal SCLK via the clock signal terminal SCLK, receives data via the data input terminal MOSI, and transmits data via the data output terminal MISO. The SPI slave device uses a system clock (SYSCLK) with a frequency several times higher than that of the SPI Serial Clock (SCLK) to synchronize and detect an edge of the SPI serial clock signal SCLK, also called a transmission edge, i.e., a transition of a rising edge or a falling edge of the serial clock signal SCLK, in the edge detection module 110, so as to obtain a transmission edge signal. The transmission edge signal is an enable signal ENTX, and only the high level of one cycle of the system clock SYSCLK is asserted. The logic module 120 reads data from the memory module 130 according to the enable signal, shifts one bit of transmission data to the data output terminal MISO, and after shifting one set of data (usually 8 bits), fetches the next set of data from the memory and shifts the data again for transmission.

Fig. 2 is a waveform diagram of the SPI mode 0 data transmission in this method. As shown, the SPI serial clock generally only works when the SPI transmits data (during the active period of the CS), and the fixed level is kept unchanged (even if there is a change, it can be gated by the CS). SPI mode 0 requires the first bit of data to be prepared and output onto data output MISO before the first SPI serial clock transmit edge arrives. Before the SPI serial clock arrives, the SPI serial clock cannot be used to read data from the memory and transmit the first bit data, so the system clock signal SYSCLK is usually used to transmit data.

There are some disadvantages to this data transmission method. In fig. 2, the transmitting edge of the SPI serial clock is synchronized with the system clock SYSCLK across the clock domain, the transmitting edge transition signal of the SPI serial clock is detected, the transition signal is used as the enable signal ENTX to shift the output data, and the data preparation delay ta (miso data preparation delay) is usually 2 to 3 system clock SYSCLK periods (T)_SYSCLK). Another delay is the data transfer delay Tb (MISO PAD/board delay) on the PAD/board. Half cycle (T) of SPI serial clock_SCLKAnd/2) subtracting the data preparation delay Ta and the data on PAD/board transmission delay Tb (MISO PAD/board delay), namely the setup time Tc (MISO setup) of the output data on the receiving end. In one item, the data is fixed at the PAD/board transmission delay Tb, and a larger data preparation delay Ta will make the output data setup time Tc smaller, limiting the increase in transmission rate.

In order to meet the requirement of the setup time of the output data at the receiving end, under the condition that the SPI serial clock frequency (namely the transmission rate) is constant (namely T_SCLKA/2 is constant), a system clock signal SYSCLK with a higher frequency is required to reduce the data preparation delay Ta; or under the condition that the frequency of the system clock signal SYSCLK is certain, the highest frequency of the SPI serial clock which can be supported is lower; this is reflected in a high frequency ratio of system clock SYSCLK/serial clock SCLK.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a slave device and method for serial communication, so as to reduce the frequency ratio of the system clock SYSCLK/serial clock signal SCLK, resulting in better output data setup time.

According to an aspect of the present invention, there is provided a serial communication method for a slave device, including:

receiving a serial clock signal via a clock signal terminal;

receiving data via a data input, the data comprising a plurality of successive bit data;

shifting the data in synchronization with a system clock signal to obtain bit data; and

latching the bit data in synchronization with the serial clock signal, and transmitting at least a portion of the latched bit data via a data output,

wherein the serial clock signal and the system clock signal have a first clock period and a second clock period, respectively, the first clock period being greater than the second clock period.

Optionally, the selected bit data of the data is shifted and latched and transmitted respectively in successive cycles of the serial clock signal.

Optionally, the method further comprises: generating a driving clock signal according to the serial clock signal, wherein the bit data is transmitted at an edge of the driving clock signal.

Optionally, the driving clock signal is obtained by gating and/or phase-shifting the serial clock signal.

Optionally, the step of shifting the data comprises:

delaying at least one second clock cycle in a first clock cycle of the serial clock signal, thereby obtaining an enable signal synchronized with the system clock signal; and

and shifting the data according to the enable signal to obtain bit data.

Optionally, the method further comprises: shifting the bit data to obtain a first bit data according to the enable signal, and latching the first bit data, and transmitting the latched first bit data.

Optionally, the method further comprises: and obtaining a selection signal according to the serial clock signal, wherein the selection signal is used for selectively providing the first bit data and the rest bit data of the data to a data output end for transmission.

Optionally, the bit data is transmitted on a rising edge or a falling edge of the serial clock signal according to an operation mode of the slave device.

Optionally, the first bit of data is sent before or after a first edge of the serial clock signal according to an operating mode of the slave device.

According to another aspect of the present invention, there is provided a slave device for serial communication, the slave device receiving a serial clock signal via a clock signal terminal, receiving data via a data input terminal, and transmitting the data via a data output terminal, the slave device comprising:

the storage module is used for storing the data;

the logic module is coupled with the storage module and used for synchronizing with a system clock signal and shifting the data to obtain bit data;

the first latching module is coupled with the logic module and used for latching first bit data of the data;

the second latch module is coupled with the logic module and used for latching the rest bit data of the data;

a selection signal generation module for obtaining a selection signal synchronized with the serial clock signal;

a selection module, coupled to the first latch module, the second latch module and the selection signal generation module, for providing one of the first bit data and the remaining bit data to the data output terminal according to a selection signal,

Optionally, the method further comprises: and the edge detection module is used for delaying at least one second clock cycle in a first clock cycle of the serial clock signal so as to obtain an enabling signal synchronous with the system clock signal.

Optionally, the method further comprises: a clock module for gating and/or phase-converting the serial clock signal to obtain a driving clock signal,

wherein the selection signal generation module generates the selection signal according to edge detection of the driving clock signal.

Optionally, the logic module shifts the first bit data to the first latch module or the second latch module according to an operation mode selection of a slave device.

Optionally, the first latch module includes a flip-flop and control logic, and is configured to latch and output the first bit of data.

Optionally, the second latch module includes a flip-flop, and the driving clock signal is applied to a clock terminal of the flip-flop to latch and output the remaining bit data.

Optionally, the selection signal generating module includes a flip-flop and a control logic module, and is configured to control the selection signal.

According to the slave device and the method for serial communication provided by the invention, the following advantages or benefits are provided: the system clock SYSCLK is used for shifting data to be sent in advance according to the detected edge of the serial clock signal SCLK, namely the rising edge or the falling edge of the serial clock signal SCLK, the data to be sent are latched and sent out by acting on a sending trigger through the clock edge when the sending edge of the serial clock signal SCLK comes, and the data to be sent is selected and output through a selector. Thus, the preparation delay of the transmission data is transferred to the time before the transmission edge arrives, and the transmission data arrives at the receiving end with only the transmission delay (PAD/board delay), so that the best transmission data establishing time is obtained, and the frequency ratio of the system clock SYSCLK/serial clock signal SCLK is reduced.

Further, the pre-shift preparation of the data to be transmitted is performed according to the sending edge of the serial clock signal SCLK detected by the system clock SYSCLK, the maximum delay time is 3 cycles of the system clock SYSCLK, and as long as the interval (i.e., the period) between two sending edges of the serial clock signal SCLK is greater than 3 cycles of the system clock SYSCLK, the sending edge of the serial clock signal SCLK (converted into the driving clock signal GSCLK in a mode) is used for directly latching and sending the data to be transmitted prepared by pre-shifting the system clock SYSCLK, which is enough to meet the requirements of the setup time and the hold time of the sending trigger, thereby ensuring the correct sending of the data.

Furthermore, the system clock SYSCLK is used to operate the memory module, so that the problems of reading, preparing and sending the first-bit data under the condition that no serial clock signal SCLK exists before the SPI transmission starts and the problems of operation (such as emptying, synchronization and the like) of the memory module during the period that no serial clock signal SCLK exists are solved.

Furthermore, a first bit data latch module is added, the problem that first bit data in different SPI modes are sent before the sending edge of a first serial clock signal SCLK is solved, the first bit data latch module only uses one trigger, and the overhead is extremely low.

Furthermore, the shift data latching and sending module is added, so that each bit of sending data is sent out after the sending edge of each serial clock signal SCLK, the hold time (hold) of the sending data at the receiving end is ensured, the data sending is not misplaced, and the shift data latching and sending module only uses one trigger, so that the overhead is extremely low.

Furthermore, a selection signal generation module and a selection module are added, so that the selection module can select correct shift bit data to output in different modes.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a block diagram illustrating a slave device for serial communication in the prior art;

FIG. 2 illustrates a timing diagram of serial communication of slave devices in the prior art;

FIG. 3 is a flow chart illustrating a serial communication method of a slave device according to a first embodiment of the present invention;

FIG. 4 is a flow chart illustrating a serial communication method of a slave device according to a second embodiment of the present invention;

FIG. 5 illustrates four modes of operation of serial communication of slave devices in accordance with embodiments of the present invention;

fig. 6 is a block diagram showing a slave device for serial communication according to a third embodiment of the present invention;

fig. 7 is a timing diagram illustrating a method for transmitting data from the device SPI mode 0 according to the fourth embodiment of the present invention.

Fig. 8 is a timing diagram illustrating a method for transmitting data from the device SPI mode 1 according to the fifth embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The SPI bus is a full-duplex, synchronous peripheral interface bus, which comprises 4 signal lines: a slave select line CS, a Serial Clock Line (SCLK), a master input/slave output data line MISO, and a master output/slave input data line MOSI, which are active at a low level. Because the signal lines are few, the protocol is simple, the relative data rate is high, and a large part of chips integrate SPI interfaces. The SPI works in a master-slave mode, the mode generally comprises a master device and one or more slave devices, data receives one bit of data between the master device and the slave devices according to the sampling edge of the SPI serial clock, and the sending edge sends the one bit of data to receive and send the data, so that full-duplex transmission (receiving and sending) is realized.

The CS is a chip select signal generated by the master device, and each slave device corresponds to a unique CS, which indicates whether the slave device is selected by the master device, and is normally active low. The effective period of the CS is effective SPI transmission between the master device and the slave device at one time, and multiple groups of multi-bit data can be transmitted. The SPI serial clock SCLK is also generated by the master device, and the master device receives/transmits data according to the sampling edge/transmitting edge of the SPI serial clock SCLK; the master device receives MISO data sent by the slave device at a sampling edge, and sends the data to the MOSI to the slave device at a sending edge; the slave receives MOSI data sent by the master device on a sampling edge and sends the data to the MISO to the master device on a sending edge.

A transmit edge is a level transition edge of a clock signal, either a rising edge or a falling edge, and in one timing diagram, a transmit edge is the starting point of a timing analysis.

Fig. 3 shows a flowchart of a serial communication method for slave devices according to a first embodiment of the present invention, where the method is implemented by a serial communication apparatus for slave devices, and includes the specific steps of:

step S301: a serial clock signal is received and data is received.

Before the chip select signal CS of the SPI slave device is valid, the serial clock signal SCLK from the master device is received, the DATA (DATA) to be transmitted is received via the DATA access terminal (MOSI), and stored in the DATA storage module.

The serial clock signal SCLK is the SPI master system clock signal, generated by the master.

Step S302: the data is shifted in synchronization with the system clock signal to obtain bit data.

The system clock signal SYSCLK is a system clock inside the SPI slave device, and the edge of the serial clock signal SCLK is synchronized and detected by the system clock signal SYSCLK to obtain the enable signal enable. The enable signal ENBIT is maintained for a corresponding one of the valid periods, the valid period starting with a first period delayed from an edge of the serial clock signal and lasting for a second period, the first period and the second period respectively including at least one second clock cycle. For example: the period of the system clock signal SYSCLK is the second clock period, the valid period of the enable signal enb it may delay 2 to 3 system clock signal periods compared to the edge of the serial clock signal SCLK, and the valid period only maintains the validity of one system clock period.

The edge of the enable signal enable is synchronized with the edge of the system clock signal SYSCLK at which data in the memory is shifted to obtain bit data.

The edge is a level transition edge of the clock signal, which is a rising edge or a falling edge, also referred to as a transmission edge.

Step S303: the pre-shifted bit data is latched and transmitted in synchronization with the serial clock signal.

And latching and transmitting the pre-shifted bit data at an edge of the serial clock signal SCLK, namely a transmitting edge, wherein the pre-shifted bit data are latched in the second latch module and transmitted to the selection module.

The pre-shifted bit data refers to that data transmitted by the current transmission edge is data synchronized by the system clock signal SYSCLK and shifted by the enable signal enb obtained by detecting the previous transmission edge, and data synchronized by the system clock signal SYSCLK and shifted by the enable signal enb obtained by detecting the current transmission edge is transmitted at the time of the next transmission edge.

The enable signal enable has a delay compared to the edge of the serial clock signal SCLK, so that the bit data shifted according to the enable signal enable also has a delay compared to the edge of the serial clock signal SCLK, that is, the latched and transmitted shifted bit data is the bit data shifted according to the enable signal obtained by detecting the edge of the last cycle of the serial clock signal SCLK in synchronization with the serial clock signal.

Step S304: and generating a selection signal, and selecting the output bit data by the selection module according to the selection signal.

The selection signal SEL is derived from the serial clock signal SCLK. The select signal SEL is 1 before the first transmit edge of the serial clock signal SCLK and 0 after the first transmit edge. When the selection signal SEL is 1, the selection module is connected to the first latch output end, and when the selection signal SEL is 0, the selection module is connected to the second latch output end.

The above steps only show the data transmission flow of the slave device serial communication method after the data transmission is started, i.e., from the first transmission edge. Before the formal start of data transmission from the device, i.e. before the first transmission edge, the method further comprises: before the first transmission edge, one bit of shifted data is prepared for transmission at the time of the first transmission edge. According to different selections of the SPI slave device modes, the method further comprises the following steps: before one bit of shift data is prepared in advance, one bit of data is shifted and latched, shifted and latched to the first latch block, and transmitted to the data output terminal MISO before the first transmission edge.

Fig. 4 shows a flow chart of a serial communication method of a slave device according to a second embodiment of the present invention, and compared with the method shown in fig. 3, fig. 4 is a preferred embodiment, except that a driving clock signal GSCLK is added to latch and transmit shift bit data at an edge of the driving clock, and the method includes the steps of:

step S401: a serial clock signal is received and data is received.

Step S402: a driving clock signal is obtained from the serial clock signal.

A block is added, the input is the serial clock signal SCLK, and the output is the driving clock signal GSCLK, specifically, the driving clock signal GSCLK may be generated by shifting the phase and/or gating the serial clock signal SCLK. Gating is enabled only during the CS lifetime, allowing the driving clock signal GSCLK to operate.

Step S403: the data is shifted in synchronization with the system clock signal to obtain bit data.

Step S404: the pre-shifted bit data is latched and transmitted in synchronization with the driving clock signal.

And latching and transmitting the pre-shifted bit data at the edge of the driving clock signal SCLK, namely the transmitting edge, wherein the pre-shifted bit data are latched in the second latch module and transmitted to the selection module.

In the second embodiment, since the driving clock is obtained by shifting the phase and/or gating the serial clock signal SCLK, the edges of the driving clock are synchronized with the edges of the serial clock.

The enable signal enable has a delay compared to the edge of the serial clock signal SCLK, and thus bit data shifted according to the enable signal enable also has a delay compared to the edge of the serial clock signal SCLK. The latched and transmitted shift bit data is bit data shifted according to an enable signal obtained by detecting an edge of one cycle on the serial clock signal SCLK in synchronization with the drive clock signal GSCLK, that is, in synchronization with the serial clock signal SCLK.

Step S405: and generating a selection signal, and selecting the output bit data by the selection module according to the selection signal.

The selection signal SEL is derived from the serial clock signal SCLK and the driving clock signal GSCLK. The select signal SEL is 1 before the first transmit edge of the serial clock signal SCLK and 0 after the first transmit edge. When the selection signal SEL is 1, the selection module is connected to the first latch output end, and when the selection signal SEL is 0, the selection module is connected to the second latch output end.

The above steps only show that the slave device serial communication method starts the data transmission flow after the data transmission is started, i.e., from the first transmission edge. Before the formal start of data transmission from the device, i.e. before the first transmission edge, the method further comprises: before the first transmission edge, one bit of shifted data is prepared for transmission at the time of the first transmission edge. According to different selections of the SPI slave device modes, the method further comprises the following steps: before one bit of shift data is prepared in advance, one bit of data is shifted and latched, shifted and latched to the first latch block, and transmitted to the data output terminal MISO before the first transmission edge.

Fig. 5 shows four operating modes of serial communication of slave devices according to an embodiment of the present invention. As shown, the system clock is divided into four operation modes according to the phase CPHA and the polarity CPOL of the system clock.

Mode one (SPI 0): the polarity CPOL is 0, the phase CPHA is 0,

mode two (SPI 1): the polarity CPOL is 0, the phase CPHA is 1,

mode three (SPI 2): a polarity CPOL of 1, a phase CPHA of 0,

mode four (SPI 3): a polarity CPOL of 1, a phase CPHA of 1,

polarity CPOL, which indicates whether serial clock signal SCLK is high or low when SPI is idle. If CPOL is set to 1, the clock signal at the pin of serial clock signal SCLK is high for the device at idle. The opposite is true when CPOL is set to 0.

Phase CPHA, which indicates whether the SPI device triggers data sampling when the clock signal on the pin of serial clock signal SCLK becomes a rising edge or when the serial clock signal SCLK becomes a falling edge. If CPHA is set to 1, the SPI device triggers data sampling when the serial clock signal SCLK becomes a falling edge, and transmits data on a rising edge. The opposite is true when the CPHA is set to 0.

In the present invention, the four modes are also distinguished as follows:

table one: four modes of SPI distinction

As can be seen from fig. 5 and table one, the transmit data beat for SPI mode 2 is the same as mode 0, the only difference being that mode 2 drives clock signal GSCLK in phase with serial clock signal SCLK.

SPI mode 1 beats equally with the transmitted data of mode 3, but mode 1 drives clock signal GSCLK in phase with serial clock signal SCLK, and mode 3 drives clock signal GSCLK in anti-phase with serial clock signal SCLK.

The SPI mode 1 differs from the mode 0 data transmission beat in that: SPI mode 0 has transmitted the first bit of data before the first transmit edge arrives, while mode 1 transmits the first bit of data after the first transmit edge.

In the

modes

1 and 3, all the transmission data is transmitted from the second latch module, and the selection signal SEL is always kept at 0. In the

modes

0 and 2, the first transmission data comes from the first latch block, the remaining transmission data comes from the second latch block, and the level of the selection signal SEL is 1 before the first transmission edge and is maintained as 0 after the first transmission edge.

Fig. 6 is a block diagram of a slave device for serial communication according to a third embodiment of the present invention, which is specifically a block diagram of a structure corresponding to the flowchart shown in fig. 4. As shown, the SPI slave device 200 according to the embodiment of the present invention may be divided into a system clock domain D1 and a driving clock signal GSCLK domain D2, and further includes a clock module 310 and a selection module 214.

The system clock domain D1 includes an edge detection module 110, a memory module 130, a logic module 120, and a first latch module 211.

The driving clock signal domain D2 includes a second latch module 212 and a selection signal generation module 213.

The edge detection module 110 detects a transmission edge of the serial clock signal SCLK using the internal system clock SYSCLK, and obtains a transmission edge enable signal enb it maintains one internal system clock period.

The storage module 130 stores all data to be transmitted.

The logic module 120 fetches a set of transmission data from the memory module 130, and shifts one bit of data BITDATA in the set of transmission data to the second latch module 212 when detecting an enable signal enable.

The first latching module 211, which includes a flip-flop and control logic, is used in

SPI modes

0 and 2, latches the first group of first bit transmission data for each transmission before the transmission starts, and transmits the first bit data after CS is active, and keeps on during this transmission.

The clock module 310 enables gating only when CS is active, and takes the inverse serial clock signal SCLK in

SPI modes

0 and 3, and takes the in-phase serial clock signal SCLK in

SPI modes

1 and 2, thereby obtaining the driving clock signal GSCLK. The driving clock signal GSCLK operates only during the active period CS, and the transmission edge of the driving clock signal GSCLK corresponds to the transmission edge of the serial system clock SCLK in the SPI modes, which are all rising edges in the modes, so that the driving clock signal domain D2 operates with a rising edge flip-flop.

The second latch module 212, which includes a flip-flop, has a sending edge of the driving clock signal GSCLK acting on a clock terminal of the flip-flop, latches and sends the sending bit data BITDATA previously shifted and prepared in the system clock domain D1, and sends the latching and sending bit data BITDATA to the select module 214 through an output terminal of the second latch module 212.

The selection signal generating module 213, which includes a flip-flop and control logic, is used to generate the selection signal SEL and select the transmission bit data output, and requires that the selection signals of SPI mode 0 and mode 2 are 1 before the first transmission edge and 0 after the first transmission edge, and keep 0 until an SPI transmission is finished;

SPI modes

1 and 3 remain at 0 at all times.

The select block 214 selects the output data of the first latch block 211 in the system clock domain D1 or the output data of the second latch block 212 in the driving clock domain D2 by a select signal SEL. Specifically, the output data of the first latch block 211 is selected when the selection signal SEL is 1, and the output data of the second latch block 212 is selected when the selection signal SEL is 0.

Fig. 7 is a timing chart showing a method for transmitting data from the device SPI mode 0 by the SPI according to the fourth embodiment of the present invention. Referring to FIG. 5, the timing diagram is divided into two parts, the upper dotted signal operates in the system clock domain D1, and the lower dotted signal operates in the driving clock domain GSCLK D2.

The driving clock signal GSCLK of SPI mode 0 takes the opposite phase of the serial clock signal SCLK.

Before CS goes low, in the system clock domain D1, the slave device fetches the first set of data from the memory module 130 and stores the first BIT of data in the first latch module 211 of BIT0, and the shift shifts the first transmission edge to the data BITDATA to be transmitted to the second latch module 212 of BIT 1-N. At the same time, the system clock domain D1 generates an asynchronous reset signal, and the select signal SEL in the reset driving clock signal GSCLK domain D2 is 1.

After CS goes low, in the driving clock domain D2, before the first transmission edge, the selection signal SEL is 1, and the selection module 214 selects BIT0, i.e., BIT0 of the first latch module 211 is output to the MISO as BIT 0. After the first transmission edge, the driving clock signal GSCLK is latched by the second latch module 212 and transmits BITDATA to the select module 214, the select signal SEL is changed to 0, and the select module 214 selects the data of the second latch module 212 to be output to the MISO.

Meanwhile, in the system clock domain D1, the system clock SYSCLK detects the sending edge of the serial clock signal SCLK to obtain the enable signal ENBIT, and the logic module 120 shifts one bit of data BITDATA according to the enable signal ENBIT, and the bit of data BITDATA is shifted to the second latch module 212.

Specifically, as shown in fig. 7, before the time t0 of the first transmission edge, BIT data BIT0 in BIT0 of the first latch module 211 is already output to MISO, and at time t0, the driving clock signal GSCLK latches and sends out BIT1 that is already prepared before the transmission starts, and is also BIT1 in BIT1-N of the second memory module 212, and then is selected by the selection module 214 to be output to MISO as BIT 1.

Meanwhile, at time t0, the serial clock signal SCLK transmission edge is detected by the system clock SYSCLK, and an enable signal enb it (maintaining a valid period of the system clock SYSCLK cycle) is generated, and the enable signal enb bit shifts data to bit2 at time t1, so that data is prepared for the second transmission edge.

At the time of the second transmit edge t2, the driving clock signal GSCLK latches and transmits out bit2 that was ready before the start of the transfer, i.e., bit2 in the second memory block, and is then selected by the selection block 214 for output onto MISO as bit 2.

Meanwhile, at time t2, the serial clock signal SCLK transmit edge is detected by the system clock SYSCLK, generating an enable signal ENBIT that shifts the data by bit3 at time t3, preparing the data for the third transmit edge.

time t4 is the third sending edge time, and data is sent down in a pipeline according to the above beat. After the first group of data is transmitted, the next group of data is taken out from the memory to be transmitted until the SPI transmission is finished (CS changes from low to high to invalid).

In the transmission process, as long as the clock cycle of the system clock SYSCLK is at least three times the cycle of the serial system clock SCLK, when the transmission edge of the serial system clock SCLK arrives, the DATA1 to be transmitted is stable enough to meet the preparation time T1 of BITDATA.

Fig. 8 shows a timing diagram of a method for transmitting data from SPI mode 1 of a fifth embodiment of the present invention, which is divided into two parts, as shown, the signal above the dotted line operates in the system clock domain D1, and the signal below the dotted line operates in the driving clock domain D2. The driving clock signal GSCLK of SPI mode 1 takes the same phase as the serial clock signal SCLK.

Before CS goes low, the slave device fetches the first set of data from the memory module 130 and shifts the first bit data bit0 to the second latch module 212 in the system clock domain D1. The select signal SEL is always held at 0.

After CS goes low, in the driving clock domain D2, the selection signal SEL remains 0 both before and after the first transmission edge, and the selection block 214 selects the data of the second latch block 212 to be output to the MISO according to the selection signal SEL.

Meanwhile, in the system clock domain D1, the system clock SYSCLK detects the sending edge of the serial clock signal SCLK to obtain the enable signal ENBIT, the logic module 120 shifts one bit of data in the memory module 130 according to the enable signal ENBIT to obtain BITDATA, and the bit of data BITDATA is shifted to the second latch module 212.

Specifically, as shown in fig. 8, before the time t0 of the first sending edge, the data in the memory module 130 is shifted to obtain BITDATA, and at the time t0, the driving clock signal GSCLK latches and sends out BIT0, which is already prepared before the transmission starts, and BIT0 in the BIT1-N second memory module 212, and then the selection module 214 selects and outputs the BIT to the MISO as BIT 0.

Meanwhile, at time t0, the serial clock signal SCLK transmission edge is detected by the system clock SYSCLK, and an enable signal enb it (maintaining a valid period of the system clock SYSCLK cycle) is generated, and the enable signal enb bit shifts data to bit1 at time t1, so that data is prepared for the second transmission edge.

At the time of the second transmit edge t2, the driving clock signal GSCLK latches and transmits out bit1 that was ready before the start of the transfer, i.e., bit1 in the second memory block, and is then selected by the selection block 214 for output onto MISO as bit 1.

Meanwhile, at time t2, the serial clock signal SCLK transmit edge is detected by the system clock SYSCLK, generating an enable signal ENBIT that shifts the data by bit2 at time t3, preparing the data for the third transmit edge.

The slave device and the method for serial communication provided by the invention can greatly reduce the frequency proportion of the system clock SYSCLK/serial clock signal SCLK, improve the data transmission rate of the slave device, or reduce the frequency of the system clock SYSCLK of the slave device. The advantageous effects of the present invention compared to the prior art are illustrated by two examples below.

Assuming that the transmission delay (PAD/board delay) time (T3 in fig. 7) of the slave device is 15ns (other related slight minor delays are not considered here, and the total delay can be uniformly taken into account), the minimum setup time (T4 in fig. 7) for the receiving end to receive the transmission data of the slave device is 5ns, and taking this as an example, compare two schemes:

table two: the highest frequency of SPI serial clock signal SCLK supported when system clock signal SYSCLK is 50MHz

It can be seen from table two that, similarly, the system clock signal SYSCLK is 50MHz, the highest frequency of the SPI serial clock signal SCLK supported by the original scheme is 6.25MHz, and the highest frequency of the SPI serial clock signal SCLK supported by the scheme is 16.6 MHz.

Table three: when the SPI serial clock signal SCLK is 10MHz, the requirement for the lowest frequency of the system clock signal SYSCLK is

It can be seen from table three that, similarly, the SPI serial clock signal SCLK is 10MHz, the original scheme requires that the lowest frequency of the system clock signal SYSCLK is 100MHz, and the scheme requires that the lowest frequency of the system clock signal SYSCLK is 33 MHz.

Through comparison of the two tables, it can be clearly seen that when the frequency of the SPI system clock SYSCLK is determined, the supporting frequency of the serial clock signal SCLK is greatly increased in the present invention, so that the rate of SPI data transmission can be increased; when the frequency of the SPI serial clock signal SCLK is determined, the requirement for the frequency of the system clock SYSCLK is greatly reduced, so that the power consumption can be reduced. Therefore, the present invention is very effective in improving the data transfer rate and reducing the power consumption.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A serial communication method for a slave device, characterized in that:

receiving a serial clock signal via a clock signal terminal;

2. The serial communication method according to claim 1, wherein the selected bit data of the data is shifted and latched and transmitted in successive cycles of the serial clock signal, respectively.

3. The serial communication method according to claim 1, further comprising: generating a driving clock signal according to the serial clock signal, wherein the bit data is transmitted at an edge of the driving clock signal.

4. The serial communication method according to claim 3, wherein the driving clock signal is obtained by gating and/or phase-shifting the serial clock signal.

5. The serial communication method according to claim 1, wherein the step of shifting the data comprises:

and shifting the data according to the enable signal to obtain bit data.

6. The serial communication method according to claim 5, further comprising: shifting the bit data to obtain a first bit data according to the enable signal, and latching the first bit data, and transmitting the latched first bit data.

7. The serial communication method according to claim 6, further comprising: and obtaining a selection signal according to the serial clock signal, wherein the selection signal is used for selectively providing the first bit data and the rest bit data of the data to a data output end for transmission.

8. The serial communication method according to claim 1, wherein the bit data is transmitted on a rising edge or a falling edge of the serial clock signal according to an operation mode of the slave device.

9. The serial communication method according to claim 7, wherein the first bit of data is transmitted before or after the first edge of the serial clock signal according to an operation mode of the slave device.

10. A slave device for serial communication, the slave device receiving a serial clock signal via a clock signal terminal, receiving data via a data input terminal, and transmitting the data via a data output terminal, the slave device comprising:

the storage module is used for storing the data;

11. The slave device of claim 10, wherein the logic module and the second latch module shift and latch, respectively, and transmit select bit data of the data in successive cycles of the serial clock signal.

12. The slave device of claim 10, further comprising:

and the edge detection module is used for delaying at least one second clock cycle in a first clock cycle of the serial clock signal so as to obtain an enabling signal synchronous with the system clock signal.

13. The slave device of claim 10, further comprising:

a clock module for gating and/or phase-converting the serial clock signal to obtain a driving clock signal,

14. The slave device of claim 10, wherein the logic module shifts the first bit of data to either the first latch module or the second latch module according to a slave device operating mode selection.

15. The slave device of claim 10, wherein the first latching module includes flip-flops and control logic to latch and output the first bit of data.

16. The slave device of claim 13, wherein the second latch module comprises a flip-flop, and wherein the driving clock signal is applied to a clock terminal of the flip-flop for latching and outputting the remaining bit data.

17. The slave device of claim 10, wherein the selection signal generation module comprises a flip-flop and control logic module to control the selection signal.