CN109698002B - Method and device for latching storage array data - Google Patents
Method and device for latching storage array data Download PDFInfo
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- CN109698002B CN109698002B CN201710993393.4A CN201710993393A CN109698002B CN 109698002 B CN109698002 B CN 109698002B CN 201710993393 A CN201710993393 A CN 201710993393A CN 109698002 B CN109698002 B CN 109698002B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The invention discloses a method and a device for latching storage array data, wherein the method comprises the following steps: the sensitive amplifier amplifies the first data signal to generate a second data signal; the register generates an operation data signal according to the selected address signal and the operation enabling signal, and updates a data signal corresponding to the selected address signal in the second data signal into the operation data signal to generate a third data signal; the register latches at least part of the third data signal to generate a fourth data signal; the register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal, generates a fifth data signal and outputs the fifth data signal; the first address signal precedes the same address of the second address signal by at least one clock cycle. According to the technical scheme of the embodiment of the invention, the problem that the calculated data cannot be correctly stored due to the fact that the time from the completion of the operation to the output of the data is short in the prior art is solved by configuring the two address signals.
Description
Technical Field
The embodiment of the invention relates to the technical field of nonvolatile memories, in particular to a method and a device for latching storage array data.
Background
When designing a memory array, in order to ensure the security of the stored data, arithmetic processing is usually performed on important data, for example, some encryption algorithms are added, and functions such as error correction are added to ensure the reliability of the data, and other performances are often lost when the functions are added, for example, after the encryption/decryption or error correction functions are added, a certain time is required to perform corresponding encryption/decryption or error correction arithmetic operations. In the prior art, the time from the completion of the operation to the output of the data is short, so that the data after the operation cannot be correctly stored, and errors in the read data are caused.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for latching storage array data, so as to solve the problem in the prior art that since the time from the completion of the operation to the output of the data is relatively short, the data after the operation cannot be correctly stored, and the read data is erroneous.
In a first aspect, an embodiment of the present invention provides a method for latching data in a memory array, including:
the sense amplifier acquires a first data signal corresponding to a first address signal according to the first address signal, amplifies the first data signal, generates a second data signal, and sends the second data signal to a register;
the arithmetic unit of the register performs arithmetic processing on data corresponding to a selected address signal according to the selected address signal and an arithmetic enabling signal to generate an arithmetic data signal, updates a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal, and generates a third data signal;
a first latch unit of the register latches at least part of the third data signals before a first address in the selected address signals according to a first latch enabling signal to generate fourth data signals;
a second latch unit of the register selects a data signal corresponding to a second address signal from the fourth data signal and the third data signal according to a second latch enable signal and the second address signal, generates a fifth data signal, and outputs the fifth data signal, wherein in the fifth data signal, at least a part of data signals before a first address in the selected address signal are selected from the fourth data signal, and data signals after the first address in the selected address signal are selected from the third data signal;
the first address signal precedes a same address of the second address signal by at least one clock cycle.
Optionally, at least a portion of the data signals before the first address in the selected address signals are data signals corresponding to an address where the first address signal precedes the second address signal.
Optionally, the updating, by the arithmetic unit, a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal, and generating a third data signal specifically includes:
and at the falling edge of the operation enabling signal, the operation unit of the register updates the data signal corresponding to the selected address signal in the second data signal into the operation data signal according to the selected address signal and the operation enabling signal, and generates a third data signal.
Optionally, the latching, by the first latch unit of the register, at least a part of the third data signal before the first address in the selected address signal according to the first latch enable signal, and generating the fourth data signal specifically includes:
and when the first latch enable signal falls, the first latch unit of the register latches at least part of the third data signals before the first address in the selected address signals according to the first latch enable signal to generate fourth data signals.
Optionally, the selecting, by the second latch unit of the register, a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to a second latch enable signal and a second address signal, generating a fifth data signal, and outputting the fifth data signal specifically includes:
and when the second latch enable signal falls, the second latch unit of the register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generates a fifth data signal, and outputs the fifth data signal.
In a second aspect, an embodiment of the present invention provides a latch device for storing array data, including:
the sense amplifier is used for acquiring a first data signal corresponding to a first address signal according to the first address signal, amplifying the first data signal to generate a second data signal, and sending the second data signal to the register;
the register comprises an arithmetic unit, a first latch unit and a second latch unit, wherein the arithmetic unit is used for carrying out arithmetic processing on data corresponding to a selected address signal according to the selected address signal and an arithmetic enabling signal to generate an arithmetic data signal, updating a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal and generating a third data signal;
the first latch unit is connected with the arithmetic unit and used for latching at least part of the third data signals before the first address in the selected address signals according to a first latch enabling signal to generate fourth data signals;
the second latch unit is respectively connected with the first latch unit and the arithmetic unit, and is configured to select, according to a second latch enable signal and a second address signal, a data signal corresponding to the second address signal from the fourth data signal and the third data signal, generate a fifth data signal, and output the fifth data signal, where, in the fifth data signal, at least a part of data signals before a first address in the selected address signal are selected from the fourth data signal, and a first address and a subsequent data signal in the selected address signal are selected from the third data signal;
the first address signal precedes a same address of the second address signal by at least one clock cycle.
Optionally, at least a portion of the data signals before the first address in the selected address signals are data signals corresponding to an address where the first address signal precedes the second address signal.
Optionally, the operation unit is specifically configured to, at a falling edge of the operation enable signal, update a data signal corresponding to the selected address signal in the second data signal into the operation data signal according to the selected address signal and the operation enable signal, and generate a third data signal.
Optionally, the first latch unit is specifically configured to, at a falling edge of the first latch enable signal, latch at least a part of the third data signal before a first address in the selected address signal according to the first latch enable signal by the first latch unit of the register, and generate a fourth data signal.
Optionally, the second latch unit is specifically configured to, when the second latch enable signal falls and the second latch enable signal falls, select, by the second latch unit of the register, a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generate a fifth data signal, and output the fifth data signal.
According to the latch method for the data of the memory array, provided by the embodiment of the invention, by configuring two address signals, namely the first address is advanced by at least one clock cycle compared with the same address of the second address signal, the problem that errors occur in read data due to the fact that the time from the completion of operation to the output of the data is short, and the data after operation cannot be correctly stored in the prior art is solved.
Drawings
Fig. 1 is a schematic flowchart illustrating a method for latching data in a memory array according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a latch device for storing array data according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic flowchart of a method for latching memory array data according to an embodiment of the present invention, where the method may be executed by a memory array data latching apparatus, where the apparatus may be implemented by hardware and/or software, and specifically includes the following steps:
A Sense Amplifier (SA) is an important component of a memory. In this embodiment, the sense amplifier reads a first data signal corresponding to a first address signal from the memory array, where the first data signal includes first data.
And 102, the arithmetic unit of the register performs arithmetic processing on data corresponding to the selected address signal according to the selected address signal and the arithmetic enable signal to generate an arithmetic data signal, and updates a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal to generate a third data signal.
Optionally, the operation processing may specifically include one or more of encryption, decryption, and error correction of data corresponding to the selected address signal.
Latching is the temporary storage of signals to maintain a certain level state. The most important role of the latch is buffering. In this step, at least a part of the third data signals before the first address in the selected address signals are latched to generate fourth data signals. The high level of the first latch enable signal has a duration of at least one clock cycle and the rising edge of the first latch enable signal occurs at a time that is at least one clock cycle ahead of a time at which the first address of the selected address signal occurs in the first address signal, so that at least a portion of the third data signal preceding the first address of the selected address signal can be latched for a sufficient time to generate the fourth data signal before the first address of the selected address signal occurs in the first address signal. In this step, at least a part of the third data signals before the first address in the selected address signal is latched to generate the fourth data signal, so that in step 104, when the second latch unit of the register outputs the data signals according to the second latch enable signal and the second address signal, the second address signal and the third data signal, and when the address signal does not correspond to the data signals, the data signal corresponding to the second address is selected from the fourth data signals to be output.
And step 104, selecting a data signal corresponding to the second address signal from the fourth data signal and the third data signal by the second latch unit of the register according to the second latch enable signal and the second address signal, generating a fifth data signal, and outputting the fifth data signal, wherein in the fifth data signal, at least a part of the data signals before the first address in the selected address signal are selected from the fourth data signal, and the data signals after the first address in the selected address signal are selected from the third data signal.
The start time and the end time of one period of the second latch signal correspond to the time when the first address of one address in the second address signal appears and the time when the last address of the address appears, respectively.
The first address signal precedes the same address of the second address signal by at least one clock cycle.
In this embodiment, the first latch unit of the register latches at least a part of the third data signal before the first address in the selected address signal according to the first latch enable signal, and generates the fourth data signal. And selecting a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal in the second latch unit, and generating a fifth data signal. Compared with the prior art, the time interval from the output of the data signal of the selected address signal after the operation is completed is longer in the implementation. The sense amplifier and the register use one clock signal, and thus the first address signal and the second address signal also use the clock signal. In this way, the arithmetic unit of the register performs arithmetic processing on data corresponding to the selected address signal based on the selected address signal and the arithmetic enable signal to generate an arithmetic data signal, and the second latch unit of the range register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal based on the second latch enable signal and the second address signal to generate a fifth data signal, and lengthens a time interval at which the fifth data signal is output. This is because the first address is advanced by at least one clock cycle from the same address of the second address signal, compared to the prior art, the sense amplifier and the register respectively read the data signal corresponding to the first address signal from the memory array according to the same address signal, and after the data signal corresponding to the selected address signal is operated in the register, the operated data signal is output according to the same address signal, which is equivalent to the data signal corresponding to the address signal being read in advance in the present embodiment. According to the latch method for the data of the memory array, provided by the embodiment of the invention, by configuring two address signals, namely the first address is advanced by at least one clock cycle compared with the same address of the second address signal, the problem that errors occur in read data due to the fact that the time from the completion of operation to the output of the data is short, and the data after operation cannot be correctly stored in the prior art is solved.
Optionally, in addition to the above technical solution, at least a part of the data signals before the first address in the selected address signals are data signals corresponding to an address where the first address signal is before the second address signal. The first latch unit of the register latches a data signal corresponding to an address where the first address signal is earlier than the second address signal according to the first latch enable signal to generate a fourth data signal, so that the storage space of the register is saved.
Optionally, in addition to the above-mentioned technical solution, the updating, by the arithmetic unit, the data signal corresponding to the selected address signal in the second data signal into an arithmetic data signal, and the generating the third data signal specifically includes:
and at the falling edge of the operation enabling signal, the operation unit of the register updates the data signal corresponding to the selected address signal in the second data signal into the operation data signal according to the selected address signal and the operation enabling signal to generate a third data signal. For example, the data corresponding to the selected address in the second data signal is operated at the rising edge of the operation enable signal to generate the operation data signal, the duration of the high level of the operation enable signal may be one clock cycle or multiple clock cycles, and the time when the rising edge of the operation enable signal occurs is the time when the first address of the selected address signal occurs in the first address signal.
Optionally, in the above-mentioned technical solution, the latching, by the first latch unit of the register, at least a part of the third data signal before the first address in the selected address signal according to the first latch enable signal, and generating the fourth data signal specifically includes:
and when the first latch enable signal falls, the first latch unit of the register latches at least part of the third data signal before the first address in the selected address signal according to the first latch enable signal to generate a fourth data signal. Illustratively, the high level of the first latch enable signal has a duration of at least one clock cycle, a rising edge of the first latch enable signal occurs at a time that is at least one clock cycle ahead of a time at which a first address in the selected address signal occurs in the first address signal, and the first latch unit of the register latches at least a portion of the third data signal before the first address in the selected address signal based on the first latch enable signal to generate the fourth data signal such that at least a portion of the third data signal before the first address in the selected address signal is latched for a sufficient time before the first address in the selected address signal occurs in the first address signal to generate the fourth data signal when a falling edge of the first latch enable signal occurs.
Optionally, in the above technical solution, the selecting, by the second latch unit of the register, a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generating a fifth data signal, and outputting the fifth data signal specifically includes:
when the second latch enable signal falls, the second latch unit of the register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generates a fifth data signal, and outputs the fifth data signal. Illustratively, one cycle of the second latch enable signal is illustratively two clock cycles.
Example two
On the basis of the above embodiments, the embodiments of the present invention provide a latch device for storing array data. Fig. 2 is a schematic structural diagram of a latch device for storing array data according to an embodiment of the present invention, where the latch device can be implemented by hardware, and as shown in fig. 2, the latch device includes:
and the sense amplifier 201 is configured to obtain a first data signal corresponding to the first address signal according to the first address signal, amplify the first data signal, generate a second data signal, and send the second data signal to the register 202.
The register 202 includes an arithmetic unit 2020, a first latch unit 2021, and a second latch unit 2022, and the arithmetic unit 2020 performs arithmetic processing on data corresponding to a selected address signal based on the selected address signal and an arithmetic enable signal to generate an arithmetic data signal, and updates a data signal corresponding to the selected address signal in the second data signal to the arithmetic data signal to generate a third data signal.
The first latch unit 2021 is connected to the operation unit, and is configured to latch at least a portion of the third data signal before the first address in the selected address signal according to the first latch enable signal, and generate a fourth data signal.
The second latch unit 2022 is connected to the first latch unit and the operation unit, respectively, and is configured to select a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generate a fifth data signal, and output the fifth data signal, where in the fifth data signal, at least a part of the data signals before the first address in the selected address signal is selected from the fourth data signal, and a first address in the selected address signal and a subsequent data signal in the selected address signal are selected from the third data signal.
The first address signal precedes the same address of the second address signal by at least one clock cycle.
According to the latch device for storing array data provided by the embodiment of the invention, two address signals are configured, namely the first address is advanced by at least one clock cycle compared with the same address of the second address signal, so that the problem that the error of read data is caused because the time from the completion of operation to the output of data is short in the prior art and the data after operation cannot be correctly stored is solved.
Optionally, on the basis of the above technical solution, at least a part of data signals before the first address in the selected address signals are data signals corresponding to an address where the first address signal is before the second address signal.
Optionally, on the basis of the foregoing technical solution, the operation unit 2020 is specifically configured to, when the operation enable signal falls, update the data signal corresponding to the selected address signal in the second data signal into the operation data signal according to the selected address signal and the operation enable signal by the operation unit of the register 202, so as to generate the third data signal.
Optionally, on the basis of the foregoing technical solution, the first latch unit 2021 is specifically configured to latch, according to the first latch enable signal, at least a portion of the third data signal before the first address in the selected address signal by the first latch unit 2021 of the register when the first latch enable signal falls, so as to generate a fourth data signal.
Optionally, on the basis of the foregoing technical solution, the second latch unit 2022 is specifically configured to, at a falling edge of the second latch enable signal and at a falling edge of the second latch enable signal, select, by the second latch unit of the register, a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generate a fifth data signal, and output the fifth data signal.
The latch device for the storage array data provided in the above embodiments can execute the latch method for the storage array data provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method. Technical details that are not described in detail in the above embodiments may be referred to a method for latching data of a memory array according to any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for latching data in a memory array, comprising:
the sense amplifier acquires a first data signal corresponding to a first address signal according to the first address signal, amplifies the first data signal, generates a second data signal, and sends the second data signal to a register;
the arithmetic unit of the register performs arithmetic processing on data corresponding to a selected address signal according to the selected address signal and an arithmetic enabling signal to generate an arithmetic data signal, updates a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal, and generates a third data signal;
a first latch unit of the register latches at least part of the third data signals before a first address in the selected address signals according to a first latch enabling signal to generate fourth data signals;
a second latch unit of the register selects a data signal corresponding to a second address signal from the fourth data signal and the third data signal according to a second latch enable signal and the second address signal, generates a fifth data signal, and outputs the fifth data signal, wherein in the fifth data signal, at least a part of data signals before a first address in the selected address signal are selected from the fourth data signal, and data signals after the first address in the selected address signal are selected from the third data signal;
the first address signal precedes a same address of the second address signal by at least one clock cycle.
2. The method of claim 1,
at least part of data signals before the first address in the selected address signals are data signals corresponding to the address where the first address signals are earlier than the second address signals.
3. The method of claim 1,
the updating, by the arithmetic unit, a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal, and generating a third data signal specifically includes:
and at the falling edge of the operation enabling signal, the operation unit of the register updates the data signal corresponding to the selected address signal in the second data signal into the operation data signal according to the selected address signal and the operation enabling signal, and generates a third data signal.
4. The method of claim 1,
the latching, by the first latch unit of the register, at least a part of the third data signal before the first address in the selected address signal according to the first latch enable signal, and generating the fourth data signal specifically includes:
and when the first latch enable signal falls, the first latch unit of the register latches at least part of the third data signals before the first address in the selected address signals according to the first latch enable signal to generate fourth data signals.
5. The method of claim 1,
the second latch unit of the register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to a second latch enable signal and a second address signal, generates a fifth data signal, and outputs the fifth data signal, specifically including:
and when the second latch enable signal falls, the second latch unit of the register selects a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generates a fifth data signal, and outputs the fifth data signal.
6. A latch device for storing array data, comprising:
the sense amplifier is used for acquiring a first data signal corresponding to a first address signal according to the first address signal, amplifying the first data signal to generate a second data signal, and sending the second data signal to the register;
the register comprises an arithmetic unit, a first latch unit and a second latch unit, wherein the arithmetic unit is used for carrying out arithmetic processing on data corresponding to a selected address signal according to the selected address signal and an arithmetic enabling signal to generate an arithmetic data signal, updating a data signal corresponding to the selected address signal in the second data signal into the arithmetic data signal and generating a third data signal;
the first latch unit is connected with the arithmetic unit and used for latching at least part of the third data signals before the first address in the selected address signals according to a first latch enabling signal to generate fourth data signals;
the second latch unit is respectively connected with the first latch unit and the arithmetic unit, and is configured to select, according to a second latch enable signal and a second address signal, a data signal corresponding to the second address signal from the fourth data signal and the third data signal, generate a fifth data signal, and output the fifth data signal, where, in the fifth data signal, at least a part of data signals before a first address in the selected address signal are selected from the fourth data signal, and a first address and a subsequent data signal in the selected address signal are selected from the third data signal;
the first address signal precedes a same address of the second address signal by at least one clock cycle.
7. The latch device for storing array data according to claim 6,
at least part of data signals before the first address in the selected address signals are data signals corresponding to the address where the first address signals are earlier than the second address signals.
8. The latch device for storing array data according to claim 6,
the arithmetic unit is specifically configured to, at a falling edge of the operation enable signal, update a data signal corresponding to the selected address signal in the second data signal to the operation data signal according to a selected address signal and the operation enable signal, and generate a third data signal.
9. The latch device for storing array data according to claim 6,
the first latch unit is specifically configured to, at a falling edge of the first latch enable signal, latch at least a part of the third data signal before a first address in the selected address signal according to the first latch enable signal, and generate a fourth data signal.
10. The latch device for storing array data according to claim 6,
the second latch unit is specifically configured to, at a falling edge of the second latch enable signal and at a falling edge of the second latch enable signal, select, by the second latch unit of the register, a data signal corresponding to the second address signal from the fourth data signal and the third data signal according to the second latch enable signal and the second address signal, generate a fifth data signal, and output the fifth data signal.
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| KR101835605B1 (en) * | 2011-11-24 | 2018-03-08 | 삼성전자 주식회사 | Flash memory device and reading method of flash memory device |
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| US5812489A (en) * | 1996-03-29 | 1998-09-22 | Nec Corporation | Single-chip synchronous dynamic random access memory (DRAM) system |
| CN1674068A (en) * | 2005-05-10 | 2005-09-28 | 友达光电股份有限公司 | Display drive chip and method for transmitting data thereof |
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