CN109696821B - Two-stage digital-to-time converter - Google Patents
Two-stage digital-to-time converter Download PDFInfo
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- CN109696821B CN109696821B CN201811529767.8A CN201811529767A CN109696821B CN 109696821 B CN109696821 B CN 109696821B CN 201811529767 A CN201811529767 A CN 201811529767A CN 109696821 B CN109696821 B CN 109696821B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
A two-stage digital-to-time converter comprising: the first delay circuit inputs a gate control signal and an optical pulse signal, comprises a delay chain formed by adopting a voltage controllable delay unit, and is used for selecting corresponding delay output by a high-order control multiplexer of a delay control word to generate corresponding delay time; the second delay circuit is connected to the rear end of the first delay circuit and comprises a first-stage phase inverter, the output end of the first phase inverter is connected with a plurality of parallel unit capacitors, and the output end of the first phase inverter is further connected with the second phase inverter. The invention realizes the higher delay resolution ratio of the delay stepping value lower than the gate delay by designing and optimizing the delay circuit structure and combining the more advanced and stable integrated circuit manufacturing process.
Description
Technical Field
The invention relates to the field of quantum key communication and photon detectors, and further relates to a two-stage digital time converter.
Background
A gated single photon detector is commonly used in current quantum communication key generation devices. One control point of a gated detector is that the detector can only respond when a quantum signal light pulse reaches a very small time window (a gating window) of the detector. In an actual system, due to factors such as different optical paths of signal light and synchronous light, delay caused by electric signal processing, and the like, a detector gate signal often cannot be accurately aligned with an optical pulse signal at a detector, so that a control mode is required in the system to realize accurate alignment of the gate signal and the optical pulse signal.
In the implementation method of the delay circuit, the step value of the delay circuit based on the clock counting method depends on the period of the reference clock, and generally only nanosecond resolution can be achieved. The circuit step value using the delay chain structure depends on the minimum delay of the delay unit, and there is a lower limit to the minimum gate delay that can be obtained under a specific process. When the delay precision requirement of the delay circuit is less than the minimum gate delay, the required step value cannot be obtained by using a simple delay chain structure. Meanwhile, in order to improve the dynamic range of the delay, the number of stages of the delay unit is generally increased, thereby causing an increase in system power consumption and a decrease in linearity. At present, when the design of a domestic delay circuit is realized by building a delay chain by using FPGA internal resources, the resolution can only reach the order of magnitude of hundreds of picoseconds. S.alahdab in 2012 proposed a digitally controlled load capacitor size that achieved sub-picosecond resolution, nanosecond dynamic range, but its input clock frequency only reached 8 MHz.
The frequency of the input clock signal in a general delay circuit is related to the dynamic range of the delay, i.e. the dynamic range of the delay does not exceed one clock cycle. The present invention is directed to a non-periodic clock signal, and 1.5GHz is the smallest pulse width of the clock signal, as shown in fig. 1, and the gate signal (gated control pulse) of the detector cannot be precisely aligned with the optical pulse signal (signal light) at the detector, so it is necessary to design a high-resolution controllable delay system to achieve precise alignment of the gate signal and the optical pulse signal. The dynamic range of delay required by the system is far beyond one clock cycle, which exacerbates the attenuation of narrow pulse signals. Chuang in 2009 designed a wide dynamic range delay locked loop for multiphase output, where the delay units can transmit clock frequencies up to GHz.
In the structure of the delay circuit, a core component delay unit for realizing a delay stepping value is composed of devices such as an MOS (metal oxide semiconductor) tube and a capacitor, and specific delay output is generated through adjustment of gate delay, capacitor discharge and the like of the MOS tube. The electrical parameters of these devices have certain process deviation and are also easily affected by temperature and voltage changes, so that the delay generates deviation along with the change of PVT, and the linearity of the delay circuit and the stability of the accuracy of the stepping value are reduced.
Disclosure of Invention
It is therefore an object of the present invention to provide a two-stage digital-to-time converter to at least partially solve the above-mentioned problems.
The invention provides a two-stage digital-to-time converter, comprising:
the first delay circuit inputs a gate control signal and an optical pulse signal, comprises a delay chain formed by adopting a voltage controllable delay unit, and is used for selecting corresponding delay output by a high-order control multiplexer of a delay control word to generate corresponding delay time;
the second delay circuit is connected to the rear end of the first delay circuit and comprises a first-stage phase inverter, the output end of the first phase inverter is connected with a plurality of parallel unit capacitors, and the output end of the first phase inverter is further connected with the second phase inverter.
In a further embodiment, further comprising: the first code converter inputs a control signal and is used for forming a control code of a middle-stage delay chain gating switch of the first delay circuit; and the second code converter inputs a control signal and is used for controlling the size of the unit capacitor in the second delay circuit.
In a further embodiment, the first transcoder is a binary to thermometer code like transcoder.
In a further embodiment, the second transcoder is a binary to standard thermometer code converter.
In a further embodiment, further comprising: a first bias voltage circuit comprising a delay locked loop for providing a bias voltage of the first delay circuit; and the second bias voltage circuit comprises a delay locking loop and is used for providing the bias voltage of the first delay circuit.
In further embodiments, the first and second bias voltage circuits each include: the phase frequency detector comprises a phase frequency detector, a charge pump, a loop filter and a voltage-controlled delay line.
In a further embodiment, the delay chain comprises a plurality of coarse delay units, and the coarse delay units are extended units based on current starvation improvement.
In a further embodiment, the first delay circuit comprises a plurality of stages of transmission gate switches connected in parallel in a delay chain to form the output stage.
In a further embodiment, the number of coarse delay units is 32, and the load of each coarse delay unit is the same.
In a further embodiment, the charge pump employs a cascode structure.
The invention realizes that the delay stepping value lower than the gate delay obtains higher delay resolution by designing and optimizing the delay circuit structure and combining with a more advanced and stable integrated circuit manufacturing process;
meanwhile, the high-resolution delay circuit provided by the invention adopts an optimized circuit structure design, gives consideration to a larger delay dynamic range and a digital time converter with higher input signal frequency requirement, adaptively adjusts the change caused by PVT deviation, and reduces the influence of the PVT deviation on the system.
Drawings
FIG. 1 is a schematic diagram of a gating signal and an optical pulse signal that are not precisely aligned in the prior art;
FIG. 2 is a block diagram of a two-stage digital-to-time converter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first delay circuit (Coarse _ stage) according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a delay unit (VCDU) in the first delay circuit;
FIG. 5 is a diagram of a second delay circuit (Fine _ stage) according to an embodiment of the present invention;
FIG. 6 is a Delay Locked Loop (DLL) providing bias voltages for the first delay circuit and the second delay circuit;
FIG. 7 shows the first and second delay circuits activating the control phase frequency detector (Start _ controlled PFD)
Fig. 8 shows a first delay circuit and a second delay circuit Charge Pump (CP).
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
Embodiments of the present invention provide a circuit with two stages of digital-to-time converters, which has a higher delay resolution, and also has a larger delay dynamic range and a higher input signal frequency requirement. And a time delay lock loop circuit which is self-adaptive and adjusts the change caused by PVT deviation is adopted, so that the influence of the PVT deviation on a system is reduced.
Under the SMIC55nm process, the input clock frequency is 1.5GHz, the step value of the delay is 10ps, and the dynamic range of the delay is 5 ns. For this design index, the embodiment of the present invention adopts a two-stage delay circuit architecture, as shown in fig. 2. The two-stage delay circuit is respectively a low bit (LSB) control stage for realizing a high-precision stepping value and a high bit (MSB) control stage for considering a large dynamic delay range. The first transcoder, for example Binary to one-hot, is a Binary to thermometer code like encoder, which differs from thermometer codes in that it has only one high bit (1) and the other low bit (0), which is usually used to indicate the state of the state machine, and in this system it is used as the control code for the coarse switching stage delay chain gating switch. The second transcoder, such as Binary to thermometer, is a Binary to standard thermometer code converter that is used to control the size of the load capacitor in the fine conversion stage. The coarse _ stage delay circuit (i.e., the first delay circuit) (as shown in fig. 3) adopts a delay chain formed by voltage-controllable delay units, and a high-order control multiplexer of a delay control word selects a corresponding delay output to generate a corresponding delay time, and the resolution can reach the order of hundreds of picoseconds. The coarse conversion stage delay circuit is formed by connecting a plurality of transmission gate switches in parallel to form an output stage, and the transmission gate switches have no driving capability, so that a driving circuit with great driving capability is needed. Because only one switch is selected to be conducted every time, no competition hazard exists, the inventor divides the output stage into four, and the four switches are selected to be conducted to control the output, so that the Coorse _ stage can be ensured to have enough driving capability. The fine switching stage (fine _ stage) is selected to adjust the delay by adjusting the size of the load capacitor, so that the time resolution lower than the gate delay can be generated, and the limit of the process is broken.
In order to make the step value and dynamic range of transmission delay not be affected by process, voltage and temperature, the bias voltage for regulating starvation type inverter is provided by reference delay locking ring, it is a delay ring of negative feedback mechanism, and can real-timely produce bias voltage which can be changed with process, voltage and temperature so as to produce stable delay step value and stable delay dynamic range. The delay locked loop is also divided into a first bias voltage circuit DLL _ coarse for supplying a bias voltage to the first delay circuit (coarse _ stage) and a second bias voltage circuit DLL _ fine for supplying a bias voltage to the second delay circuit (fine _ stage). The clock frequency period of the input reference voltage of DLL _ coarse is the delay dynamic range of the system, and the clocks CLK _ START and CLK _ STOP controlling DLL _ fine are two adjacent output clocks of the delay chain in DLL _ coarse, and the clock interval is the delay dynamic range of fine _ stage.
In the design of the two-stage delay circuit system architecture, the resolution of coarse _ stage is 156.25ps, and the bit number of the control word is 5 bits. Coarse delay cells (VCDU) in the Coarse _ stage are modified based on current starved inverters, as shown in fig. 4, where the control voltage VC generates a bias current at M1 to control the rising edge of the input clock. The pulse width of the control signal at the last charge-discharge stage is consistent, so that the duty ratio of the output clock signal is close to 50%, the condition that the signal passing through the whole delay chain is not output due to too large attenuation of the output clock pulse is avoided, and the attenuation of the output signal is reduced totally. Wherein M2 and M5 are control voltage ranges with minimum charge and discharge current mismatch of the charge pump in the delay locked loop for self-adaptively adjusting PVT deviation change, and the control voltage of the delay chain is moved to a range close to Vref/2. In order not to affect the adjusting capability of the main adjusting and controlling tube, the width-length ratio of M2 and M5 is much smaller than that of the controlling tubes M1 and M4.
The circuit principle of the fine switching stage (i.e. the second delay circuit) is as shown in fig. 5, the output of the first stage inverter formed by M1 and M2 is connected with a group of 16 parallel capacitors, each unit Capacitor (CL) is formed by connecting two MOS transistors whose source and drain are connected together in parallel, the gates are connected together and connected to the output end of the first stage inverter, and the digital voltage applied to the drain and source determines whether the MOS channel is formed, so that the channel capacitor is inserted or removed according to the logic of the drain and source. The 16 CL's are identical and are not arranged in binary weighted groups but are controlled by a 16-bit thermometer code, so that the switching is less, the glitch can be reduced, and most importantly, the linearity is improved. The fine conversion stage produces a delay dynamic range of 146.48ps with a delay step value of 9.77ps via the control word. The bias voltage controls the bias current of the whole starvation type inverter, and the bias voltage automatically adjusts and adapts to the changes of a delay stepping value and a dynamic range caused by the changes of the process, the voltage and the temperature. The inverter used as a comparator is added with a control tube, the width-to-length ratio of the tube of M6 is smaller than that of the main control tube M3 and also smaller than that of M5, and mainly the falling time of the output pulse is prolonged, so that the attenuation of the pulse width is reduced.
Compared with the traditional phase-locked loop, the Delay Locked Loop (DLL) adopts the voltage-controlled delay unit, has small delay jitter and has incomparable advantages in the aspects of system stability and bandwidth. The variable delay line (VCDL) is used to delay the signal for a certain time, and the delay time is determined by the control voltage Vctrl. Ideally, the delay time of the VCDL is linearly related to the control voltage Vctrl, and the slope of the curve is the VCDL gain Kvcdl (rad/V). The slope of the curve may be positive or negative. I.e. the delay time decreases with increasing control voltage. In the embodiment of the invention, the slope of the voltage-controlled delay curve of the coarse conversion unit is positive, and the slope of the voltage-controlled delay curve of the fine conversion control unit is negative. The mathematical model expression of VCDL is
delay＝Kvcdl·Vctrl+t0
t0Is the inherent delay time of VCDL, t0>0。
The DLL _ coarse (i.e. the first bias voltage circuit) and the DLL _ fine (i.e. the second bias voltage circuit) in the embodiment of the present invention mainly provide bias voltages for the coarse conversion unit and the fine conversion control unit, as shown in fig. 6, the variable delay lines and the variable delay control stages in the DLL _ coarse and the DLL _ fine have the same variable delay units as the coarse _ stage and the fine _ stage of the main delay chain, respectively, and mainly provide the bias voltages to adjust the driving capacities of the coarse conversion unit and the fine conversion unit in the main delay chain, so as to suppress the influence of the transmission delay by the PVT. The basic DLL consists of a Phase Detector (PD), a Charge Pump (CP), a loop filter (LP) and a Voltage Controlled Delay Line (VCDL).
The VCDL in the first bias voltage circuit (DLL _ coarse) may include 32 delay units (VCDU), and outputs a delayed signal to be fed back to the PD, and the PD compares the phase relationship between the reference clock and the feedback signal and outputs a phase difference signal indicating the phase relationship therebetween, and the phase difference signal is converted by the CP and the LP into a change in the control voltage of the VCDL, thereby forming negative feedback. Under the action of a loop, the same phase of a reference signal and a feedback signal is realized by continuously adjusting the control voltage of the VCDL. In the embodiment of the invention, the delay locked loop of the coarse conversion stage takes a reference clock with the period of 200M as an input, and the reference clock is provided by an external crystal oscillator. The coarse switching stage has a dynamic range of delay of 5ns and a step value of 156.25 ps. However, when the initial delay of the delay chain is less than half of the input reference clock, or more than 1.5 times of the input reference clock, the basic DLL has the possibility of locking to a direction tending to 0 or an integer multiple of the input reference clock, and when considering process variations and the like, the DLL _ coarse has a higher possibility of locking error. Some designs avoid this false lock problem by additional ancillary circuitry. First, the operational phase of the phase detector is typically expanded to ± 2 pi, but without other control circuitry, such a delay-locked loop would tend to lock only in the direction of a delay of 0. For high frequency signals, there is a greater likelihood that the initial delay between the reference input clocks Clk _ ref and Clk _ out is greater than two clock cycles and there is a greater chance of false lock.
In the embodiment of the invention, a Phase Frequency Detector (PFD) is adopted to solve the problem of error locking. It is based on a dynamic DFF resettable startup controlled PFD (SC _ PFD). First, the delay between the input and output of the VCDL of DLL _ coarse is initially set to a minimum value and the output signal DN of the PFD is allowed to be activated, assuming that the delay of the VCDL increases as the control voltage decreases. Thus, the delay between the input and output of the VCDL will increase until one clock cycle of the input signal is reached. The DLL does not lock in error and the delay time is fixed to one clock cycle no matter how long the delay time is provided by the VCDL. The SC _ PFD is composed of one resettable dynamic DFF and two resettable dynamic DFFs composed of NAND, and the schematic block diagram of the circuit is shown in fig. 7. The advantage of using such a PFD is that the circuit diagram is simple, the operational input reference frequency is high, the reset path is short, the power consumption is low, and secondly the duty cycle of Clk _ ref and Clk _ out does not need to be exactly 50% because the triggering type of DFF is edge triggered. The inventors extended the charging time of the capacitor by cascading more even-numbered stages of inverters at the output of fig. 7, thereby introducing additional delay in the PFD. Because if the pulse widths of UP and DN are not sufficient, the voltage value to which the capacitor is charged does not reach the threshold to turn on the switch, which cannot turn on the switch in the charge pump.
The main problem affecting the linearity of the PFD/CP is the mismatch of current sources, the current varies with the process angle, and the current is also affected by the output voltage of the charge pump, when the charge pump has charge/discharge loss, extra charge will be injected into and flow out of the loop filter, and periodic voltage fluctuation will be generated on the capacitor. The unstable output voltage of the charge pump mainly comes from the channel length modulation effect of the switching MOS tube, and the channel modulation effect can be effectively weakened by the long-channel MOS tube, so that the output voltage of the charge pump tends to a stable value. As shown in fig. 8, a cascode structure is adopted, which can increase the output impedance of the current source, so that the influence of the voltage variation at the output end of the charge pump on the current variation in the saturation region of the MOS transistor is greatly reduced. The transmission gate is used as a switch, so that mismatching of conduction time of the charge and discharge branch switch can be reduced. And secondly, the non-ideal effect of the charge pump is clock feed-through and charge injection of the switching tube, and the corresponding method is to connect a dummy tube and control an MOS tube connected with a drain source by a clock opposite to the clock for controlling the switching tube.
In order to make the VCDU of DLL _ coarse (DCC in fig. 6) and the VCDU of coarse _ stage completely duplicated, the load of the VCDU should be identical, so a dummy buffer (DB in fig. 6) is added at the node of the VCDL. Also to achieve the same delay between Clk _ ref and Clk _ out, a dummy delay unit (DCC _ D) is added after Clk _ ref to ensure that their loads are consistent. Buf is a buffer unit that corrects the waveform.
When DLL _ coarse is stable, the delay interval between CLK _ start and CLK _ stop is a dynamic range of the fine conversion stage, and the step value of the fine conversion stage is denoted by Td _ f, then
fine_stage_1-fine_stage_2＝16Td_f
The delay control units of DLL _ fine and fine _ stage must also be kept consistent so that the step value and dynamic range of fine _ stage can follow the DLL _ fine variation. Thereby negatively feeding back the influence of the PVT variation on the coarse conversion unit and the fine conversion control unit.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A two-stage digital-to-time converter, comprising:
the first delay circuit inputs a gate control signal and an optical pulse signal, comprises a delay chain formed by adopting a voltage controllable delay unit, and is used for selecting corresponding delay output by a high-order control multiplexer of a delay control word to generate corresponding delay time;
the second delay circuit is connected to the rear end of the first delay circuit and comprises a first phase inverter, the output end of the first phase inverter is connected with a plurality of parallel unit capacitors, the output end of the first phase inverter is also connected with a second phase inverter, and the first phase inverter is a starvation phase inverter;
a first bias voltage circuit comprising a delay locked loop for providing a bias voltage of the first delay circuit;
and a second bias voltage circuit including a delay locked loop for providing a bias voltage for the second delay circuit.
2. The two-stage digital-to-time converter of claim 1, further comprising:
the first code converter inputs a control signal and is used for forming a control code of a middle-stage delay chain gating switch of the first delay circuit;
and the second code converter inputs a control signal and is used for controlling the size of the unit capacitor in the second delay circuit.
3. The two-stage digitizer as in claim 2, wherein the first transcoder is a binary to thermometer code like transcoder.
4. A two-stage digital-to-time converter as claimed in claim 2 wherein said second transcoder is a binary to standard thermometer code converter.
5. The two-stage digital-to-time converter of claim 1, wherein the first and second bias voltage circuits each comprise: the phase frequency detector comprises a phase frequency detector, a charge pump, a loop filter and a voltage-controlled delay line.
6. The two-stage digital-to-time converter according to claim 1, wherein said delay chain comprises a plurality of coarse delay cells, said coarse delay cells being modified based on the current starvation principle.
7. A two-stage digital-to-time converter as claimed in claim 1, wherein said first delay circuit comprises a plurality of transmission gate switches connected in parallel in a delay chain to form an output stage.
8. The two-stage digitizer as in claim 6, wherein the number of said coarse delay units is 32 and the load of each coarse delay unit is the same.
9. The two-stage digital-to-time converter according to claim 5, wherein the charge pump employs a cascode configuration.
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| CN110488595B (en) * | 2019-08-29 | 2020-10-13 | 北京理工大学 | Time-to-digital converter for time difference ranging of frequency modulation continuous wave radar |
| CN110764492B (en) * | 2019-11-15 | 2021-06-29 | 北京广利核系统工程有限公司 | Multichannel switching value signal generating device and SOE event simulator |
| CN112054800B (en) * | 2020-08-03 | 2023-08-08 | 博流智能科技（南京）有限公司 | Digital time conversion method, digital time converter and digital phase-locked loop |
| CN114509929B (en) * | 2022-01-20 | 2023-09-12 | 芯思原微电子有限公司 | Time-to-digital conversion system |
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