CN109684746A - A method of positioning number timing path spice emulation failure - Google Patents
A method of positioning number timing path spice emulation failure Download PDFInfo
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- CN109684746A CN109684746A CN201811608230.0A CN201811608230A CN109684746A CN 109684746 A CN109684746 A CN 109684746A CN 201811608230 A CN201811608230 A CN 201811608230A CN 109684746 A CN109684746 A CN 109684746A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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Abstract
A method of positioning number timing path spice emulation failure, comprising the following steps: read simulation waveform file content, list each node on pre- emulation timing path together with its timing while value and spice emulate after timing on each node while value；Check that the signal of each node on timing path jumps situation；Emulation failure cause is judged according to inspection result.The reason of present invention compares each node actual signal on whole timing path with desired signal, while the pin bias by each element not on current path is listed, and quickly and easily finds emulation failure is simultaneously positioned.
Description
Technical field
The present invention relates to EDA technical field, in particular to a kind of method of number timing path spice emulation.
Background technique
Further advanced with process node in digital circuit, STA (static timing analysis) has shown more obvious
Limitation, carrying out spice emulation to timing path then becomes a kind of more reasonable manner.In board design
Spice emulation is different, and the spice emulation in digital circuit is usually to emulate to some critical timing paths.It uses first
STA tool obtains a series of timing paths, then on these paths element and gauze using spice carry out time delay simulation simultaneously
Calculate time sequence allowance.
Although the spice simulation objectives of digital circuit are the delays in imitative path rather than imitative circuit function, it appears that seem
It is easier to reach target.But since digital circuit structure is complicated, the component kind for including on path is various, in addition bypasses road
The factors such as diameter and design constraint can all influence simulation result.Once emulation failure, due to progress be transistor level emulation,
Spice emulator itself can not see each standard block element on path, cannot provide exact failure cause.It is artificial to adjust
Examination then needs the functional information of Integrated Checkout standard block, the timing side information of each point and waveform on timing path as a result,
Inefficiency, feasibility are poor.
When emulation, driving source, the pumping signal transmittance process are added in path root node according to timing path information first
The middle delay needed in measuring route between every two pin, finally obtains the delay value in whole path.According to this principle, imitate
The essence really to fail is that required signal does not hand on, and spice emulator is not measured by the variation of output signal, such as:
Driving source do not add, signal is not handed on, signal has and hands on but do not reach required level etc..
There are many reason of causing emulation failure meetings, and most commonly seen reason has the following two kinds:
(1) the control signal assignment of multi input combinational logic element is not right.
(2) excitation that the data terminal of sequential element is connect is not right.
It is then desired to a kind of method of location simulation failure.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of digital timing paths of positioning
The method of spice emulation failure, each node actual signal on whole timing path is compared with desired signal, simultaneously will
The reason of pin bias of each element not on current path is listed, and emulation failure is quickly and easily found simultaneously is determined
Position.
To achieve the above object, the method for positioning number timing path spice emulation failure provided by the invention, including with
Lower step:
Read simulation waveform file content, list it is pre- emulation timing path on each node together with its timing side value and
After spice emulation on each node timing side value；
Check that the signal of each node on timing path jumps situation；
Emulation failure cause is judged according to inspection result.
Further, it is described check timing path on each node signal jump situation the step of, further comprise,
It checks signal not jump, then emulates failure；Check signal have jump but the jump and the jump in original temporal path it is different
It causes, then emulates failure.
It does not jump caused emulation failure for signal, checks the preset value of each input pin of counter element；
In case of the output pin in element, then it is assumed that the element control terminal assignment is not pair or sequential element data terminal
Driving source is not right；In case of the input pin in element, then it is assumed that the gauze before the element is connected with ground or high level.
Jump is occurred for signal but the jump and the inconsistent caused emulation of the jump in original temporal path fail, then is recognized
It is not right for control terminal assignment, the control terminal assignment of the point and counter element that emulate failure on timing path is listed, emulation is found out and loses
The exact cause lost.
To achieve the above object, the present invention also provides a kind of computer readable storage mediums, are stored thereon with computer and refer to
It enables, the computer instruction executes the step of above-mentioned positioning number timing path spice emulates the method for failure when running.
In current large scale digital SOC design, the critical path series of emulation is very long, and the component kind for including is numerous
More, design constraint and path structure are intricate, lead to spice emulation often failure.The digital timing of positioning provided by the invention
The method of path spice emulation failure, combines comprehensive analysis for simulation result and original timing path information, can be fast
Speed finds the point and reason of emulation failure, greatly improves the service efficiency of engineer, while can also substantially reduce and entirely to emulate
The number of iterations.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart of the method for positioning number timing path spice emulation failure according to the present invention；
Fig. 2 is the schematic diagram containing composition element circuit according to embodiments of the present invention；
Fig. 3 is the schematic diagram containing sequential element circuit according to embodiments of the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the flow chart of the method for positioning number timing path spice emulation failure according to the present invention, below will ginseng
Fig. 1 is examined, the method for positioning number timing path spice emulation failure of the invention is described in detail.
Firstly, reading simulation waveform file content in step 101.
In this step, the simulation waveform file content of reading, including, the pre- node emulated on timing path is together at that time
Sequence while value (transition edges) (desired signal) and spice emulation after timing on each node while value (actual signal).
Step 102, compare the signal jump situation of each point on timing path.
In this step, according to the value on the pre- emulation timing side on the node on timing path one by one more each node
Desired signal, i.e., be compared, and recorded by the value on timing side with actual signal after (transition edges) and spice emulation.
Step 103, comparable situation judgement emulation failure cause is jumped according to the signal of each point on timing path.
In this step, the reason of emulation failure, is generally divided into following two situation:
A) there is no hopping edge.Mean emulation failure if the jump of not signal, checks each of counter element at this time
A preset value of input pin.In case of element output pin, then show that the element control terminal assignment is not right, for when
For sequence element, the driving source of data terminal may not also be right.In case of the input pin in element, then illustrate the gauze of front
It has been connected to ground or high level.
B) the jump edge obtained and the hopping edge in original temporal path are inconsistent.The each of counter element is also checked at this time
The crucial preset value of a input.In this case be usually control terminal assignment it is not right, by by emulated on path failure point and
The control terminal assignment of counter element is listed, it will be able to directly find out the exact cause of emulation failure.
Fig. 2 is the schematic diagram containing composition element circuit according to embodiments of the present invention, and Fig. 3 is according to the present invention
The schematic diagram containing sequential element circuit of embodiment.Explanation is further explained to the present invention in conjunction with Fig. 2 and Fig. 3.
Element on timing path can be divided into two kinds: composition element and sequential element.In circuit shown in Fig. 2, AND
It is a composition element -- with door, functional representation are as follows:
ZN=！(A1∩A2)∪(B1∩B2)
For the said elements on path, when spice is emulated, Bypass Control pin A2, B1 and B2 need to be arranged correct
Level value could make the signal of A1 be transmitted to ZN.However in spice netlist, tool is usually to complex logic Elementary Function point
It analyses imperfect, it is incorrect to which signal can not hand on to result in the voltage logic that is connect of control pin.
In the electronic circuit as shown in figure 3, DFF is a sequential element.Unlike composition element, sequential element is in addition to control
End CDN processed needs outside assignment, data pins also need plus skip signal driving source, and jump type to depend on it is original
The signal at the end Q is depending in timing path.The state truth table of the element is as follows:
| CDN | CLK | D | Q |
| L | - | - | L |
| H | ↑ | H/L | H/L |
| H | ↓ | N | N |
If spice emulation failure, reason if, are more slightly more complex on such element.A kind of situation is at CDN
In reset state, Q signal can not be overturn.Another situation is driving source added by D not to causing the jump of Q and desired value different
It causes.Both of these case can obtain relevant information from the wave file of simulation result, by the comparison with truth table, in turn
Orient definite reason.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer instruction, the computer
The step of method of above-mentioned positioning number timing path spice emulation failure is executed when instruction operation, when the positioning is digital
The method of sequence path spice emulation failure is repeated no more referring to the introduction of preceding sections.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (5)
1. a kind of method of positioning number timing path spice emulation failure, comprising the following steps:
Read simulation waveform file content, list it is pre- emulation timing path on each node together with its timing side value and
After spice emulation on each node timing side value；
Check that the signal of each node on timing path jumps situation；
Emulation failure cause is judged according to inspection result.
2. the method for positioning number timing path spice emulation failure according to claim 1, which is characterized in that described
It checks the step of signal of each node on timing path jumps situation, further comprises the jump for checking not signal,
Then emulate failure；It checks the jump of signal but the jump and the jump in original temporal path is inconsistent, then emulate failure.
3. the method for positioning number timing path spice emulation failure according to claim 2, which is characterized in that described
The step of emulating failure cause is judged according to inspection result, further comprises,
It does not jump caused emulation failure for signal, checks the preset value of each input pin of counter element；
In case of the output pin in element, then it is assumed that the element control terminal assignment is not pair or the excitation of sequential element data terminal
Source is not right；In case of the input pin in element, then it is assumed that the gauze before the element is connected with ground or high level.
4. the method for positioning number timing path spice emulation failure according to claim 2, which is characterized in that described
The step of emulating failure cause is judged according to inspection result, further comprises,
There is jump for signal but the jump and the inconsistent caused emulation of the jump in original temporal path fail, then it is assumed that control
It holds assignment not right, lists the control terminal assignment of the point and counter element that emulate failure on timing path, find out emulation failure really
Cut reason.
5. a kind of computer readable storage medium, is stored thereon with computer instruction, which is characterized in that the computer instruction fortune
Perform claim requires the step of method of 1 to 4 described in any item positioning number timing path spice emulation failures when row.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110268404A (en) * | 2019-05-09 | 2019-09-20 | 长江存储科技有限责任公司 | For the emulation mode in functional equivalence detection |
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Application publication date: 20190426 |