CN109656849B - Bus address distribution system based on cascade father node gating and communication method - Google Patents
Bus address distribution system based on cascade father node gating and communication method Download PDFInfo
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- CN109656849B CN109656849B CN201811594192.8A CN201811594192A CN109656849B CN 109656849 B CN109656849 B CN 109656849B CN 201811594192 A CN201811594192 A CN 201811594192A CN 109656849 B CN109656849 B CN 109656849B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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Abstract
The invention discloses a bus address distribution system based on cascade father node gating and a communication method, wherein the system comprises a master device and a plurality of slave devices, the slave devices are respectively more than one first-level slave device, more than one second-level slave device,. …, more than one N-1-level slave device and more than one N-level slave device, and the master device and the slave devices are sequentially cascaded. The master device can calculate the topological structures among all the slave devices by using the address allocation process, thereby coordinating the roles of all the nodes in the whole system according to the topological graph and being used in extensible systems such as electronic module splicing and the like.
Description
Technical Field
The invention relates to a bus address allocation technology, in particular to a bus address allocation system and a communication method based on cascade father node gating.
Background
The conventional bus address allocation technology is realized based on a bus arbitration mechanism, only one master device is arranged on a bus, a plurality of slave devices are possible, the master device sends data to the bus, all the slave devices can receive the data, but the slave devices need to establish a set of rules based on bus arbitration when needing to send the data to the bus, the slave devices are required to monitor whether other slave devices send the data on the bus, and the rules are avoided when the bus conflicts. The steps generally comprise the following steps:
a 1: the master device on the bus sends an address clearing instruction, and all slave devices can receive the instruction and clear own addresses;
a 2: after clearing the address, the slave device needs to initiate an address application request to the master device, but since the slave device cannot simultaneously send data to the bus, otherwise, the bus data is disordered, the slave device needs to monitor whether the bus is busy before sending the data, and if the bus is busy, the slave device waits for the bus to be free and then sends the data;
a 3: when the bus is idle, a plurality of slave devices may possibly monitor the bus simultaneously and send data to the bus simultaneously, at the moment, the bus also collides, the slave devices immediately stop sending the data after monitoring the collision, and send the data again after a random time;
a 4: after each slave device applies for the address to the master device, the slave device which assigns the address to the master device transmits data, so that no bus collision occurs in the subsequent communication.
The traditional bus address allocation technology has the following defects:
1. the bus is required to support collision detection;
2. the more the number of slave devices is, the higher the probability of collision is, so that the bus efficiency is not high, and the number of slave devices accessed to the bus is limited;
3. the master device cannot know how each slave device is connected to the bus, nor the connection relationship of each slave device.
Therefore, the prior art is in need of improvement.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a bus address distribution system based on cascade father node gating, which has the following specific scheme:
the system comprises a master device and a plurality of slave devices, wherein the slave devices are respectively more than one first-level slave device, more than one second-level slave device, … …, more than one N-1-level slave device and more than one Nth-level slave device, wherein N is a natural number;
the master device is provided with more than one interface, the slave devices are provided with more than two interfaces, each interface comprises a group of bus interfaces and a group of strobe signal interfaces, the bus interfaces are directly connected to the bus, the slave devices are also directly mounted on the bus, the strobe signal interfaces are directly connected to the slave devices, and each group of strobe signals can be used as strobe signals, namely input states or active strobe (output state) signals, namely output states; the first-stage slave device is directly connected to an interface of the master device through a bus and a strobe signal, the second-stage slave device is connected to the interface of the first-stage slave device through the bus and the strobe signal, the third-stage slave device is connected to the interface of the first-stage slave device through the bus and the strobe signal, and the like, and the Nth-stage slave device is connected to the Nth-1-stage slave device through the bus and the strobe signal;
all the slave devices can receive the data sent by the master device, but only the gated slave devices are allowed to send the data to the bus; at most one slave device can be gated at any one time.
Preferably, the number of interfaces on the master device is four.
Preferably, the number of interfaces on each slave device is four.
The invention also provides a communication method of the bus address distribution system based on the cascade father node gating, which comprises the following steps:
s1: closing the gating signal: the master device sends a broadcast message to inform all slave devices to close the gating signals cascaded downwards, and sets the gating signals to be in an input state, and the master device also closes all the gating signals;
s2: first level slave address assignment: the master device sequentially traverses all the interfaces of the master device, gates the first-stage slave devices of the corresponding interfaces, and distributes addresses to the gated first-stage slave devices by using address distribution instructions;
in the process, only the gated slave device can respond to the address allocation instruction, after the slave device responds successfully, the address of the slave device is allocated successfully, and the master device closes the gating signal;
s3: gated slave node partitioning: after the first-level equipment receives the broadcast address of the assigned address, the node of the interface cascade which is selected by the first-level slave equipment is identified as the upper-level node, namely the father node of the first-level slave equipment, and other interfaces are automatically classified as the lower-level cascade interface;
s4: second level slave address assignment: the master device sequentially traverses each interface of each first-stage slave device, requires the first-stage slave device to gate the appointed next-stage cascade interface by using an instruction message attached with the address corresponding to the first-stage slave device, and sends a response message to the master device after the first-stage slave device gates the appointed next-stage cascade interface to inform the master device that the appointed cascade interface is gated, so that address allocation can be carried out, and address allocation of the second-stage slave device connected with the appointed cascade interface is completed; then the master device uses the instruction message attached with the address of the first-stage slave device to request the first-stage slave device to close the gating signal connected with the second-stage slave device;
s5: address assignment of other slave devices: according to step S4, by analogy, after the master device traverses all the slave devices in the entire system, the address allocation of all the slave devices is completed;
s6: the master device communicates according to the addressing mode of the address; specifically, the communication between the master device and the slave device does not depend on the gating signal, the master device attaches the address of the destination slave device when sending each instruction message, and only the slave devices with the matched addresses respond after receiving the instruction.
Preferably, the step S4 further includes: the master device records the interface to which each slave device is connected.
The invention provides a bus address distribution system based on cascade father node gating and a communication method thereof, which have the following beneficial effects:
the method is used in an expandable node cascade system, the master device can calculate the topological structures among all the slave devices by using the address allocation process, thereby coordinating the roles of all the nodes in the whole system according to a topological graph, and being used in an expandable system such as electronic module splicing and the like; after address allocation, the communication between the master device and other slave devices is no longer dependent on gating signals, the master device attaches the address of the target slave device when sending each instruction message, and only the slave devices with the consistent addresses respond after receiving the instruction, thereby avoiding collision.
Drawings
FIG. 1 is a schematic diagram illustrating a schematic structural diagram of a bus address allocation system based on cascaded parent node gating according to an embodiment of the present invention;
fig. 2 is a flow chart of a communication method in an embodiment of the invention.
Detailed Description
The invention is further described below with reference to the following figures and specific examples.
Referring to fig. 1, the present embodiment provides a bus address allocation system based on cascade father node gating, which includes a master device 1 and a plurality of slave devices, where the plurality of slave devices are respectively one or more first-level slave devices 21, one or more second-level slave devices 22, one or more third-level slave devices 23, one or more fourth-level slave devices 24, one or more fifth-level slave devices 25, … …, one or more N-1-level slave devices, and one or more nth-level slave devices; the master device 1 and the slave device are respectively provided with four interfaces, and each interface comprises a group of bus interfaces and a group of gating signal interfaces; the first-level slave device 21 is directly connected to the interface of the master device 1 through the bus 3 and the strobe signal 31, the second-level slave device 22 is connected to the interface of the first-level slave device 21 through the bus 3 and the strobe signal 31, the third-level slave device 23 is connected to the interface of the second-level slave device 22 through the bus 3 and the strobe signal 31, and so on, the nth-level slave device is connected to the nth-1-level slave device through the bus 3 and the strobe signal 31, namely the nth-level slave device is a lower-level device of the nth-1-level slave device, the buses 3 among all the devices are connected together, namely the devices are hung under the same bus 3.
The gating signal 31 follows the following rules: all the slave devices can receive the data sent by the master device 1, but only the gated slave devices allow the data to be sent to the bus 3; at most one slave device can be gated at any one time.
Each of said slave devices is provided with more than one joint 5.
Referring to fig. 1 and fig. 2, the present embodiment further provides a communication method using the address allocation system, including the following steps:
s1: closing the gating signal: the master equipment sends a broadcast message to inform all slave equipment to close the gating signals cascaded downwards, and the master equipment also closes all the gating signals;
s2: first level slave address assignment: the master device sequentially traverses all the interfaces of the master device, gates the first-stage slave devices of the corresponding interfaces, and distributes addresses to the gated first-stage slave devices by using address distribution instructions;
in the process, only the gated slave device can respond to the address allocation instruction, after the slave device responds successfully, the address of the slave device is allocated successfully, and the master device can close the gating signal;
s3: gated slave node partitioning: after the first-level equipment receives the broadcast address of the assigned address, the node of the interface cascade which is selected by the first-level slave equipment is identified as the upper-level node, namely the father node of the first-level slave equipment, and other interfaces are automatically classified as the lower-level cascade interface;
s4: second level slave address assignment: the master device sequentially traverses each interface of each first-stage slave device, requires the first-stage slave device to gate the appointed next-stage cascade interface by using an instruction message attached with the address corresponding to the first-stage slave device, and sends a response message to the master device after the first-stage slave device gates the appointed next-stage cascade interface to inform the master device that the appointed cascade interface is gated, so that address allocation can be carried out, and address allocation of the second-stage slave device connected with the appointed cascade interface is completed; then the master device uses the instruction message attached with the address of the first-stage slave device to request the first-stage slave device to close the gating signal connected with the second-stage slave device;
s5: address assignment of other slave devices: according to the steps and analogized, after the master device traverses all the slave devices in the whole system, the address allocation of all the slave devices is completed; in the process, the main device records the interface connected with each slave device, so that the cascade relation of the whole system can be obtained;
s6: the master device communicates according to the addressing mode of the address; specifically, the communication between the master device and the slave device is not dependent on the strobe signal, and the master device attaches the address of the destination slave device when sending each instruction message. Only the slave devices with the consistent addresses respond after receiving the instruction;
the bus address distribution system and the communication method based on the cascade father node gating have the following advantages that: in the cascade system used for the expandable node, the master device can calculate the topological structures among all the slave devices by using the address allocation process, thereby coordinating the roles of all the nodes in the whole system according to a topological graph; the method can be used in extensible systems such as electronic module splicing; after address allocation, the communication between the master device and other slave devices is no longer dependent on gating signals, the master device attaches the address of the target slave device when sending each instruction message, and only the slave devices with the consistent addresses respond after receiving the instruction, thereby avoiding collision.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (2)
1. A communication method of a bus address distribution system based on cascade father node gating is characterized in that: the method comprises the following steps:
s1: closing the gating signal: the master device sends a broadcast message to inform all slave devices of closing the gating signals cascaded downwards, and sets the gating signals as gated signals, and the master device also closes all the gating signals;
s2: first level slave address assignment: the master device sequentially traverses all the interfaces of the master device, gates the first-stage slave devices of the corresponding interfaces, and distributes addresses to the gated first-stage slave devices by using address distribution instructions through the bus;
in the process, only the gated slave device can respond to the address allocation instruction, after the slave device responds successfully, the address of the slave device is allocated successfully, and the master device closes the gating signal;
s3: gated slave node partitioning: after the first-level equipment receives the broadcast address of the assigned address, the node of the interface cascade which is selected by the first-level slave equipment is identified as the upper-level node, namely the father node of the first-level slave equipment, and other interfaces are automatically classified as the lower-level cascade interface;
s4: second level slave address assignment: the master device sequentially traverses each interface of each first-stage slave device, requires the first-stage slave device to gate the appointed next-stage cascade interface by using an instruction message attached with the address corresponding to the first-stage slave device, and sends a response message to the master device after the first-stage slave device gates the appointed next-stage cascade interface to inform the master device that the appointed cascade interface is gated, so that address allocation can be carried out, and address allocation of second-stage slave devices connected with the appointed cascade interface is completed; then the master device uses the instruction message attached with the address of the first-stage slave device to request the first-stage slave device to close the gating signal connected with the second-stage slave device;
s5: address assignment of other slave devices: according to step S4, by analogy, after the master device traverses all the slave devices in the entire system, the address allocation of all the slave devices is completed;
s6: the master device communicates according to the addressing mode of the address; specifically, the communication between the master device and the slave device does not depend on the gating signal, the master device attaches the address of the destination slave device when sending each instruction message, and only the slave devices with the matched addresses respond after receiving the instruction.
2. The communication method according to claim 1, wherein: the step S4 further includes: the master device records the interface to which each slave device is connected.
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| CN104881382A (en) * | 2015-06-15 | 2015-09-02 | 刘晓辉 | Master and slave equipment connection device and address recognition method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020138156A1 (en) * | 2001-01-25 | 2002-09-26 | Wong Isaac H. | System of connecting multiple processors in cascade |
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| CN101499046A (en) * | 2008-01-30 | 2009-08-05 | 鸿富锦精密工业（深圳）有限公司 | SPI equipment communication circuit |
| CN101630298A (en) * | 2009-07-28 | 2010-01-20 | 中兴通讯股份有限公司 | Serial bus slave address setting system |
| CN102523141A (en) * | 2011-11-25 | 2012-06-27 | 中国科学院光电技术研究所 | Method for networking and cascading electronic equipment by using universal serial port technique |
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