CN109614214B - MILP-based partition mapping scheduling method for distributed IMA architecture - Google Patents

MILP-based partition mapping scheduling method for distributed IMA architecture Download PDF

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CN109614214B
CN109614214B CN201811512375.0A CN201811512375A CN109614214B CN 109614214 B CN109614214 B CN 109614214B CN 201811512375 A CN201811512375 A CN 201811512375A CN 109614214 B CN109614214 B CN 109614214B
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宋佳静
凌翔
陈亦欧
高溦
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a partition mapping scheduling method facing to a distributed IMA architecture based on MILP, which comprises the following steps: the method comprises the steps of establishing a system model facing distributed IMA framework partition scheduling, comprehensively considering partition hard real-time constraint conditions, resource constraint conditions, partition mapping constraint conditions, processor activation conditions, two-partition same-core constraint conditions, time resource isolation constraint conditions, communication partition chain worst end-to-end delay constraint conditions and binary variable constraint conditions, minimizing the number of used processors as a target function, solving the mapping scheduling problem of partitions on the distributed heterogeneous multiprocessor by establishing an MILP model, and obtaining an optimal scheduling scheme using the least processors. Therefore, the invention can effectively solve the mapping scheduling problem of partitions with space-time resource isolation and worst end-to-end communication delay requirements on heterogeneous multiprocessors under the distributed IMA architecture.

Description

MILP-based partition mapping scheduling method for distributed IMA architecture
Technical Field
The invention relates to the technical field of comprehensive modular avionics systems, in particular to a partition mapping scheduling method facing a distributed IMA architecture based on MILP.
Background
With the increase of airplane functions, design requirements and the improvement of electronic technology, an avionics system integrates and manipulates numerous sensors, actuators and controllers, which makes the avionics system more and more important for the safety and reliability of an airplane, and also puts higher demands on the weight power consumption and the economic comfort of the airplane. An Integrated Modular Avionics (IMA) system can reside in a wide variety of applications with different functions and different safety levels, and integrates the traditional and independent Avionics systems on a common platform, so that the Integrated modular Avionics system has the advantages of small volume, light weight, low equipment energy consumption, flexibility, expandability and the like, and is widely applied to the Avionics industry.
The IMA architecture supports independent development of various real-time avionics applications on a shared computing platform and enables all applications to execute within spatially and temporally isolated partitions. Spatial isolation means that each partition has independent system resources (such as memory, etc.); temporal isolation refers to each partition using a pre-assigned time window to perform the tasks therein. The partition mechanism effectively avoids the mutual influence among different security level applications, thereby effectively improving the reliability and the security of the IMA system. In addition, because of inter-partition memory isolation, it can only transmit data by way of communication, in an on-board system, a communication partition chain is composed of a set of ordered partition sequences with data transmission, typically originating from sensors or user input, and sent to actuators or screens after being processed by one or more partitions, at which time delay constraints need to be imposed on the partition chain based on the criticality of data operation, limiting the end-to-end latency to within a predefined range to obtain satisfactorily stable system performance. While the IMA architecture can achieve effective cost reduction and reliability enhancement in the development of avionics systems, it presents a more complex mapping scheduling problem that not only needs to consider schedulability of partitions with strict cycle requirements on the same processor, but also needs to perform end-to-end delay analysis.
At present, most of researches on IMA partition scheduling only consider one-sided constraints and are limited in the scenes of homogeneous processors, but in practical application, more and more embedded systems use heterogeneous processors to cooperatively process tasks.
Disclosure of Invention
At least one of the objectives of the present invention is to provide a partition mapping scheduling method based on MILP for a distributed IMA architecture, so as to solve the problem of mapping scheduling of partitions with space-time resource isolation and worst end-to-end communication delay requirements on heterogeneous multiprocessors in the distributed IMA architecture, where the method can guarantee hard real-time requirements of the partitions and use the minimum number of processors.
In order to achieve the above object, the present invention adopts the following aspects.
A partition mapping scheduling method based on MILP facing to a distributed IMA architecture comprises the following steps:
step 101, establishing a system model facing distributed IMA architecture partition mapping scheduling, wherein the system model facing distributed IMA architecture partition mapping scheduling comprises a processing module sub-model, a partition task sub-model and a communication partition chain sub-model; the processing module submodel comprises a plurality of central processing units, the partition task submodel consists of a plurality of partitions, and the communication partition chain submodel comprises a plurality of communication partition chains;
102, setting a constraint condition of the partitioned mapping scheduling facing the distributed IMA architecture based on the performance of a central processing unit, the hard real-time requirement and strict cycle attribute of a partitioned task, the space-time resource isolation requirement among the plurality of partitions and the upper limit of end-to-end communication delay of a communication partition chain under the worst condition;
103, establishing a mixed integer linear programming model for the partitioned mapping scheduling of the distributed IMA architecture by taking the minimized number of the central processing units as an objective function and the constraint condition for the partitioned mapping scheduling of the distributed IMA architecture as a constraint condition;
and 104, solving the mixed integer linear programming model to obtain the partition scheduling scheme which uses the least processors for the distributed IMA architecture.
Preferably, in the partition mapping scheduling method, the constraint condition of the partition mapping scheduling for the distributed IMA architecture includes: the system comprises a partition hard real-time constraint condition, a resource constraint condition, a partition mapping constraint condition, a processor activation condition, a two-partition same-core constraint condition, a time resource isolation constraint condition, a communication partition chain worst end-to-end delay constraint condition and a binary variable constraint condition.
Preferably, in the partition mapping scheduling method, the partition hard real-time constraint condition is:
Figure BDA0001901117720000031
wherein, piiFor the ith partition, pi ═ pi1,π2,…πNIs the set of said plurality of partitions, TiIs a partition piiPeriod of (a) siIs a partition piiTime offset of first execution, mapi,kE {0,1} is partition piiMapping to a central processor pkResult of the mapping of (2), map i,k1 represents a partition piiIs mapped onto the processor pk.
Preferably, in the partition mapping scheduling method, the resource constraint condition is set based on the performance of the central processing unit, where the performance of the central processing unit includes the maximum number of partitions that can be borne by the central processing unit and the maximum capacity of the local memory carried by the central processing unit.
Preferably, in the partition mapping scheduling method, the partition mapping constraint condition indicates that each partition has and can only be mapped to one central processor.
Preferably, in the partition mapping scheduling method, the processor activation condition is:
Figure BDA0001901117720000032
pk∈P,mapi,k≤prok；
Figure BDA0001901117720000033
wherein pi is ═ { pi-1,π2,…πNIs the set of said plurality of partitions, piiFor the ith partition, P ═ P1,p2,…,pKIs a collection of multiple CPUs, pkIs the kth central processing unit; prokE {0,1} is processor usage, prokDenotes a processor p for 1kIs used.
Preferably, in the partition mapping scheduling method, the constraint condition of the two partitions and the same core is set based on the mapping relationship of the partitions; introducing variable sepijE {0,1} to characterize partition πiAnd pijWhen the partition is piiAnd partition pijWhen mapped onto the same processor, sep ij0, when partition piiAnd partition pijWhen mapped onto different processors, sep ij1, the two-partition homonuclear constraint is characterized as:
Figure BDA0001901117720000041
πj∈Π,
Figure BDA0001901117720000042
i≠j,mapi,k+mapj,k+sepij≤2；
Figure BDA0001901117720000043
πj∈Π,
Figure BDA0001901117720000044
pl∈P,i≠j,k≠l,mapi,k+mapj,l-sepij≤1。
preferably, in the partition mapping scheduling method, the time resource isolation constraint condition is set based on non-overlapping of partition execution times mapped to the same processor.
Preferably, in the partition mapping scheduling method, the worst end-to-end delay constraint condition of the communication partition chain is set based on an end-to-end communication delay upper limit of the communication partition chain under the worst condition.
Preferably, in the partition mapping scheduling method, the central processing unit is a heterogeneous processor.
In summary, due to the adoption of the technical scheme, the invention at least has the following beneficial effects:
according to the method, the hard real-time and strict periodic attributes of partition tasks, the space-time resource isolation requirements among partitions and the end-to-end communication delay constraint of a communication partition chain under the worst condition are comprehensively considered, the mapping scheduling problem of the partitions on the distributed heterogeneous multiprocessor is solved by establishing a mixed integer linear programming model, and the optimal mapping scheduling scheme using the least processors can be obtained;
meanwhile, the method can be simultaneously applied to harmonic period and non-harmonic period situations, and has strong practicability.
Drawings
Fig. 1 is a flowchart of a partition mapping scheduling method based on MILP for a distributed IMA architecture according to an exemplary embodiment of the present invention;
fig. 2 is a platform architecture diagram of a distributed IMA system in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a representation of an IMA partition task model according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a communication zone chain worst end-to-end delay according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic diagram of worst case communication delays between consecutive partitions in accordance with an illustrative embodiment of the present invention;
FIG. 6 is a schematic diagram of simulation parameter settings according to an exemplary embodiment of the present invention;
FIG. 7 is a communication zone chain diagram in accordance with an exemplary embodiment of the present invention;
FIG. 8 is a schematic illustration of harmonic partition mapping scheduling results according to an exemplary embodiment of the invention;
FIG. 9 is a schematic diagram of non-harmonic partition mapping scheduling results according to an exemplary embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and embodiments, so that the objects, technical solutions and advantages of the present invention will be more clearly understood. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 shows a partition mapping scheduling method based on MILP for a distributed IMA architecture according to an exemplary embodiment of the present invention, which mainly includes:
step 101, establishing a system model facing distributed IMA architecture partition mapping scheduling, wherein the system model facing distributed IMA architecture partition mapping scheduling comprises a processing module sub-model, a partition task sub-model and a communication partition chain sub-model; the processing module submodel comprises a plurality of central processing units, the partition task submodel consists of a plurality of partitions, and the communication partition chain submodel comprises a plurality of communication partition chains;
102, setting a constraint condition of the partitioned mapping scheduling facing the distributed IMA architecture based on the performance of a central processing unit, the hard real-time requirement and strict cycle attribute of a partitioned task, the space-time resource isolation requirement among the plurality of partitions and the upper limit of end-to-end communication delay of a communication partition chain under the worst condition;
103, establishing a mixed integer linear programming model for the partitioned mapping scheduling of the distributed IMA architecture by taking the minimized number of the central processing units as an objective function and the constraint condition for the partitioned mapping scheduling of the distributed IMA architecture as a constraint condition;
and 104, solving the mixed integer linear programming model to obtain the partition scheduling scheme which uses the least processors for the distributed IMA architecture.
Specifically, a system model facing distributed IMA architecture partition mapping scheduling is established, wherein the system model comprises a processing module sub-model, a partition task sub-model and a system communication chain sub-model. The method specifically comprises the following steps:
processing module submodels: figure 2 shows a platform architecture diagram of a typical distributed IMA system. The processing Module submodel in the IMA system of this embodiment includes K (K > 1) general processing modules (modules), where each general processing Module has one cpu running therein, and the cpus are heterogeneous processors with different processing capabilities, and the set P ═ { P ═ is1,p2,…,pKRepresents it. The central processing unit pkFrom a doublet pk＝{Hk,MkCharacterization, HkAnd MkRespectively representing processors pkThe maximum number of partitions that can be carried and the maximum capacity available for the local memory carried by the processor.
And (3) partitioning task submodels: given N partition tasks form a partition set pi ═ pi1,π2,…πNTherein, the partition piiFrom the quintuple ni＝{{bi,k},Ti,mi,si,{mapi,kAnd } characterization. In connection with the IMA partition task characterization diagram shown in fig. 3, partitions have hard real-time properties of strict periodicity. Wherein b isi,kIs a partition piiAt processor pkThe Worst Case Execution Time (WCET); t isiIs a partition piiPeriod of (2) of
Figure BDA0001901117720000062
Ti≥b i,k0 or more and the deadline of a partition is equal to its period; m isiIs a partition piiThe required memory capacity, it should be noted that, to protect the partitioned data and prevent any modification from other partitions, a partition needs an independent memory area to satisfy a space isolation mechanism; siIs a partition piiTime offset of first execution; binary variable mapi,kE {0,1} characterizes the partition piiThe mapping result of (1), mapi ,k1 represents a partition piiIs mapped to a processor pkThe above.
System communication chain model: in the system, C communication partition chains are arranged, wherein lambda is equal to { lambda1,λ2,…λCEach communication partition chain is a group of ordered partition sequences with data transmission, the partition chains are independent, and each communication partition chain has an end-to-end delay index
Figure BDA0001901117720000063
Representing the maximum duration that the source partition can tolerate to generate data to the first use of the destination partition. By λc(i) Denotes a partition chain lambdacThe ith partition of the chain, the worst case communication time length between two consecutive partitions of the chain being recorded as
Figure BDA0001901117720000061
For example, partition 1 implements the data collection function and partition 2 is responsible for the backup recording work, the delay between the start of partition 1 to the end of partition 2 should not exceed 0.5 seconds, and the worst communication delay must be considered in the analysis if the two partitions are mapped to different processors.
Specifically, the IMA system model is oriented to comprehensively consider hard real-time and strict cycle attributes of partition tasks, space-time resource isolation requirements among partitions, end-to-end communication delay limitation of communication partition chains and necessary system constraints, and a constraint condition and an objective function of a mixed integer linear programming are established. The constructed constraints include:
to meet the hard real-time nature of the partition's mission critical cycle, the partition must complete execution before the deadline. Therefore, the hard real-time constraint conditions of the partitions are set as follows:
Figure BDA0001901117720000071
setting a resource constraint condition based on the maximum bearable partition number of the plurality of central processing units and the maximum capacity of the local memory carried by the maximum bearable partition number, wherein the resource constraint condition is as follows:
Figure BDA0001901117720000072
setting a partition mapping constraint by each partition having and being mapped to only one central processor, the partition mapping constraint being:
Figure BDA0001901117720000073
since the present invention aims to obtain a scheduling mapping method with a minimum of processors, a binary variable pro is introducedkE {0,1} to characterize processor usage when at least one partition is mapped to processor pkWhen above, prokSet 1 when no partition is mapped to processor pkWhen above, prokSet to 0, the resulting processor activation constraint is:
Figure BDA0001901117720000074
pk∈P,mapi,k≤prok；
Figure BDA0001901117720000075
since the partitions have temporal isolation constraints, it is necessary to perform a time-non-overlapping analysis on partitions mapped onto the same processor, for which we introduce a binary variable sepijE {0,1} represents partition πiAnd pijMap of (1), sep ij0 denotes a partition piiAnd partition pijIs mapped onto the same processor, and sep ij1 denotes a partition piiAnd pijAre mapped onto different processors. And thus two partition corelness constraints are obtained:
Figure BDA0001901117720000081
πj∈Π,
Figure BDA0001901117720000082
∈P,i≠j,mapi,k+mapj,k+sepij≤2；
Figure BDA0001901117720000083
πj∈Π,
Figure BDA0001901117720000084
pl∈P,i≠j,k≠l,mapi,k+mapj,l-sepij≤1。
in order to realize the time isolation among the partitions, the execution time of the partitions mapped on the same processor is ensured not to overlap, and two partitions pi can be known by theorems in the literature by searching relevant literatureiAnd pijThe requirements for scheduling non-overlapping execution on the same processor are as follows: bi≤(sj-si)mod(gij)≤gij-bjWherein, biAnd bjAre each a partition piiAnd pijExecution time on homogeneous processors; gijIs a partition piiAnd pijGreatest common divisor of cycles, i.e. gij＝gcd(Ti,Tj). To ensure the partition piiAnd pijIs mapped onto a different processor (i.e., sep)ij1) the condition of no overlap is constantly satisfied, and a large constant positive integer Z is introduced. Secondly, the scene is expanded to the scene of the heterogeneous processor, and the above-mentioned essential conditions can be adjusted as follows:
Figure BDA0001901117720000085
πj∈Π,i≠j,
Figure BDA0001901117720000086
in addition, since the modulo operation is a nonlinear operation that cannot be directly applied to the MILP model, the modulo operation is linearized as:
(sj-si)mod(gij)＝(sj-si)-qjigij，
Figure BDA0001901117720000087
wherein q isjiAre integers and have the following value ranges:
Figure BDA0001901117720000088
πj∈Π,i≠j,
Figure BDA0001901117720000089
and finally, setting the worst end-to-end delay constraint condition of the communication partition chain according to the end-to-end delay index of each communication partition chain in the comprehensive modular avionics system model:
Figure BDA00019011177200000810
wherein the content of the first and second substances,
Figure BDA00019011177200000811
representing a communication zone chain lambdacThe worst-case end-to-end delay time for the first use of the data generated by the middle source partition to the target partition is composed of two parts, wherein the first part refers to the sum of corresponding execution time lengths after each partition is mapped onto a heterogeneous processor, and the second part refers to the sum of worst-case communication delays existing among all continuous partitions. FIG. 4 is a drawing of a group pii、πjAnd pikSchematic diagram of worst end-to-end delay condition of composed communication partition chain, which is mapped to processor pn、pmAnd plThe above. DλcThe maximum duration that the chain can tolerate cannot be exceeded. In addition, in the formula
Figure BDA0001901117720000091
Representing a communication zone chain lambdacIn two consecutive divisions λc(i) And λc(i +1) worst-case communication delay between partitions, which depends on the mapping of partitions, when two partitions are mapped to the same processor, the upper delay bound is taken into account
Figure BDA0001901117720000092
The worst case occurs in partition λ when mapping onto different processorsc(i) Happens to be in the partition lambdacWhen (i +1) arrives after operation, as shown in fig. 5, the worst delay time needs to be considered in addition to the communication time period between the two partitions
Figure BDA0001901117720000093
In summary,
Figure BDA0001901117720000094
can be expressed as:
Figure BDA0001901117720000095
since we introduce binary variables in the process of building this mixed integer linear programming algorithm model: mapi,k、prokAnd sepij. Therefore, binary variable constraints are also set:
Figure BDA0001901117720000096
πj∈Π,
Figure BDA0001901117720000097
i≠j
mapi,k∈{0,1}
prok∈{0,1}
sepij∈{0,1}。
finally, to achieve scheduling using a minimum of processors, we target a minimum number of processors used as partition map scheduling, namely:
Figure BDA0001901117720000098
based on the above hard real-time constraint condition of the partitions, the resource constraint condition, the partition mapping constraint condition, the processor activation condition, the two-partition homonuclear constraint condition, the time resource isolation constraint condition, the worst end-to-end delay constraint condition of the communication partition chain and the binary variable constraint condition, the mixed integer linear programming model is solved by taking the minimization of the number of the processors as an objective function, and the obtained optimal solution is the optimal mapping scheduling scheme of the comprehensive modular avionic system model.
In order to further verify the performance of the mapping scheduling algorithm designed by the invention, the mapping scheduling algorithm is simulated by using a specific test case. During the simulation, we used Gurobi (a large-scale mathematical programming optimizer) as the solver for the mixed integer linear programming model. The computer running the simulation had Intel (R) core (TM) i5-4590 CPU 3.30GHz and 10.00GB of system memory. The software platforms are matlab 2015b, yalcip R10260930 and Cplex 12.5.
We first simulated the mapping scheduling algorithm proposed in this study using a small helicopter test case. TheIn the experimental example, 7 partitions exist, 4 heterogeneous processors are distributed in the IMA system, and the processor attribute pk＝{Hk,MkPeriod T of partitioniMemory capacity m required for partitioniAnd execution time of partitions on heterogeneous processors bi,kFig. 6. Furthermore, consider that there are two communication partition chains in the system, as shown in fig. 7, chain 1 is composed of partition 3, partition 4, and partition 2, and chain 2 is composed of partition 6, partition 1, and partition 7, the communication duration between any two consecutive partitions is as marked in the figure, and the maximum end-to-end delay that can be tolerated by the two communication partition chains is 123 and 80, respectively.
The simulation objective function is set to minimize the number of processors required for mapping and scheduling, and the partition mapping and scheduling result obtained by the solver is shown in fig. 8, in which case, at least 3 processors are required and the solution time is 0.12 s.
As can be seen from the mapping and scheduling result graph obtained by simulation, the execution times of all the partitions do not overlap, in addition, the number of the partitions loaded on the four processors is respectively 3, 0, and 1, and the total memory capacity required by the partitions on each processor is respectively 15, 13, 0, and 9, which do not exceed the limit condition of each processor. As for the communication partition chain, three partitions of chain 1 are mapped onto the same processor with an end-to-end delay of 22.5; the first two partitions in chain 2 are mapped onto the same processor, and their worst end-to-end communication delay is 45, which does not exceed a tolerable threshold.
In order to further verify the applicability of the study to partition period non-harmonic, the periods of 7 partitions in the above example were changed to 20, 40, 100, 50, 40, 50, and 25, and other system parameters were not changed. At this time, the simulation result using the least processors is shown in fig. 9, in which case, at least 2 processors are required, and the solution time is 0.15 s. The result is analyzed, and the hard real-time requirement, the partition time space resource isolation constraint and the worst end-to-end communication delay limit are also met.
In conclusion, the mapping scheduling method provided by the invention can effectively solve the problem of mapping scheduling of partitions with space-time resource isolation and worst end-to-end communication delay requirements on a heterogeneous multiprocessor under a distributed IMA architecture, can be simultaneously applied to harmonic cycle and non-harmonic cycle situations, and can obtain an optimal scheduling scheme.
The foregoing is merely a detailed description of specific embodiments of the invention and is not intended to limit the invention. Various alterations, modifications and improvements will occur to those skilled in the art without departing from the spirit and scope of the invention.

Claims (9)

1. A partition mapping scheduling method facing a distributed IMA architecture based on MILP is characterized by comprising the following steps:
step 101, establishing a system model facing distributed IMA architecture partition mapping scheduling, wherein the system model facing distributed IMA architecture partition mapping scheduling comprises a processing module sub-model, a partition task sub-model and a communication partition chain sub-model; the processing module submodel comprises a plurality of central processing units, the partition task submodel consists of a plurality of partitions, and the communication partition chain submodel comprises a plurality of communication partition chains;
102, setting a constraint condition of the partitioned mapping scheduling facing the distributed IMA architecture based on the performance of a central processing unit, the hard real-time requirement and strict cycle attribute of a partitioned task, the space-time resource isolation requirement among the plurality of partitions and the upper limit of end-to-end communication delay of a communication partition chain under the worst condition; wherein the space-time resource isolation requirements among the plurality of partitions include: setting based on non-overlapping partition execution times mapped on the same processor and non-overlapping partition execution times mapped on different processors, wherein the requirements that the partition execution times mapped on the different processors are not overlapped are as follows:
Figure FDA0002671619870000011
Figure FDA0002671619870000012
wherein, piiFor the ith partition, pi ═ pi1,π2,…πNIs a set of the plurality of partitions; piiIs the jth partition; mapi,kE {0,1} is partition piiMapping to a central processor pkResult of the mapping on, binary variable sepijE {0,1} characterizes the partition piiAnd pijThe mapping relationship of (2); bi,kIs a partition piiIn the central processing unit pkThe execution time of (1); (s)i-sj)mod(gij) Is a modulo operation; gijIs a partition piiAnd pijA greatest common divisor of the periods; z is a constant positive integer; siIs a partition piiTime offset of first execution; mapj,kIs a partition pijMapping to a central processor pkThe mapping result of (2); bj,kIs a partition pijIn the central processing unit pkThe execution time of (1); sjIs a partition pijTime offset of first execution;
103, establishing a mixed integer linear programming model for the partitioned mapping scheduling of the distributed IMA architecture by taking the minimized number of the central processing units as an objective function and the constraint condition for the partitioned mapping scheduling of the distributed IMA architecture as a constraint condition; p is a set of multiple processors;
and 104, solving the mixed integer linear programming model to obtain the partition scheduling scheme which uses the least processors for the distributed IMA architecture.
2. The partition mapping scheduling method of claim 1, wherein the constraints of the partitioned mapping scheduling for the distributed IMA architecture include: the system comprises a partition hard real-time constraint condition, a resource constraint condition, a partition mapping constraint condition, a processor activation condition, a two-partition same-core constraint condition, a time resource isolation constraint condition, a communication partition chain worst end-to-end delay constraint condition and a binary variable constraint condition.
3. The partition map scheduling method of claim 2, wherein the partition hard real-time constraint is:
Figure FDA0002671619870000021
wherein, piiFor the ith partition, pi ═ pi1,π2,…πNIs the set of said plurality of partitions, TiIs a partition piiPeriod of (a) siIs a partition piiTime offset of first execution, mapi,kE {0,1} is partition piiMapping to a central processor pkResult of the mapping of (2), mapi,k1 represents a partition piiIs mapped to a processor pkThe above step (1); bi,kIs a partition piiIn the central processing unit pkP is a set of multiple processors.
4. The partition mapping scheduling method according to claim 2, wherein the resource constraint condition is set based on the performance of the central processing unit, and the performance of the central processing unit includes the maximum bearable partition number of the central processing unit and the maximum capacity of the local memory carried by the central processing unit.
5. The partition mapping scheduling method of claim 2, wherein the partition mapping constraint indicates that each partition has and can only be mapped to one central processor.
6. The partition mapping scheduling method according to claim 2, wherein the processor activation condition is:
Figure FDA0002671619870000031
Figure FDA0002671619870000032
wherein pi is ═ { pi-1,π2,…πNIs the set of said plurality of partitions, piiFor the ith partition, P ═ P1,p2,…,pKIs a collection of multiple CPUs, pkIs the kth central processing unit; prokE {0,1} is processor usage, prokDenotes a processor p for 1kIs used.
7. The partition mapping scheduling method according to claim 2, wherein the constraint condition of the two partitions and the core is set based on the mapping relationship of the partitions; introducing variable sepijE {0,1} to characterize partition πiAnd pijWhen the partition is piiAnd partition pijWhen mapped onto the same processor, sepij0, when partition piiAnd partition pijWhen mapped onto different processors, sepij1, the two-partition homonuclear constraint is characterized as:
Figure FDA0002671619870000033
Figure FDA0002671619870000034
8. the partition mapping scheduling method according to claim 2, wherein the worst end-to-end delay constraint condition of the communication partition chain is set based on an upper end-to-end communication delay limit of the worst-case communication partition chain.
9. The partition mapping scheduling method of any of claims 1-8, wherein the central processor is a heterogeneous processor.
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