CN109586734A - Interpretation method and its signal processing circuit for signal processing circuit - Google Patents
Interpretation method and its signal processing circuit for signal processing circuit Download PDFInfo
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- CN109586734A CN109586734A CN201811196022.4A CN201811196022A CN109586734A CN 109586734 A CN109586734 A CN 109586734A CN 201811196022 A CN201811196022 A CN 201811196022A CN 109586734 A CN109586734 A CN 109586734A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
- H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/80—Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
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Abstract
The invention discloses a kind of interpretation method and its signal processing circuit for signal processing circuit, which receives a modulation data as entrained by a coil signal, which includes the jitter feature for judging the coil signal；When the jitter feature occurs, a triggering notch is obtained；When the length of the triggering notch is located at a preset range, a notch indication signal is exported；Judge whether to occur multiple notch indication signals in a first period and multiple notch indication signal was dispersed in the first period；It is a dither signal by a flag tag according to above-mentioned judging result；Within a second phase, judge whether the mark is marked as dither signal, and inserts a numerical value in a period of time layout for corresponding to the second phase accordingly；And according to it is multiple when layout in the numerical value inserted, obtain a numeric data code of the modulation data.
Description
Technical field
The present invention relates to a kind of interpretation method more particularly to a kind of signal processings that can be used in inductive power-supply supply device
The interpretation method of circuit.
Background technique
In inductive power-supply supply device, for safe operation, need to confirm induction zone in its power supply coil in feed end
Domain be correct power receiving device, just and electric power transmission is carried out under the situation that can receive electric power, in order to enable feeder ear to know
Whether other receiving end is correct power receiving device, needs to be identified by numeric data code transmission.The transmission of numeric data code can pass through
Feeder ear drives power supply coil to generate resonance, sends electromagnetic energy and is transmitted to receiving end, to carry out power transmission, and in receiving end
When receiving electric power, the impedance state on receiving coil can be changed by signal modulation technique, then pass through feedback influence power supply coil
On resonance carrier signal variation, to transmit numeric data code.
In above-mentioned inductive power-supply supply device, since numeric data code is passed between power supply coil and power receiving coil
Send, thus the transmission of numeric data code is usually associated with the different electric power of intensity and sends so that the numeric data code that receives of feeder ear vulnerable to
To the interference of power supply noise.Therefore, how under the noise jamming of varying strength effective interpretation data code has become industry urgently
One of the target to be made great efforts.
Summary of the invention
Therefore, the main object of the present invention is to provide a kind of signal processing that can be used in inductive power-supply supply device
The interpretation method of circuit effectively to obtain numeric data code corresponding to coil signal, and excludes the dry of power supply noise or other noises
It disturbs.
The invention discloses a kind of interpretation methods, are used for a signal processing circuit, which receives by a line
A modulation data entrained by ring signal, the interpretation method include: to receive the coil signal, and judge that the one of the coil signal trembles
Dynamic feature；When the jitter feature appears in a crest location of multiple wave crests on the coil signal, a triggering notch is obtained；Sentence
The length of the triggering notch of breaking exports a notch indication signal when the length of the triggering notch is located at a preset range；Judgement
Whether occur multiple notch indication signals in one first period, and judge multiple notch indication signal whether be dispersed in this first
During；According to judging whether to occur multiple notch indication signal in the first period and judge multiple notch indication signal
One flag tag is a dither signal by the judging result whether being dispersed in the first period；Within a second phase, sentence
Whether the mark that breaks is marked as the dither signal, and accordingly for judge the modulation data it is multiple when layout in correspond to
A numerical value is inserted in a period of time layout of the second phase；And according to it is multiple when layout in multiple numerical value for inserting, obtaining should
One numeric data code of modulation data.
The invention also discloses a kind of signal processing circuits, for receiving a modulation number as entrained by a coil signal
According to, and the modulation data is decoded, which includes an at least comparator module and a processor.This is at least
One comparator module can be used to receive the coil signal, and judge a jitter feature of the coil signal.The processor is coupled to
The comparator module can be used to execute following steps: when the jitter feature appears in a wave of multiple wave crests on the coil signal
When peak position, a triggering notch is obtained；The length for judging the triggering notch, when the length of the triggering notch is located at a preset range
When, export a notch indication signal；Judge whether occur multiple notch indication signals in a first period, and judges multiple lack
Whether mouth indication signal was dispersed in the first period；According to judging whether to occur in the first period multiple notch instruction letter
Number and judge whether multiple notch indication signal is dispersed in the judging result in the first period, by a flag tag be one
Dither signal；Within a second phase, judge whether the mark is marked as the dither signal, and accordingly for judging the tune
Data processed it is multiple when layout in correspond to the second phase a period of time layout in insert a numerical value；And according to multiple time
The multiple numerical value inserted in lattice, obtain a numeric data code of the modulation data.
Detailed description of the invention
Fig. 1 is the schematic diagram of one power supply module of the embodiment of the present invention.
Fig. 2 is the schematic diagram that the embodiment of the present invention one decodes process.
Fig. 3 is that the embodiment of the present invention judges jitter feature to obtain the schematic diagram of triggering notch.
Fig. 4 A and 4B are for the embodiment of the present invention by queuing register come record dither and the schematic diagram of triggering notch.
Fig. 5 is that label of the embodiment of the present invention one indicates and corresponds to the signal that numerical value is written to dither signal queuing register
Figure.
Fig. 6 be the embodiment of the present invention according to when layout interval come the schematic diagram that judges start bit and numeric data code.
Fig. 7 is the waveform diagram for the coil signal that the embodiment of the present invention carries partial data string.
Wherein, the reference numerals are as follows:
1 power supply module
110 signal processing circuits
111 processors
112,113 comparator module
120 clock generators
121,122 for electric drive unit
130 bleeder circuits
131,132 divider resistance
141,142 resonant capacitance
151,153 voltage generating unit
152,154 comparator
16 power supply coils
161 magnetic conductors
C1 coil signal
20 decoding processes
200~216 steps
CP1, CP2 comparison result
V_P peak voltage level
V_D differentiates voltage level
TMR3 mark
During P1~P4
Specific embodiment
Referring to FIG. 1, Fig. 1 is the schematic diagram of one power supply module 1 of the embodiment of the present invention.Power supply module 1 can be used for an induction
Formula power supply unit, for send power to inductive power-supply supply device by electric module, and from by electric module receive modulation number
According to modulation data can be used for notifying the functions such as power supply state, adjustment power.Power supply module 1 includes a power supply coil 16 and resonance
Capacitor 141,142.Wherein, power supply coil 16 can be used to send electromagnetic energy to by electric module to be powered, resonant capacitance
141,142 it is coupled to power supply coil 16, can be used to the progress resonance of power supply coil 16 of arranging in pairs or groups.In addition, in power supply module 1, it is optional
Kept away simultaneously using the magnetic conductor 161 that magnetic material is constituted for promoting the electromagnetic induction ability of power supply coil 16 to selecting property
Exempting from electromagnetic energy influences the object in coil non-inductive face direction.
For the running of control power supply coil 16 and resonant capacitance 141,142, power supply module 1 further includes a clock generator
120, for electric drive unit 121 and 122, one signal processing circuit 110 and a bleeder circuit 130.Wherein, clock generator 120
And be used to that power supply coil 16 is driven to send electric power for electric drive unit 121 and 122, Detailed Operation mode should be art technology
Known to personnel, this will not be repeated here.Bleeder circuit 130 includes divider resistance 131 and 132, can be to the line in power supply coil 16
After ring signal C1 is decayed, signal processing circuit 110 is output this to.In some embodiments, if signal processing circuit
110 have enough pressure resistances, can not also use bleeder circuit 130, directly be received in power supply coil 16 by signal processing circuit 110
Coil signal C1.
Signal processing circuit 110 can detect modulated signal on coil signal C1, and take out modulation number by decoded mode
According to.In general, power supply module 1 and its it is corresponding by electric module be that data are transmitted by specified communication mode, it is real one
It applies in example, can be encoded by transmitting the time interval length of modulated signal, in rear detailed description.As shown in Figure 1, signal processing
Circuit 110 includes a processor 111 and comparator module 112,113.It is noted that in some embodiments, processor 111
Other than it can be utilized for data interpretation, starting has been provided simultaneously with for electric drive unit 121 and the function of 122 output drive signals
Energy.Therefore, the setting of processor 111 is independently of except signal processing circuit 110, and without being limited thereto.
Referring to FIG. 2, Fig. 2 is the schematic diagram that the embodiment of the present invention one decodes process 20.Decoding process 20 can be used for incuding
Signal processing circuit in the power supply module of formula power supply unit, signal processing circuit 110 as shown in Figure 1, for coming from
It is decoded in the modulation data of receiving end, modulation data is to be sent to signal processing circuit as entrained by coil signal C1
110.As shown in Fig. 2, decoding process 20 the following steps are included:
Step 200: starting.
Step 202: receiving coil signal C1, and judge shake (jitter) feature of coil signal C1.
Step 204: when jitter feature appears in a crest location of multiple wave crests on coil signal C1, obtaining a triggering
Notch.
Step 206: the length of judgement triggering notch, when the length for triggering notch is located at a preset range, output one is lacked
Mouth indication signal.
Step 208: judging whether occur multiple notch indication signals in a first period, and judge multiple notch instruction
Whether signal is dispersed in first period.
Step 210: according to judging whether to occur multiple notch indication signals in first period and judge that multiple notch refers to
Show the judging result whether signal was dispersed in first period, is a dither signal by a flag tag.
Step 212: within a second phase, whether judgement symbol is marked as dither signal, and accordingly for judging
Modulation data it is multiple when layout in correspond to the second phase a period of time layout in insert a numerical value.
Step 214: according to it is multiple when layout in multiple numerical value for inserting, obtain a numeric data code of modulation data.
Step 216: terminating.
According to decoding process 20, signal processing circuit 110 can first judge a jitter feature (step of coil signal C1
202), and then triggering notch (step 204) is obtained.Specifically, referring to FIG. 3, Fig. 3 is that judgement shake of the embodiment of the present invention is special
Sign triggers the schematic diagram of notch to obtain.Fig. 3 show coil signal C1, comparator module 112 a comparison result CP1, with
An and comparison result CP2 of comparator module 113.Specifically, comparator module 112 or 113 is all by comparator plus electricity
Pressure generates unit and is constituted, and comparator module 112 includes a voltage generating unit 151 and a comparator 152, comparator module
113 include a voltage generating unit 153 and a comparator 154.Wherein, comparator module 112 can be used to tracking coil signal C1
Peak voltage, specifically, processor 111 exportable one sets data to comparator module 112, with control voltage generate it is single
Member 151 generates a peak voltage level V_P, so that comparator 152 may compare peak voltage level V_P and coil signal C1.?
In one coil cycle of oscillation, when the crest height of coil signal C1 exceeds peak voltage level V_P, what comparator 152 exported
There is a pulse signal (triggering) in comparison result CP1, and in this case, the change of processor 111 is supplied to voltage generation
The setting data of unit 151 are to improve peak voltage level V_P；In a coil cycle of oscillation, when the wave crest of coil signal C1
When height is lower than peak voltage level V_P, the comparison result of comparator 152 persistently exports low level (not triggering),
Under this situation, processor 111 changes the setting data for being supplied to voltage generating unit 151 to reduce peak voltage level V_P.It is logical
Aforesaid way is crossed, so that peak voltage level V_P keeps track the crest voltage of coil signal C1, comparison result CP1 is then presented
When and the when of triggering and the state without triggering, as shown in Figure 3.
Then, peak voltage level V_P can be reduced a predetermined value by processor 111, differentiate voltage level to obtain one
V_D, and the voltage generating unit 153 of related setting data to comparator module 113 is exported, to control voltage generating unit 153
It generates and differentiates voltage level V_D, so that comparator 154 is comparable to differentiate voltage level V_D and coil signal C1.General normal
In the case where oscillation, since peak voltage level V_P keeps track the crest voltage of coil signal C1, voltage level is differentiated
V_D is consistently less than the crest voltage of coil signal C1.In this case, comparison result CP2 is sent out in each coil cycle of oscillation
Raw triggering.However, crest voltage will appear larger when receiving modulated signal or data shake coil signal C1
The decline of width, if crest voltage deteriorates to less than when differentiating voltage level V_D, comparison result CP2 will appear of short duration triggering and lack
Mouth (i.e. at least a coil cycle of oscillation does not occur trigger signal, as shown in Figure 3).
Processor 111 can further judge to trigger the length of notch, i.e. the continuous oscillation period number that does not occur trigger signal
Amount.In general, modulated signal/data receive only can generate of short duration fluctuation up and down in the peak value of coil signal C1, so that
The length of triggering notch is fallen in a certain range.Too long triggering notch may be from the change in coil output power or load
Change, too short triggering notch may be from noise jamming.In this case, processor 111 can set a preset range, and
On each coil cycle of oscillation, judge whether the length for triggering notch falls within a preset range.For example, processor 111 can
The range of setting 3~5, and be greater than or equal to the length of three coil cycles of oscillation in the length of triggering notch and be less than or wait
(continuous 3~5 coil cycles of oscillation, upper comparison result CP2 generation did not triggered when the length of five coil cycles of oscillation
Situation), export a notch indication signal (step 206).
In one embodiment, processor 111 can be by the queue of register come the state of record dither and triggering notch, team
Column register can update numerical value in each coil cycle of oscillation, for example, newest numerical value can enter the minimum bit of queue, in queue
For each numerical value originally stored sequentially to larger Bit Shift, the numerical value of dominant bit then removes queue.Please refer to Fig. 4 A and 4B, Fig. 4 A
And 4B be the embodiment of the present invention by queuing register come record dither and trigger notch schematic diagram.Wherein, comparator triggers
State queue register is used to record comparison result CP1 and CP2 that comparator module 112 and 113 is exported, wherein has triggering
It is then denoted as 1, no triggering is then denoted as 0.As shown in Figure 4 A, in the case of there is no notch is triggered, corresponding to comparison result CP2
Register is continuously 1, so that notch state queuing register is persistently denoted as 0.Fig. 4 B then shows the case where in the presence of triggering notch,
Wherein, the minimum bit of register corresponding to comparison result CP2 occurs continuous 30, represents length as 3 triggering notch, at this time
Above-mentioned notch information can be sent to notch state queuing register, and record 1 and be used as notch indication signal.In other words, for
Each coil cycle of oscillation, processor 111 can judge continuously to go out since the minimum bit of comparator triggering state queuing register
Existing 0 quantity can be converted into notch indication signal and export to notch state queue if the quantity meets preset range
Register.By taking Fig. 4 B as an example, if comparison result CP2 is still no triggering in next coil cycle of oscillation, corresponding deposit is represented
Device data are 0, and the triggering notch that length is 4 occurs in minimum bit at this time, and it is pre- that processor 111 judges that above-mentioned triggering notch length is located at
If in range, and then recording 1 in notch state queuing register.In this instance, 1 generation that notch state queuing register is recorded
There is triggering notch in table, there is no triggering notch or triggering notch length are too long or too short for 0 representative.Week is vibrated in each coil
Interim, comparator triggering state queuing register and notch state queuing register all continuous updating numerical value, queue can mark
Triggering notch state during showing one section.
By the above-mentioned means, processor 111 can be recorded in notch state queuing register in one section of specific time in the past
Triggering notch state, to judge whether occur multiple notch indication signals during this is specific.Meanwhile processor 111 is also sentenced
Multiple notch indication signals of breaking whether be dispersed in this it is specific during (step 208).Specifically, inductive power supply of the invention
Power supply unit is a High Speed System, therefore coil cycle of oscillation is the very short time, that is to say, that the speed that queuing register updates
It spends very fast.Therefore, coil signal caused by modulated signal up and down shake should across several or dozens of coil cycle of oscillation,
It accordingly, should include multiple triggering notches generated by crest voltage decline on coil signal, and trigger notch to be distributed in
During longer (such as within dozens of coil cycle of oscillation), rather than concentrate on a time point.In this case, it handles
Device 111 need to judge whether notch indication signal is the state dispersed.
For example, processor 111 can set a first period, which is substantially equal to 16 coil cycles of oscillation
Length, correspond to continuous 16 notch state queuing registers data.Then, first period can divide into one first son
During period and one second son, for example, can will first period to being divided into two so that corresponding to notch state queue during the first son
8 data of leading portion of register correspond to 8 data of back segment of notch state queuing register during the second son.Then, it handles
Whether device 111 there is notch indication signal during can determine whether the first son, i.e. 8 data of the leading portion of notch state queuing register are
It is no to occur 1；And whether occur notch indication signal during judging the second son, i.e. 8 numbers of the back segment of notch state queuing register
According to whether occurring 1.When all occurring notch indication signal during the first son and during the second son, processor 111 be can determine whether
Notch indication signal was dispersed in first period.On the contrary, if locating when there is notch indication signal during there was only a wherein son
Reason device 111 then assert that notch indication signal is not dispersed in first period.
In another embodiment, processor 111 can also carry out the judgement of notch indication signal dispersion otherwise,
Such as the length of first period can be modified.Specifically, the length that first period length is equal to 32 coil cycles of oscillation can be set
Spend and correspond to the data of continuous 32 notch state queuing registers.In this case, processor 111 can be according to notch state
Preceding 16 data and rear 16 data judge the distribution of notch indication signal in queuing register.
Further, when processor 111 judges to occur notch indication signal in first period and notch indication signal is dispersed
When within first period, a flag tag can be dither signal (step 210) by processor 111, this mark is used to refer to coil
Signal C1 whether there is jitter feature during one section.Specifically, the record of aforementioned dither signal and triggering notch is all
Using coil cycle of oscillation as judging that period, i.e., each coil cycle of oscillation input new data.However, the label conduct of mark
Subsequent decoding foundation, the period of output signal are foundation code periods to set.In the power supply system of signal high speed oscillation,
Length of the cycle length of flag output signals commonly greater than above-mentioned coil cycle of oscillation.In one embodiment, processor 111 can
A dither signal queuing register is set, for recording the label result of mark.According to coding and decoding mode, dither signal queue is posted
Storage fixed every 0.25 millisecond (millisecond, ms) inputs a new data, during being used to refer to 0.25 millisecond of this section
Whether coil signal occurs jitter feature.That is, each of dither signal queuing register can be corresponded to 0.25 millisecond
A period of time layout, if mark when being marked as dither signal during corresponding 0.25 millisecond, this when layout in can insert
Numerical value 1；If mark during corresponding 0.25 millisecond without labeled, this when layout in can insert 0 (step of numerical value
212)。
Referring to FIG. 5, Fig. 5 is that label of the embodiment of the present invention one indicates TMR3 and corresponds to numerical value write-in dither signal queue
The schematic diagram of register.Fig. 5 shows P1~P4 during 4 sections of dither signals differentiate, wherein each section of period P1~P4 length is all
Equal to 0.25 millisecond.In this instance, mark TMR3 can be indicated by a signal, and mark TMR3 is represented when signal is low potential
It is not labeled, labeled mark TMR3 is then indicated with high potential.During P1, since notch state queuing register has occurred
All there is for 1 the case where in preceding segment data and rear segment data, therefore indicate that TMR3 is marked as dither signal (rising to high potential).
At the end of during P1, indicate that the label result of TMR3 is written into dither signal queuing register, i.e., when corresponding in layout
Numerical value 1 is inserted, meanwhile, indicate that low potential is removed and reset to the label of TMR3, with the interpretation for subsequent dither signal.Together
Sample, at the end of during P2, since mark TMR3 is marked as dither signal (rising to high potential), thus believe in shake
Numerical value 1 is inserted when the correspondence of number queuing register in layout.Then at the end of, during P3 and P4, due to above-mentioned period internal standard
Will TMR3 is not labeled as dither signal (maintaining low potential), thus the layout in the correspondence of dither signal queuing register
Interior filling numerical value 0.In this instance, during each section at the end of, indicate that the label result of TMR3 is written into dither signal queue
The dominant bit of register, when new data enter dither signal queuing register, each numerical value for originally being stored in queue
Sequentially to smaller Bit Shift, the numerical value of minimum bit then removes queue.This numerical value writing mode triggers shape with comparator is previously used for
The write-in of state queuing register and notch state queuing register is contrary, in fact, those skilled in the art can be according to being
System demand, is written register for numerical value in a manner of preferable, and above-mentioned writing mode all alternatively uses and should not be as limit.
It is worth noting that, in each section of period P1~P4, as long as notch state queue deposit occurs for any time point
All there is for 1 the case where in the preceding segment data and rear segment data of device, and mark TMR3 is collectively labeled as dither signal, terminates during the section
Indicate the label of TMR3 by until removing.In a period of after indicating that TMR3 is labeled to by before removing, regardless of whether hair
All there is for 1 the case where in the preceding segment data and rear segment data of raw notch state queuing register, and mark TMR3 maintains labeled
For the state of dither signal.
It is furthermore noted that the dither signal queue in inductive power-supply supply system of the invention, for decoding
The data period of register is 0.25 millisecond, for pre-determined and regular time, the data week encoded with receiving end
Phase is corresponding.In comparison, aforementioned comparator triggering state queuing register and notch state queuing register internal data position
The period of shifting then corresponds to coil cycle of oscillation.In general, coil cycle of oscillation correspond to payload size and coil power and
Offset, operating frequency about fall in the left and right 100 kHz (kHz), i.e. the period is about 0.01 millisecond.In this case, each
The secondary judgement that experienced about 25 dither signals when outputting data to dither signal queuing register, but this judges that number can be according to
The change of coil cycle of oscillation/operating frequency and change.
In one embodiment, during processor 111 can learn that modulated signal/data may occur according to default,
And interpretation is carried out within this period, other periods then suspend the interpretation of modulation data, to save its calculation resources.In an embodiment
In, according to the communication specification of inductive power-supply supply system, receiving end transmits the data of a byte during every 50 milliseconds, takes
With a start bit and a parity check code.In this case, during one 50 milliseconds, if processor 111 judges a byte number
When receiving according to, start bit and parity check code, data interpretation running can be suspended, during next 50 milliseconds again
Start to carry out interpretation.
In this instance, position data can be transmitted according to the mode of table one:
| Time span | Corresponding time compartment every | |
| Start bit | 2.5 millisecond | 10 |
| Place value 0 | 2 milliseconds | 8 |
| Place value 1 | 3 milliseconds | 12 |
| Parity check code 0 | 2.75 millisecond | 11 |
| Parity check code 1 | 3.25 millisecond | 13 |
Table one
It can be seen from the above, the data period of dither signal queuing register is 0.25 millisecond, i.e., layout is 0.25 when each
Millisecond, thus the time span of above-mentioned different data code can according to table one mode in correspondence with each other.In this case, one it is complete
Serial data (including a byte data, a start bit and a parity check code) shortest time length be 21.25 milliseconds (including
8 place values 0 and parity check code 0), maximum duration length be 29.25 milliseconds (including 8 place values 1 and parity check code 0,
By taking even parity check as an example).Processor 111 can according to it is each when layout in the numerical value inserted, obtain the numeric data code (step of modulation data
It is rapid 214).Specifically, processor 111 can be taken off a first time lattice of filling 1 and one second time of next filling 1
Lattice, and when calculating first time lattice and second layout interval, to judge whether the interval meets the bit length of numeric data code, Jin Ergen
Numeric data code is obtained according to gap size.For example, can determine whether that numeric data code is 0 when the gap size of layout is 8 at that time；Layout at that time
Gap size be 12 when, can determine whether numeric data code be 1.
Referring to FIG. 6, Fig. 6 be the embodiment of the present invention according to when layout interval come the signal that judges start bit and numeric data code
Figure.As shown in fig. 6, numerical value sequentially can be inserted dither signal queuing register according to aforementioned mark TMR3 by layout when each,
Number is 0~31.Firstly, processor 111 first judges whether start bit occur, i.e. whether the when layout of number 0 and number 10 is filled out
Enter numerical value 1.For example, processor 111 can be after a period of time layout inserts numerical value 1, the position of layout when judging to be spaced 10
Whether it is numerical value 1, receives start bit if so, being judged as.Start bit is in addition to can be used to judge whether numeric data code has started to pass
It send, it is also possible to the corresponding time relationship of Lai Dingyi numeric data code, that is, processor 111 can be according to the time case for receiving start bit
It sets to judge the subsequent position that may be received in numerical value 1 in dither signal queuing register.By taking Fig. 6 as an example, number 0 and number 10
The defined position of start bit of when layout, therefore, the when layout of number 18,22,26,30 is that possible be received in numerical value 1
Position, if first numeric data code is 0, the when layout of number 18 is numerical value 1；If first numeric data code is 1, number 22 when
Layout is numerical value 1.In one embodiment, the numerical value of layout is when processor 111 can be taken off each to carry out subsequent interpretation.Alternatively,
Processor 111 can also only take out may be received in numerical value 1 when layout and/or its it is adjacent when layout to carry out subsequent interpretation,
To save calculation resources, remaining when layout in insert numerical value 1 do not meet encoding mechanism, necessarily trembled as caused by noise
It is dynamic, it can be neglected.Finally, processor 111 can according to when layout interval judge parity check code, to complete one group of modulation
The judgement of data.
It is worth noting that, finding out triggering notch from comparator module, to judge the dither signal on coil, and then will tremble
The running of the relevant information write-in dither signal queuing register of dynamic signal is simultaneously non-fully ideal.For example, receiving end carries out
Modulation can generate the shake of a period of time in power supply coil, and there may be time migrations for corresponding dither signal, thus mention
It is preceding or be delayed on adjacent time lattice and occur.Alternatively, in the more good situation of signal quality, time that dither signal maintains compared with
It is long, dither signal do not have with when layout detecting cycle synchronisation in the case of, it is also possible to occur in continuous two adjacent times lattice
The case where all inserting numerical value 1.Therefore, processor 111 also judges phase in addition to the when layout for judging that numerical value 1 may be received in simultaneously
Adjacent when layout, the case where to deviate or extend in response to above-mentioned dither signal.
In one embodiment, processor 111 can may be received in numerical value 1 when layout and its adjacent time lattice in, take
The when layout for being received in numerical value 1 out is numbered, and is inserted a shaky time lattice sequence PIN, as shown in Table 2:
Table two
In table two, shaky time lattice sequence PIN_01~PIN_18 represent a sequence when layout in detect shake letter
Number and the when layout that is received in numerical value 1 is numbered, above-mentioned number is identical as the numbering of Fig. 6 and includes reneing after the figure
It stretches.Shaky time compartment then describes every two in shaky time lattice sequence PIN_01~PIN_18 respectively every GAP_01~GAP_18
Interval between adjacent time lattice, for example, GAP_01 has recorded PIN_01 and start bit terminates time (when layout number 10)
Interval, GAP_02 has recorded the interval of PIN_02 and PIN_01, and GAP_03 has recorded the interval of PIN_03 and PIN_02, and according to
This analogizes.
Then, processor 111 can be recorded according to shaky time compartment every GAP_01~GAP_18 numerical value is decoded.
As described above (referring to table one), place value 0 and place value 1 are respectively corresponding to time compartment every 8 and 12, can be decoded accordingly.Firstly,
GAP_01 is equal to 8, and representing first is 0.GAP_02 is equal to 1, indicates first and crosses adjacent time lattice, then judges GAP_
03 is equal to 7, in addition the part of first leap is it is found that GAP_02+GAP_03=8, represents second as 0.GAP_04 is equal to 1,
Indicate second also cross adjacent time lattice, then judge GAP_05 be equal to 11, in addition second leap part it is found that
GAP_04+GAP_05=12, representing third position is 1.The rest may be inferred, and the modulation data that can obtain a byte is " 00110101 ".
Then, processor 111 can determine whether parity check code, be equal to 10, GAP_16+GAP_17=since GAP_16 is equal to 1 and GAP_17
11, parity check code is represented as 0.Coding according to even parity check inspection is it is found that the data of this byte are correct, and processor 111 is in turn
This modulation data is received to carry out subsequent processing.After the reception for completing modulation data, when processor 111 can remove above-mentioned shake
Layout sequence PIN_01~PIN_18 and shaky time the compartment content documented by GAP_01~GAP_18, for subsequent
The processing of numeric data code.
It can be seen from the above, can define place value 0 and place value 1 according to the specification of coding is respectively corresponding to time compartment every 8 and 12,
And time compartment is tolerance every 7 and 11, can handle according to above-mentioned complement value mode and correctly be encoded.In another implementation
In example, it is also possible to the case where time of origin compartment is divided into 9 or 13, can also be adjusted to according to similar mode time compartment every 8 or
12, and then judge numeric data code.
Therefore, each complete serial data (including a byte data, a start bit and a parity check code), which is transmitted, includes
11 jitter features, as shown in Figure 7.Fig. 7 shows the coil signal C1 waveform for carrying partial data string, each jitter feature warp
Cross after analysis and label, record respectively at least 11 different locations when layout (and its adjacent time lattice), and then generate 10
Group time compartment every data, processor 111 can judge the numerical value of numeric data code accordingly and judge data by parity check code
Whether code is correct.
It is worth noting that, the purpose of the present invention is to provide a kind of data decodings that can be used for inductive power-supply supply device
Mode can decode the modulation data being entrained on coil signal.Those skilled in the art when can modify accordingly or
Variation, and it is without being limited thereto.For example, afore-mentioned code mode is only a kind of exemplary embodiment, and interpretation method of the invention can also
For different data code framework, coding is defined for example, by using different time spans, or can be in a complete serial data
The numeric data code of middle transmission multibyte, and it is without being limited thereto.In addition, what interpretation method of the invention can be used for being encoded by the time
Various data transmission systems are not limited to the modulation data transmission of aforementioned inductive power-supply supply device.In addition, those skilled in the art
It will be appreciated that the settings such as aforementioned various numerical value, place value, number are only that the numerous embodiments of the present invention one of are worked as, definition
Number can be all adjusted according to system requirements.
In conclusion the present invention provides a kind of decodings of signal processing circuit that can be used in inductive power-supply supply device
Method, for being decoded to the received modulation data of power supply module institute.Received modulation data/the signal of power supply module institute can be
Shake is generated in power supply coil, to generate triggering notch during the detecting of comparator module.According to the triggering recurred
Breach quantity, can produce notch indication signal, processor and during judging whether notch indication signal is dispersed in one section, with true
Protecting notch is as produced by the shake of modulated signal, and then by the label of mark come input jiffer signal, in dither signal
Queuing register it is corresponding when layout in insert numerical value 1.Then, processor can be taken off filling numerical value 1 time case set or
It numbers, and judges the place value of numeric data code by its spacing.Multi-level interpretation method through the invention, even if in power supply noise
Interference under, also can effectively take out correct modulation data.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (20)
1. a kind of interpretation method, is used for a signal processing circuit, which is received as entrained by a coil signal
One modulation data, the interpretation method include:
The coil signal is received, and judges a jitter feature of the coil signal；
When the jitter feature appears in a crest location of multiple wave crests on the coil signal, a triggering notch is obtained；
The length for judging the triggering notch, when the length of the triggering notch is located at a preset range, output one notch instruction letter
Number；
Judge whether occur multiple notch indication signals in a first period, and judges whether multiple notch indication signal disperses
Within the first period；
According to judging whether to occur multiple notch indication signal in the first period and judge that multiple notch indication signal is
One flag tag is a dither signal by the no judging result being dispersed in the first period；
Within a second phase, judge whether the mark is marked as the dither signal, and accordingly for judging the modulation number
According to it is multiple when layout in correspond to the second phase a period of time layout in insert a numerical value；And
According to it is multiple when layout in multiple numerical value for inserting, obtain a numeric data code of the modulation data.
2. interpretation method as described in claim 1, which is characterized in that receive the coil signal, and judge the coil signal
The jitter feature, and when the jitter feature appears in crest location of multiple wave crest on the coil signal, obtaining should
Trigger notch the step of include:
A peak voltage level is set, for tracking the crest voltage of multiple wave crest；
The peak voltage level is reduced into a predetermined value, differentiates voltage level to obtain one；
Compare the differentiation voltage level and the coil signal；And
When the crest voltage for detecting a wave crest in multiple wave crest is less than the differentiation voltage level, judge that a triggering occur lacks
Mouthful.
3. interpretation method as described in claim 1, which is characterized in that the first period is divided into during one first son and one
During second son, and the step for judging whether the notch indication signal was dispersed in the first period includes:
Judge whether occur the notch indication signal during first son；
Judge whether occur the notch indication signal during second son；And
When all occurring the notch indication signal during first son and during second son, the notch indication signal point is judged
It is dispersed in the first period.
4. interpretation method as described in claim 1, which is characterized in that multiple according to judging whether to occur in the first period
Notch indication signal and judge whether multiple notch indication signal is dispersed in the judging result in the first period, by the mark
Will be labeled as the dither signal the step of include:
When occurring the notch indication signal in the first period and the notch indication signal was dispersed in the first period, by this
Flag tag is the dither signal.
5. interpretation method as described in claim 1, which is characterized in that within the second phase, judge whether the mark is marked
Be denoted as the dither signal, and accordingly for judge the modulation data it is multiple when layout in correspond to the second phase should
When layout in insert the numerical value the step of include:
When the mark is marked as the dither signal, one first number of filling in layout in this for corresponding to the second phase
Value；And
When the mark is not labeled as the dither signal, one second number of filling in layout in this for corresponding to the second phase
Value.
6. interpretation method as claimed in claim 5, which is characterized in that according to it is multiple when layout in multiple number for inserting
Value, the step of obtaining the numeric data code of the modulation data include:
When multiple in layout, the first time lattice and next filling first numerical value for inserting first numerical value are taken out
One second when layout；
Calculate the first time lattice and this second when layout an interval, to judge whether the interval meets one of the numeric data code
It is long；And
According to the size at the interval, the numeric data code is obtained.
7. interpretation method as claimed in claim 6, which is characterized in that further include:
According to the interval, judge that a start bit of the modulation data and a parity check code at least one of are worked as.
8. interpretation method as claimed in claim 7, which is characterized in that further include:
During a third, the start bit of the modulation data, the numeric data code of a byte and the parity check code are obtained.
9. interpretation method as claimed in claim 8, which is characterized in that be equal to 50 milliseconds during the third, the second phase etc.
In 0.25 millisecond.
10. interpretation method as described in claim 1, which is characterized in that further include:
At the end of the second phase, if the mark is marked as the dither signal, the label of the mark is removed.
11. a kind of signal processing circuit, for receiving a modulation data as entrained by a coil signal, and to the modulation data
It is decoded, which includes:
An at least comparator module for receiving the coil signal, and judges a jitter feature of the coil signal；And
One processor is coupled to an at least comparator module, which is used to execute following steps:
When the jitter feature appears in a crest location of multiple wave crests on the coil signal, a triggering notch is obtained；
The length for judging the triggering notch, when the length of the triggering notch is located at a preset range, output one notch instruction letter
Number；
Judge whether occur multiple notch indication signals in a first period, and judges whether multiple notch indication signal disperses
Within the first period；
According to judging whether to occur multiple notch indication signal in the first period and judge that multiple notch indication signal is
One flag tag is a dither signal by the no judging result being dispersed in the first period；
Within a second phase, judge whether the mark is marked as the dither signal, and accordingly for judging the modulation number
According to it is multiple when layout in correspond to the second phase a period of time layout in insert a numerical value；And
According to it is multiple when layout in multiple numerical value for inserting, obtain a numeric data code of the modulation data.
12. signal processing circuit as claimed in claim 11, which is characterized in that an at least comparator module includes one first
Comparator module and one second comparator module, wherein the first comparator module, second comparator module and the processor
Following steps are executed, to receive the coil signal and judge the jitter feature of the coil signal, and then are gone out in the jitter feature
On the present coil signal when crest location of multiple wave crest, the triggering notch is obtained:
The processor sets a peak voltage level, so that the first comparator module is used to track the peak value electricity of multiple wave crest
Pressure；
The peak voltage level is reduced a predetermined value by the processor, differentiates voltage level to obtain one；
Second comparator module compares the differentiation voltage level and the coil signal；And
When the crest voltage that second comparator module detects a wave crest in multiple wave crest is less than the differentiation voltage level,
There is a triggering notch in processor judgement.
13. signal processing circuit as claimed in claim 11, which is characterized in that the first period was divided into for one first sub- phase
Between and one second son during, and the processor execute following steps, with judge the notch indication signal whether be dispersed in this first
During:
Judge whether occur the notch indication signal during first son；
Judge whether occur the notch indication signal during second son；And
When all occurring the notch indication signal during first son and during second son, the notch indication signal point is judged
It is dispersed in the first period.
14. signal processing circuit as claimed in claim 11, which is characterized in that the processor executes following steps, with basis
Judge whether to occur multiple notch indication signal in the first period and judges whether multiple notch indication signal is dispersed in
The flag tag is the dither signal by the judging result in the first period:
When occurring the notch indication signal in the first period and the notch indication signal was dispersed in the first period, by this
Flag tag is the dither signal.
15. signal processing circuit as claimed in claim 11, which is characterized in that the processor executes following steps, at this
In the second phase, judge whether the mark is marked as the dither signal, and accordingly for judge the modulation data this is more
The numerical value is inserted in layout when corresponding to this of the second phase when a in layout:
When the mark is marked as the dither signal, one first number of filling in layout in this for corresponding to the second phase
Value；And
When the mark is not labeled as the dither signal, one second number of filling in layout in this for corresponding to the second phase
Value.
16. signal processing circuit as claimed in claim 15, which is characterized in that the processor executes following steps, with basis
The multiple numerical value inserted in layout when multiple, obtains the numeric data code of the modulation data:
When multiple in layout, the first time lattice and next filling first numerical value for inserting first numerical value are taken out
One second when layout；
Calculate the first time lattice and this second when layout an interval, to judge whether the interval meets one of the numeric data code
It is long；And
According to the size at the interval, the numeric data code is obtained.
17. signal processing circuit as claimed in claim 16, which is characterized in that the processor also executes following steps:
According to the interval, judge that a start bit of the modulation data and a parity check code at least one of are worked as.
18. signal processing circuit as claimed in claim 17, which is characterized in that the processor also executes following steps:
During a third, the start bit of the modulation data, the numeric data code of a byte and the parity check code are obtained.
19. signal processing circuit as claimed in claim 18, which is characterized in that be equal to 50 milliseconds during the third, this second
Period is equal to 0.25 millisecond.
20. signal processing circuit as claimed in claim 11, which is characterized in that the processor also executes following steps:
At the end of the second phase, if the mark is marked as the dither signal, the label of the mark is removed.
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| TW107130369A TWI680649B (en) | 2018-08-30 | 2018-08-30 | Decoding method for signal processing circuit and signal processing circuit using the same |
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| CN112564305A (en) * | 2020-11-02 | 2021-03-26 | 富达通科技股份有限公司 | Signal analysis circuit and method |
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| TWI808562B (en) * | 2021-12-10 | 2023-07-11 | 富達通科技股份有限公司 | Decoding method for induction type power supply system and related supplying-end module |
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| CN109586734B (en) | 2022-11-25 |
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