CN109581067B - Capacitance measuring device based on FPGA high-speed receiver - Google Patents

Capacitance measuring device based on FPGA high-speed receiver Download PDF

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CN109581067B
CN109581067B CN201811334148.3A CN201811334148A CN109581067B CN 109581067 B CN109581067 B CN 109581067B CN 201811334148 A CN201811334148 A CN 201811334148A CN 109581067 B CN109581067 B CN 109581067B
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王锂
戴志坚
黄敏
刘松林
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University of Electronic Science and Technology of China
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    • G01—MEASURING; TESTING
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    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
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Abstract

The invention discloses a capacitance measuring device based on an FPGA high-speed receiver, which provides a driving signal for capacitance measurement through a signal source, adjusts the voltage amplitude of the driving signal to the required amplitude value acquired by an ADC, generates phase and amplitude changes when the driving signal is input to a measured capacitor through a standard resistor, thereby generating two paths of test signals with consistent frequency but inconsistent amplitude and phase at two ends of the standard resistor, realizes the alternative selection through a relay after the two paths of test signals are respectively isolated through an operational amplifier, then completes the acquisition and conversion of the two paths of test signals, and finally inputs the test signals to the FPGA, and calculates the capacitance value of the measured capacitor through the FPGA.

Description

Capacitance measuring device based on FPGA high-speed receiver
Technical Field
The invention belongs to the technical field of impedance measurement, and particularly relates to a capacitance measuring device based on an FPGA high-speed receiver.
Background
When we need to realize high-precision capacitance measurement, the vector current-voltage method is a good choice. Capacitance measurement is one type of impedance measurement. The vector voltage-current method comes directly from the definition of impedance. Because the sinusoidal voltage signal passing through the capacitor cannot change frequency and only changes amplitude and phase, the essence of measuring the capacitor by the vector voltage current method is to measure the phase difference of two paths of voltage after separating a real part and an imaginary part of impedance. At present, the adopted methods are a phase-sensitive detection method and a zero-crossing comparison method. The phase reference standard of the phase-sensitive detection is divided into a fixed axis method and a free axis method, the fixed axis method needs to keep the vector phase consistent, which brings difficulty in realization and has complex hardware circuit. The free axis method mainly depends on software to ensure the accuracy of an orthogonal coordinate system, eliminates in-phase errors which are difficult to overcome by a fixed axis method, improves the measurement accuracy, has a simple hardware circuit structure, and reduces the measurement speed by using a large amount of software. The invention adopts zero-crossing comparison to obtain phase information and RMS detection to obtain effective value information to calculate impedance. The basic measurement principle is shown in fig. 1.
Z in FIG. 1rIs a standard resistor, ZxTo be measured capacitance, UsAs a vector voltage signal on a reference resistor, UxThe vector voltage signal on the element under test, I, is the vector current flowing through the device. In measurementDue to passage of capacitance ZxThe sinusoidal signal of (a) produces a phase and amplitude transformation, whereby the corresponding phase and amplitude changes need to be detected by the corresponding measuring device. U shapesAnd UxThe amplitude measurement of the two ends can be acquired by a multimeter or ADC. When the capacitance measurement is realized based on the vector voltage current method, the phase measurement precision is directly related to the precision of the capacitance measurement. The phase measurement requires extremely high resolution in the time-frequency measurement and processing field, even in the generalized precise measurement field. However, the conventional high-precision phase measurement is often limited and complicated in structure. At present, phase difference measurement can be realized through an oscilloscope, a phase meter, a vector voltmeter and the like or a time-to-digital conversion device and the like, but measurement in a capacitance measurement system is obviously infeasible and has limited measurement precision by using special instruments, but the use of special devices not only increases the complexity of a circuit structure, but also limits the measurement precision and range of corresponding capacitance according to the constraint of the indexes of the devices.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a capacitance measuring device based on an FPGA high-speed receiver, which realizes high-precision capacitance measurement by a vector current-voltage method.
In order to achieve the above object, the present invention provides a capacitance measuring device based on an FPGA high-speed receiver, comprising:
the signal source is used as a drive for capacitance measurement and provides a drive signal for the capacitance measurement;
the first operational amplifier is used for improving the driving capability of the driving signal, adjusting the voltage amplitude of the driving signal to the required amplitude value acquired by the ADC, and inputting the improved driving signal into the second operational amplifier and the standard resistor respectively;
the standard resistor is used for measuring according to different parameters of the capacitor to be measured, and different standard resistors are selected, so that the driving signal generates phase and amplitude changes when being input to the capacitor to be measured through the standard resistor, and two paths of test signals with consistent frequency but inconsistent amplitude and phase are generated at two ends of the standard resistor;
the second operational amplifier and the third operational amplifier are mainly used for isolating detection errors introduced by the detector due to impedance inconsistency of two ends of the standard resistor and filtering high-frequency noise in the two paths of test signals respectively;
the relay switches the two paths of test signals to realize one of two choices;
the wave detector is used for carrying out RMS detection on the single-path test signal gated by the relay in a time-sharing manner to obtain a voltage detection value U of the two paths of test signalss、Ux；
ADC, collecting voltage detection values of two paths of test signals in a time-sharing manner to obtain a voltage effective value | Us|、|Ux|；
The comparator is used for carrying out zero-crossing comparison on the two paths of simulated test signals, converting the two paths of simulated test signals into digital signals of Lvpecl level, converting the digital signals of the Lvpecl level into digital signals of CML level, and finally inputting the digital signals into the FPGA through a GTX interface of the FPGA;
FPGA, which uses the embedded high-speed transceiver IP core to receive two paths of CML level digital signals, calculates the phase time difference between the same rising edge or falling edge of the two paths of digital signals, and finally combines the voltage effective value | Us|、|UxAnd calculating the capacitance value of the capacitor to be measured according to the resistance values of the standard resistors and storing the capacitance value in the RAM.
The invention aims to realize the following steps:
the invention relates to a capacitance measuring device based on an FPGA high-speed receiver, which provides a driving signal for capacitance measurement through a signal source, adjusts the voltage amplitude of the driving signal to the required amplitude value acquired by an ADC, generates phase and amplitude changes when the driving signal is input to a measured capacitor through a standard resistor, thereby generating two paths of test signals with consistent frequency but inconsistent amplitude and phase at two ends of the standard resistor, realizes one-out-of-two through a relay after the two paths of test signals are respectively isolated through an operational amplifier, then completes the acquisition and conversion of the two paths of test signals, and finally inputs the test signals to the FPGA, and calculates the capacitance value of the measured capacitor through the FPGA.
Meanwhile, the capacitance measuring device based on the FPGA high-speed receiver also has the following beneficial effects:
(1) the invention has simple structure and high measurement precision and wide range;
(2) in the invention, amplitude measurement is completed by combining RMS detection and ADC acquisition, and the phase difference is measured through a high-speed receiving and transmitting port of the FPGA, and the precision of the phase measurement is directly related to the speed of the high-speed receiving and transmitting port, so that the measurement precision can be greatly improved by the structural mode;
(3) the invention can reduce the difference between the devices by detecting the two voltage signals by the same detector, thereby effectively reducing the relative error of voltage measurement.
Drawings
FIG. 1 is a diagram of one embodiment of a prior art volumetric apparatus;
FIG. 2 is a structural diagram of a capacitance measuring device based on an FPGA high-speed receiver;
fig. 3 is a diagram of FPGA phase data reception.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 2 is a structural diagram of a capacitance measuring device based on an FPGA high-speed receiver according to the present invention.
In this embodiment, as shown in fig. 2, the capacitance measuring device based on the FPGA high-speed receiver of the present invention includes: the circuit comprises a signal source, a first operational amplifier, a standard resistor, a second operational amplifier, a third operational amplifier, a relay, a detector, an ADC (analog to digital converter), a comparator, an FPGA (field programmable gate array) and an RAM (random access memory).
The signal source is used as a drive for high-precision capacitance measurement, and the requirement on the signal quality is high. The output frequency of the signal source and the frequency accuracy directly affect the accuracy of the phase difference measurement. Therefore, a sine wave quartz temperature compensation oscillator is adopted in the design, the output frequency is 1MHz, and the frequency accuracy is +/-0.5 ppm.
The first operational amplifier is used for improving the driving capability of the crystal oscillator, and meanwhile, the voltage amplitude of the driving signal is adjusted to a proper amplitude value to meet the requirements of subsequent calculation and ADC acquisition, such as 1 Vpp.
The standard resistor needs to be selected according to different parameter measurement, so that the driving signal generates phase and amplitude changes when being input to the capacitor to be measured through the standard resistor, and two paths of test signals with consistent frequency but inconsistent amplitude and phase are generated at two ends of the standard resistor;
the second operational amplifier and the third operational amplifier are mainly used for isolating detection errors introduced by the detector due to impedance inconsistency of two ends of the standard resistor and filtering high-frequency noise in the two paths of test signals respectively; in this embodiment, a low bandwidth operational amplifier with high input impedance and small input capacitance is required. The low bandwidth can filter out high-frequency noise in the signal, improve the signal source quality, and the influence on the front end can be reduced by the high input impedance and the small input capacitance. The ADI operational amplifier ADA4522 was chosen to meet the hardware requirements of the design.
The relay adopts time-sharing detection and collection in the embodiment, so that the front section of the detector needs a first-stage relay to realize one of two;
the wave detector is used for carrying out RMS detection on the single-path test signal gated by the relay in a time-sharing manner to obtain a voltage detection value U of the two paths of test signalss、UxTherefore, the difference between the devices can be reduced by detecting the two voltage signals by the same detector, so that the relative error of voltage measurement is effectively reduced.
ADC, collecting voltage detection values of two paths of test signals in a time-sharing manner to obtain a voltage effective value | Us|、|Ux|；
The comparator is used for carrying out zero-crossing comparison on the two paths of simulated test signals, converting the two paths of simulated test signals into digital signals of Lvpecl level, converting the digital signals of the Lvpecl level into digital signals of CML level, and finally inputting the digital signals into the FPGA through a GTX interface of the FPGA;
FPGA, which uses the embedded high-speed transceiver IP core to receive two paths of CML level digital signalsCalculating the phase time difference between the same rising edge or falling edge of two paths of digital signals, and finally combining with the voltage effective value | Us|、|UxAnd calculating the capacitance value of the capacitor to be measured according to the resistance values of the standard resistors and storing the capacitance value in the RAM.
In the embodiment, a standard sine wave signal is used, so that a low-delay two-way comparator (ADCMP562) is used for realizing zero-crossing comparison, the sine wave signal is converted into an LVpecl level signal with the same frequency, and the LVpecl level output by the comparator is converted into a CML level through a level converter and is sent to a GTX interface of the FPGA. Meanwhile, the FPGA acquires, stores and processes the input signals, and then the phase difference time between the same rising edge or the same falling edge of the two paths of signals is obtained through calculation.
And the receiving end of each serial transceiver of the FPGA receives input data according to the set acquisition rate. As shown in fig. 3, the first and second waveforms in fig. 3 are equivalent to the two converted data signals, and the frequencies are both 1 MHz. The clock is equivalent to the data reception rate, and it can be seen from fig. 3 that the faster the acquisition rate, the higher the phase difference resolution. Simulation of data received by the GTX interface is shown in fig. 3, and the receiving end needs to implement serial-parallel conversion and FIFO buffer, so that the output data will be slower than the current actual waveform.
After the system receives an impedance measurement instruction, data received by the two GTX interfaces are stored in the RAM according to a certain number of bits (32 bit wide is adopted in design), and then the data are detected one by one. The FPGA data search processing logic is as follows:
firstly, two paths of data are compared, and when the two paths of data are the same, the next state is entered. When the data received by the first path is detected to be different from the data received by the second path, the data received by the two paths are stored as reg _ start1 and reg _ start2 respectively, counting is started at the same time, and after N different data pass, the data different from the first path are also detected by the second path, and the two data are stored as reg _ stop1 and reg _ stop2 respectively. Then, comparing reg _ start1 and reg _ start2, reg _ stop1 and reg _ stop 2bit by bit respectively, and calculating the number of bits different between them as cout1 and cout2 respectively, then:
Figure BDA0001860764170000051
wherein, Δ t is phase difference time, N is the different number of two paths of data, and F is the GTX interface acquisition rate. Then calculate the phase difference
Figure BDA0001860764170000052
Figure BDA0001860764170000053
And
Figure BDA0001860764170000054
the phases of the two paths of test signals are shown, and f is the frequency of the signal source. If the gigabit transceiver is set to a 4GHz acquisition rate, 4Gbit data can be received per second. Each bit of data corresponds to 250 ps. It follows that the higher the velocity, the smaller the phase difference resolution time, and the higher the accuracy of the measurement calculation.
Finally, according to the phase difference time delta t and the resistance value Z of the standard resistorrAnd effective value of voltage | Us|、|UxI calculating capacitance value C of measured capacitorx：
Figure BDA0001860764170000055
Wherein the content of the first and second substances,
Figure BDA0001860764170000056
as can be seen from table 1, under the same test conditions, when the measured effective value voltage is fixed, the phase difference is every 1 °, and the capacitance measured value calculated by the data in the following table will be about 2.78pF and 2.79pF respectively. If the phase resolution is insufficient, the phase difference accuracy is insufficient, and thus it is known that the influence of the phase difference accuracy on the capacitance measurement accuracy is large.
Table 1 is a statistical table of measurement calculation errors due to phase errors;
|Us| |Ux| phase difference Measured value
893mV 838mV 19° 55.33pF
893mV 838mV 20° 58.12pF
893mV 838mV 21° 60.90pF
TABLE 1
And then, the influence on the capacitance testing precision is obtained by calculating when the effective voltage values at the two ends of the tested piece have measurement errors. Under the same test conditions, when | UsWith a 10mV error in the measured value, | the calculated value of the measured capacitance will yield an error of 0.66 pF. However, considering that the same effective value detector is adopted in the subsequent hardware circuit design to detect two paths of signals respectively and the same ADC is used for sampling for multiple times, noise or external interference generated in the system will be generatedActing on two signal paths simultaneously. In which case the measurement errors that bring about the valid value will be synchronous. The following table lists the values of when | UsI and I UxThe capacitance measurement error caused by the simultaneous generation of 10mV measurement error is only 0.04pF, and the influence on the measurement accuracy can be almost ignored.
Table 2 is a statistical table of measurement calculation errors caused by effective value errors;
|Us| |Ux| phase difference Measured value
893mV 838mV 20° 58.12pF
903mV 838mV 20° 58.78pF
903mV 848mV 20° 58.08pF
TABLE 2
From the above discussion, it can be known that the high-speed acquisition capability of the FPGA high-speed receiver can greatly reduce the quantization error to improve the measurement accuracy, but there are still many factors that bring the measurement error, such as the inherent system error of the detector, the comparator, and other devices; quantization errors of ADC acquisition and GTX interface acquisition; testing a distribution parameter of the circuit; temperature drift of the standard resistor; frequency accuracy of the crystal oscillator, etc. Then the measurement system needs to be calibrated after the project design is completed, and the inherent error of the system is eliminated. In particular, when the measurement conditions are changed, the system needs to be calibrated again and then measured. The influence of the equivalent circuit on the measurement result cannot be ignored, and different equivalent circuits need to be selected according to different test conditions so as to reduce errors and improve the measurement precision. The following table is the results and accuracy of the measurements of the capacitance measurement system designed herein after calibration. The actual value is measured by an Agilent 4285A precision LCR measuring instrument, and the measuring precision can reach 0.1%.
Table 3 is a table of the measured capacitance results of the invention after calibration;
actual value (pF) Measured value (pF) Absolute error (pF) Relative error
3.147 3.162 0.015 0.48％
20.739 20.824 0.085 0.41％
51.582 51.307 0.221 0.43％
74.693 74.574 0.119 0.16％
102.371 101.927 0.444 0.43％
151.964 152.248 0.284 0.19％
TABLE 3
The above table shows that the capacitance measurement precision can reach +/-0.5%. If the impedance in different measuring range needs to be measured, the corresponding standard resistance needs to be changed to improve the measurement accuracy. The invention only adopts the corresponding measuring range capacitance measurement based on the corresponding items, and can select the corresponding standard resistor for measurement according to the circuit if the capacitance of other measuring ranges needs to be measured. The selection of the standard resistor should be calculated according to the above corresponding formula and the standard device corresponding to the proper measuring range is obtained through experiments. While the calibration of the instrument uses high precision capacitor devices.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (2)

1. A capacitance measuring device based on an FPGA high-speed receiver is characterized by comprising:
the signal source is used for driving capacitance measurement and providing a driving signal for the capacitance measurement, wherein the signal source adopts a sine wave quartz temperature compensation oscillator, the output frequency is 1MHz, and the frequency accuracy is +/-0.5 ppm;
the first operational amplifier is used for improving the driving capability of the driving signal, adjusting the voltage amplitude of the driving signal to the required amplitude value acquired by the ADC, and inputting the improved driving signal into the second operational amplifier and the standard resistor respectively;
the standard resistor is used for measuring according to different parameters of the capacitor to be measured, and different standard resistors are selected, so that the driving signal generates phase and amplitude changes when being input to the capacitor to be measured through the standard resistor, and two paths of test signals with consistent frequency but inconsistent amplitude and phase are generated at two ends of the standard resistor;
the second operational amplifier and the third operational amplifier are mainly used for isolating detection errors introduced by the detector due to impedance inconsistency of two ends of the standard resistor and filtering high-frequency noise in the two paths of test signals respectively;
the relay switches the two paths of test signals to realize one of two choices;
the wave detector is used for carrying out RMS detection on the single-path test signal gated by the relay in a time-sharing manner to obtain a voltage detection value U of the two paths of test signalss、Ux；
ADC, collecting voltage detection values of two paths of test signals in a time-sharing manner to obtain a voltage effective value | Us|、|Ux|；
The comparator is used for carrying out zero-crossing comparison on the two paths of simulated test signals, converting the two paths of simulated test signals into digital signals of Lvpecl level, converting the digital signals of the Lvpecl level into digital signals of CML level, and finally inputting the digital signals into the FPGA through a GTX interface of the FPGA;
FPGA, which uses the embedded high-speed transceiver IP core to receive two paths of CML level digital signals, calculates the phase time difference between the same rising edge or falling edge of the two paths of digital signals, and finally combines the voltage effective value | Us|、|UxCalculating the capacitance value of the capacitor to be measured according to the resistance values of the standard resistors and storing the capacitance value in the RAM;
the phase time difference calculation method comprises the following steps:
setting the bit width 32bit of the GTX interface; after the two GTX interfaces receive the two CML level digital signals, the FPGA data search processing logic is as follows:
firstly, comparing two paths of data, and entering the next state when the two paths of data are the same; when the data received by the first path is detected to be different from the data received by the second path, storing the data received by the two paths at the time as reg _ start1 and reg _ start2 respectively, starting counting at the same time, after N different data pass, the data different from the first path is also detected by the second path, storing the two data as reg _ stop1 and reg _ stop2 respectively, then comparing the reg _ start1 and reg _ start2 and reg _ stop1 and reg _ stop 2bit by bit respectively, calculating the different bits as cout1 and cout2 respectively, and then calculating the phase difference time:
Figure FDA0002923182990000021
wherein, Δ t is phase difference time, N is the different number of the two paths of CML levels, and F is the GTX interface acquisition rate.
2. The capacitance measuring device based on the FPGA high-speed receiver as claimed in claim 1, wherein the FPGA calculates the capacitance value of the measured capacitor by:
Figure FDA0002923182990000022
wherein, CxIs the capacitance value of the measured capacitor, ZrIs the resistance value of a standard resistor, X1Satisfy the requirement of
Figure FDA0002923182990000023
R1Satisfy the requirement of
Figure FDA0002923182990000024
Figure FDA0002923182990000025
And
Figure FDA0002923182990000026
is the phase of two test signals and satisfies
Figure FDA0002923182990000027
f is the frequency of the signal source, and delta t is the phase difference time of the two paths of test signals.
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