CN109543316B

CN109543316B - Method for extracting connection relation of different modules of layout

Info

Publication number: CN109543316B
Application number: CN201811428183.1A
Authority: CN
Inventors: 姚聪
Original assignee: Shanghai Anlu Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co ltd
Priority date: 2018-02-26
Filing date: 2018-11-27
Publication date: 2023-07-14
Anticipated expiration: 2038-11-27
Also published as: CN109543316A

Abstract

The invention relates to a method for extracting connection relation of different modules of a layout, which is realized by extracting connection relation information among modules by a verification tool Calibre LVS, and mainly comprises the following steps: using an integrated circuit layout editing tool to call in and open two or more modules with connection relations to be extracted, wherein a label in the module adopts a distinguishable label and ensures that the interior of the module passes through LVS; connecting wires among cells of the modules are added into an operation interface; copying the positions corresponding to connecting lines between the internal label of the module and the module; opening a calibre verification tool to perform LVS (LVS) examination; and writing a script file according to a top.LVS.report.short file generated by the checking result, and counting and extracting the connection relation among the modules. The method has high efficiency and accuracy.

Description

Method for extracting connection relation of different modules of layout

Technical Field

The invention relates to the field of integrated circuit layout design, in particular to a method for extracting connection relations of different modules of a layout.

Background

The integrated circuit board diagram is an intermediate link between the circuitry and the integrated circuit process, and is an essential important link. Through integrated circuit layout design, a three-dimensional circuit system can be changed into a two-dimensional plane figure, and then the two-dimensional plane figure is processed and reduced into a three-dimensional structure based on silicon materials.

When comparing a layout with a design drawing, a Calibre verification tool usually considers that one connecting line (net) has a unique label, and if different labels appear on the same connecting line, the Calibre verification tool considers that you link two connecting lines which should not be connected together, and the connecting lines are connected together in error, which represents that the wrong connection relationship appears in the layout when the layout verification is performed normally. In this case, when the layout is subjected to LVS (Layout Versus Schematics layout schematic diagram contrast inspection), the calibre verification tool chooses to open the inspection short, and the software reports the errors of two different labels appearing on the same line in the layout.

Calibre LVS (Layout Versus Schematics layout schematic contrast), which is a headache-comparing inspection for most layout verification engineers, must filter out useful information in complex reports to find the wrong node or device correctly. The Calibre has good performance and error checking capability when performing LVS inspection, can more accurately position errors in a layering error checking mode, and helps engineers to solve the problems fastest and most accurately through good interaction capability among a layout, a schematic diagram and a netlist.

Integrated circuit layout designs, sometimes require statistics of the connection between two modules, e.g., port a (1) of module a, to port B (1) of module B.

The current statistical method is to manually find the points actually connected together on the layout, then write the port a (1) and the port b (1) on the same line of a file, and separate the points by spaces, which represents that the two points are connected together in the layout.

When the layout format derives data, only the corresponding label position between the two modules can be derived, but the connection relation between cells (units) between the two modules in the layout cannot be displayed.

In the prior art, if the connection relation of cells between two modules in a layout is required to be known, manual operation is required for each line, and if statistics is performed line by line, the efficiency is low; if the statistics are performed line by line, an uncertainty such as a wrong order may occur. And after statistics is completed, manual inspection is needed, so that the efficiency is low and the error rate is high.

Disclosure of Invention

The invention aims to solve the problems of low efficiency and poor accuracy in extracting connection relations of different modules of a layout in the prior art, and provides a method for extracting connection relations of different modules of the layout by using the existing Calibre LVS verification tool so as to extract the connection relations among the modules of the integrated circuit layout rapidly and accurately.

In order to solve the technical problems, the embodiment of the invention discloses a method for extracting connection relations of different modules of a layout, which comprises the following steps:

the method for extracting the connection relation of different modules of the layout is realized by extracting the connection relation information between the modules by a verification tool Calibre LVS, and comprises the following steps:

step 1, using an integrated circuit layout editing tool to create and open a current operation interface module top, and calling in and opening two or more modules needing to extract connection relations, wherein the two or more modules adopt distinguishable labels and ensure that the interior of the two or more modules respectively pass through LVS;

step 2, adding connecting wires between cells of two or more than two modules into the current operation interface module top;

step 3, copying the two or more than two module internal labels to the positions corresponding to connecting lines between the module A and the module B;

step 4, opening the calibre verification tool to perform LVS detection;

and 5, writing a script file according to a top.LVS.report.short file generated by the LVS checking result, and counting and extracting the text file of the connection line relation between the modules from the script file.

The text file for counting and extracting the connection line relation between the modules comprises the following sub-steps:

step 5.1, finding the calibre verification tool output directory, and calling a top.LVS.report.short text file;

and 5.2, writing a script file, extracting lines beginning with SHORT, and arranging.

The invention uses the short file generated by the back-end physical verification tool calibre LVS to count and extract the text file correspondingly connected with different modules, and has the obvious advantages of rapidly and accurately counting and extracting the connection relation among the modules of the integrated circuit layout under the condition that the connection relation to be counted is relatively more and the wiring in the integrated circuit layout is complex.

Drawings

FIG. 1 is a schematic diagram of an interface where two or more modules requiring connection extraction are called in and opened;

FIG. 2 is a schematic diagram of an interface of a connecting line between two or more modules added to the system;

FIG. 3 is a schematic diagram of a warning message reported by the borrowed calibre verification tool of the present invention;

FIG. 4 is a schematic diagram of a text file of top.lvs.report.shorts extracted according to the present invention, wherein the text file contains text file format samples of link relationships between modules;

fig. 5 is a schematic diagram of a text file format of a connection line relationship between modules after the arrangement of the script file according to the present invention.

FIG. 6 is a flow chart of a method embodiment of the present invention

FIG. 7 is a flow chart of one embodiment of a method of writing script files in accordance with the present invention

Detailed Description

In the following description, numerous specific details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the claims of the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

as shown in fig. 1, an integrated circuit layout editing tool (such as virtuoso, broker, etc.) is used to create and open a current operation interface module top, two or more modules needing to extract connection relations are called in and opened, for example, a module a and a module B needing to extract connection relations are called in and opened, the internal label of the module a and the module B should adopt distinguishable labels, and the module a and the module B should ensure that the interior of the module a and the module B pass through LVS respectively, i.e. ensure that the internal label of the module a and the module B is correct;

as shown in fig. 2, connecting lines between the cells of the module a and the module B are added in the current operation interface module top;

then, copying the positions corresponding to connecting lines between the module A and the module B and between the module A and the module B, namely copying the labels which need to be in statistical connection relation between cells in the module A and the module B into the current operation interface module top;

then, a calibre verification tool is opened to perform LVS check, and a run short is required to be opened by LVS option (directory), so that a top.LVS.report.short file is generated, wherein the top.LVS.report.short file is a report file with different tables connected on the same line in a layout. Typically, when LVS is executed, a "top.lvs.report.short" file represents an incorrect connection in the layout, and the calibre verification tool reports some warnings, but can borrow this file when we want to know the connection between two modules. Since the internal label of the module A and the module B adopts distinguishable labels, all the connecting lines of the module A and the module B are counted, which can be used as a source for counting and extracting the connecting line relation between the module A and the module B according to the invention, as shown in figure 3.

And then, opening the verification tool Calibre LVS to generate a short file, wherein the short file comprises all connection line relation format files between the module A and the module B.

Taking the format file shown in figure 4 as an example,

the row beginning with the first row SHORT of the top lvs. Report. SHORT file indicates that a_x and b_x are two points that are connected together, the second row extracts the date, and the third row's coordinates appear in the layout, for example:

″a<3>″at(Θ.7，5Θ.415)on layer″MlTXT″SN 1

″b<3>″at(1.75，5Θ.415)on layer″MlTXT″SN 6

we use script get_short.pl (using perl language, the operation mode is perl get_short.pl script is pasted under the linux system), extract the line with SHORT as the first line, then use space as separator, store this line in the array, take out the label value output in the array.

And writing a script file to extract a row-related label value which is started by SHORT to obtain a text file of the connection line relation between the module A and the module B. As shown in FIG. 5, the connection line relationship between the module A and the module B in the layout which we want to obtain is shown.

FIG. 6 is a flow chart of an embodiment of the method of the present invention: determining a cell needing to count a connection relation, creating and opening a top_cell by using an integrated circuit layout editing tool virtuoso, calling two or more modules needing to count and extract the connection relation into the top_cell, and calling each module connecting wire needing to count and each module label into the top_cell; performing LVS verification by using a verification tool Calibre to obtain a top.LVS.report.short file; running a script file and executing a command: and finally obtaining the inter-cell line text file requiring statistics.

The script file writing process includes the following steps:

the text file of top.LVS.report.short is taken as input, and the line related element values including SHORT are extracted and sorted.

Referring to fig. 7, a flowchart of an embodiment of a method for writing a script file according to the present invention is shown, firstly, a file is opened, a top.lvs.report.short file shown in fig. 4 is read, a line beginning with a SHORT is read, for facilitating data use in the following steps, redundant blank spaces at the beginning or end of the line are removed first, then the line is divided by blank spaces and then stored in an array @ line, for example, a certain line in fig. 4 is sorted according to the above steps: "SHORT 1.A <3> -b <3> in top", then determine if the value of $line [0] in the array @ line is shrot, if so, output $line [2] and $line [4 ]. (in the array, 0 is "short",1 is "1", "2 is" a <3> ",3 is" - ", and 4 is" b <3> "; if not, the next row is read back. The script file written in this embodiment is as follows:

in this embodiment, only three wires in two modules are illustrated, and similarly, a plurality of wires between two or more modules may be illustrated. When the connection relations to be counted are relatively more and wiring in the integrated circuit layout is complex, the connection relations of different modules of the layout are counted and extracted more efficiently than manual searching, and the accuracy of counting is greatly improved.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. The method for extracting the connection relation of different modules of the layout is realized by extracting the connection relation information between the modules by a verification tool Calibre LVS, and is characterized by comprising the following steps:

step 4, opening the verification tool calibre, and performing LVS (LVS) detection;

step 5, writing script files according to the top.LVS.report.shorts file generated by the LVS checking result, counting and extracting text files of the connection line relation between the modules;

wherein, the statistics and extraction of the text file of the connection line relation between the modules comprises the following steps:

step 5.1, finding the output catalog of the verification tool calibre, and calling a top.LVS.report.short text file, wherein the top.LVS.report.short text file is a format file containing all connection line relations among modules;

and 5.2, writing a script file, extracting lines taking the SHORT as a main part, and arranging, wherein the lines taking the SHORT as a main part are extracted by using script get_short.pl, then the lines are stored in an array by taking a space as a separator, and the label value in the array is extracted and output.