CN109542811A - A kind of data communication processing method - Google Patents
A kind of data communication processing method Download PDFInfo
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- CN109542811A CN109542811A CN201811193759.0A CN201811193759A CN109542811A CN 109542811 A CN109542811 A CN 109542811A CN 201811193759 A CN201811193759 A CN 201811193759A CN 109542811 A CN109542811 A CN 109542811A
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- dma
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- buffering area
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/285—Halt processor DMA
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
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Abstract
Technical solution of the present invention includes a kind of data communication processing method, a large amount of, real-time data communication is realized based on DMA double buffering combination traps, in program of breaking in the dma, it only executes the destination address of switching DMA channel and triggers the operation of traps, carry out the carrying operation of data again in traps program, and DMA interruption just will lead to CPU interruption, traps not will lead to CPU interruption, therefore it is smaller to interrupt expense by DMA, lesser cpu resource can be occupied when CPU has a lot of work to do as far as possible, has stronger advantage in resource scarcity, the system having a lot of work to do.
Description
Technical field
The present invention relates to a kind of data communication processing methods, belong to data communication technology field.
Background technique
Now, in embedded systems, the task that MCU undertakes is more and more, and the speed of communication data interface is getting faster,
Therefore communication bring burden is also increasingly heavier.It is more to occupy processor in the case where full load communicates for the communication interface of MCU
Resource and be easy to cause communication data to lose.
The problem of although traditional DMA double-buffered data is able to solve loss of data, but when the amount of data is large, DMA
It is more that data time-consuming is carried when interruption, it will occupy the more resource of processor, make it difficult to meet that system resource is in short supply, task is numerous
More data communication requirements.
Summary of the invention
To solve the above problems, this method is based on DMA the purpose of the present invention is to provide a kind of data communication processing method
Double buffering combination traps realize a large amount of, real-time data communication, in program of breaking in the dma, only switch the destination address of DMA channel
And triggering traps, carry out the carrying of data again in traps program, and DMA interruption just will lead to CPU interruption, traps
It not will lead to CPU interruption, therefore DMA interruption expense is smaller, can occupy lesser cpu resource when CPU has a lot of work to do as far as possible,
There is stronger advantage in resource scarcity, the system having a lot of work to do.
Technical solution used by the present invention solves the problems, such as it is: a kind of data communication processing method, is based on DMA double buffering
In conjunction with traps realize MCU and peripheral hardware data communication, the MCU include serial ports, FIFO memory, dma controller, memory and
CPU；Include the following steps:
S1, serial ports DMA reception pattern is opened, configure FIFO memory and its reception threshold value is set；
S2, two receptions buffer areas, respectively first buffering area and second buffering area are opened up in memory；
S3, initialization dma controller, configure the DMA channel between peripheral hardware and memory, the source address that DMA channel is arranged is
The address data memory of peripheral hardware；
S4, the address that the destination address that DMA channel is arranged is first buffering area, and enabled DMA channel receives data；
S5, DMA interruption is generated when the received data capacity of first buffering area reaches buffer pool size threshold value, CPU is executed
The destination address of DMA channel is switched to the address of second buffering area by DMA interrupt routine, and enabled DMA channel receives data,
The first traps are triggered simultaneously；
S6, in the first traps program, the data of first buffering area are transferred to it in FIFO memory by dma controller
Backed off after random the first traps program simultaneously returns to main program, handles the data in FIFO memory by CPU；
S7, DMA interruption is generated when the received data capacity of second buffering area reaches buffer pool size threshold value, CPU is executed
The destination address of DMA channel is switched to the address of first buffering area by DMA interrupt routine, and enabled DMA channel receives data,
The second traps are triggered simultaneously；
S8, in the second traps program, the data of second buffering area are transferred to it in FIFO memory by dma controller
Backed off after random the second traps program simultaneously returns to main program, handles the data in FIFO memory by CPU；
S9, circulation execute step S5-S8, until communication terminates.
Further, the buffer pool size threshold value of the first buffering area and second buffering area is equal.
Further, the DMA interrupts the hard break generated for peripheral hardware, and first traps and the second traps are MCU
The traps that process generates.
Further, the priority that the DMA is interrupted is higher than the priority of first traps and the second traps.
Further, the FIFO memory include a fifo controller, the fifo controller have a reading pointer and
One write-in pointer, when dma controller is read out FIFO memory or when write activity, fifo controller accordingly changes this
The value of reading pointer or the write-in pointer.
Further, the fifo controller reads or is written every time the data that FIFO memory receives threshold value.
The beneficial effects of the present invention are: a kind of data communication processing method that the present invention uses, is combined based on DMA double buffering
Traps realize a large amount of, real-time data communication, in program of breaking in the dma, only execute destination address and the touching of switching DMA channel
Feel like jelly the operation of interruption, carries out the carrying operation of data again in traps program, and DMA interruption just will lead to CPU and interrupt, it is soft
Interruption not will lead to CPU interruption, therefore DMA interruption expense is smaller, can occupy lesser CPU when CPU has a lot of work to do as far as possible
Resource has stronger advantage in resource scarcity, the system having a lot of work to do.
Detailed description of the invention
Fig. 1 is the data flow block diagram of embodiment of the disclosure；
Fig. 2 is the basic steps flow chart of embodiment of the disclosure；
Fig. 3 is a kind of specific implementation block diagram of embodiment of the disclosure.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, right in the following with reference to the drawings and specific embodiments
The present invention is described in detail.Data communication processing method of the invention is suitable for the number of resource scarcity, the system having a lot of work to do
According to real-time communication.
- Fig. 3 referring to Fig.1, a kind of data communication processing method of the invention are realized based on DMA double buffering combination traps
The data communication of MCU and peripheral hardware, MCU therein include serial ports, FIFO memory, dma controller, memory and CPU, data flow
To as shown in Figure 1, passing through data bus transmission data between the memory and peripheral hardware of MCU；As shown in Fig. 2, including the following steps:
S1, serial ports DMA reception pattern is opened, configure FIFO memory and its reception threshold value is set；
S2, two receptions buffer areas, respectively first buffering area and second buffering area are opened up in memory；
S3, initialization dma controller, configure the DMA channel between peripheral hardware and memory, the source address that DMA channel is arranged is
The address data memory of peripheral hardware；
S4, the address that the destination address that DMA channel is arranged is first buffering area, and enabled DMA channel receives data；
S5, DMA interruption is generated when the received data capacity of first buffering area reaches buffer pool size threshold value, CPU is executed
The destination address of DMA channel is switched to the address of second buffering area by DMA interrupt routine, and enabled DMA channel receives data,
The first traps are triggered simultaneously；
S6, in the first traps program, the data of first buffering area are transferred to it in FIFO memory by dma controller
Backed off after random the first traps program simultaneously returns to main program, handles the data in FIFO memory by CPU；
S7, DMA interruption is generated when the received data capacity of second buffering area reaches buffer pool size threshold value, CPU is executed
The destination address of DMA channel is switched to the address of first buffering area by DMA interrupt routine, and enabled DMA channel receives data,
The second traps are triggered simultaneously；
S8, in the second traps program, the data of second buffering area are transferred to it in FIFO memory by dma controller
Backed off after random the second traps program simultaneously returns to main program, handles the data in FIFO memory by CPU；
S9, circulation execute step S5-S8, until communication terminates.
Further, the buffer pool size threshold value of first buffering area and second buffering area therein is equal.
Further, DMA therein interrupts the hard break generated for peripheral hardware, and the first traps and the second traps therein are
The traps that MCU process generates.
Further, the priority that DMA therein is interrupted is higher than the priority of the first traps and the second traps therein.
First traps and the second traps can be interrupted by other DMA and be interrupted, so that system is to receive requirement of real-time higher
It is handled in time when transactions requests.
Further, FIFO memory therein includes a fifo controller, and there is fifo controller therein a reading to refer to
Needle and a write-in pointer, when dma controller is read out FIFO memory or when write activity, fifo controller accordingly changes
Become the value of the reading pointer or the write-in pointer.
Further, fifo controller therein reads or is written every time the data that FIFO memory receives threshold value.
It not up to receives threshold value when FIFO memory receives data and does not receive new data within a preset period of time,
Fifo controller reads or is written existing total data.
As shown in figure 3, serial ports is configured to DMA reception pattern, the first buffering of setting by taking STM32F103RCT6 chip as an example
Area and second buffering area capacity threshold are 512 bytes, and DMA interrupt routine executes destination address and the triggering of switching DMA channel
Traps, traps program, which is executed, carries data from first buffering area or second buffering area to FIFO memory.
The above, only presently preferred embodiments of the present invention, the invention is not limited to above embodiment, as long as
It reaches technical effect of the invention with identical means, all should belong to protection scope of the present invention.In protection model of the invention
Its technical solution and/or embodiment can have a variety of different modifications and variations in enclosing.
Claims (6)
1. a kind of data communication processing method realizes the data communication of MCU and peripheral hardware, institute based on DMA double buffering combination traps
Stating MCU includes serial ports, FIFO memory, dma controller, memory and CPU；It is characterized by comprising the following steps:
S1, serial ports DMA reception pattern is opened, configure FIFO memory and its reception threshold value is set；
S2, two receptions buffer areas, respectively first buffering area and second buffering area are opened up in memory；
S3, initialization dma controller, configure the DMA channel between peripheral hardware and memory, and the source address that DMA channel is arranged is peripheral hardware
Address data memory；
S4, the address that the destination address that DMA channel is arranged is first buffering area, and enabled DMA channel receives data；
S5, DMA interruption is generated when the received data capacity of first buffering area reaches buffer pool size threshold value, CPU is executed in DMA
The destination address of DMA channel is switched to the address of second buffering area by disconnected program, and enabled DMA channel receives data, touches simultaneously
Send out the first traps；
S6, in the first traps program, the data of first buffering area are transferred to the retrogressing in FIFO memory by dma controller
The first traps program and main program is returned to out, passes through CPU and handle data in FIFO memory；
S7, DMA interruption is generated when the received data capacity of second buffering area reaches buffer pool size threshold value, CPU is executed in DMA
The destination address of DMA channel is switched to the address of first buffering area by disconnected program, and enabled DMA channel receives data, touches simultaneously
Send out the second traps；
S8, in the second traps program, the data of second buffering area are transferred to the retrogressing in FIFO memory by dma controller
The second traps program and main program is returned to out, passes through CPU and handle data in FIFO memory；
S9, circulation execute step S5-S8, until communication terminates.
2. data communication processing method according to claim 1, it is characterised in that: the first buffering area and the second buffering
The buffer pool size threshold value in area is equal.
3. data communication processing method according to claim 1, it is characterised in that: it is what peripheral hardware generated that the DMA, which is interrupted,
Hard break, first traps and the second traps are the traps that MCU process generates.
4. data communication processing method according to claim 1, it is characterised in that: the priority that the DMA is interrupted is higher than
The priority of first traps and the second traps.
5. data communication processing method according to claim 1, it is characterised in that: the FIFO memory includes a FIFO
Controller, the fifo controller has a reading pointer and a write-in pointer, when dma controller reads FIFO memory
It takes or when write activity, fifo controller accordingly changes the value of the reading pointer or the write-in pointer.
6. data communication processing method according to claim 5, it is characterised in that: the fifo controller read every time or
The data that FIFO memory receives threshold value are written.
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