CN109521666B - Time-to-digital converter based on delay locked loop - Google Patents
Time-to-digital converter based on delay locked loop Download PDFInfo
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Abstract
The invention relates to a time-to-digital converter based on a delay locked loop, comprising: the delay phase-locked loop is used for receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal; the integer time detection array is connected with the delay phase-locked loop and used for receiving the reference clock signal, counting the reference clock signal and outputting integer time data; and the fractional time detection array is connected with the delay phase-locked loop and is used for receiving the equal-interval same-frequency clock cluster signals, the start signals and the stop signals, quantizing the start signals and the stop signals by taking the equal-interval same-frequency clock cluster signals as a reference, and outputting fractional time data. The time-to-digital converter of the embodiment of the invention improves the accuracy and stability of measurement, improves the anti-interference capability of the TDC, simplifies the complexity of a decoding circuit and reduces the power consumption area of the TDC.
Description
Technical Field
The invention belongs to the technical field of laser radar optical signal receiver systems, and particularly relates to a time-to-digital converter based on a delay phase-locked loop.
Background
In 1960, the first laser in the world came out, and in 1961, the laser was first used in a distance measuring system. Because laser has a series of excellent optical properties such as high collimation, high monochromaticity, high power density and high coherence, various ranging technologies applied to different scenes and different ranges are continuously updated. The object shape of centimeter-order, the object distance of several kilometers to tens of kilometers from the small micron-order range close to the laser wavelength, and the distance between the earth and the satellite or even the moon can be accurately measured by using the laser. With the development of technology, the application range of the lidar is becoming wider and wider, such as navigation and collision avoidance of automobiles or spacecrafts, three-dimensional space profile scanning, weather detection, geological detection, and the like. According to the currently published reports, all main research institutions of unmanned automobiles, such as google, ford, hectometre and the like, adopt scanning laser radars to collect data; when the automobile runs at a high speed, the distance and the relative speed between the two automobiles are scanned in real time through the laser radar, barrier information is provided for a driving system, and the probability of accidents can be reduced.
The laser radar utilizes a laser transmitter to emit laser to irradiate on a detected object, laser echoes reflected by a target object are received by an avalanche photodiode working in a linear mode and converted into current signals, a front-end analog receiver linearly converts pulse current generated by the avalanche photodiode into voltage signals, and then a time-to-digital conversion circuit is utilized to obtain the flight time information of pulses. The time-of-flight information of the pulse essentially expresses the actual distance between the detected object and the lidar. The performance of the time-to-digital converter thus directly determines the accuracy of the lidar ranging.
The existing pulse wave laser radar is developed into multi-line scanning type detection or even large-area array detection from the initial single-channel detection (please refer to fig. 1), so that a time-to-digital conversion circuit also needs area array, and if a traditional time-to-digital conversion method is applied, the accuracy is poor, meanwhile, large-area integration has high power consumption, and the actual application of the vehicle-mounted laser radar is far from being met.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a time-to-digital converter based on a delay locked loop. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a time-to-digital converter based on a delay phase-locked loop, which comprises:
the delay phase-locked loop is used for receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal;
the integer time detection array is connected with the delay phase-locked loop and used for receiving the reference clock signal, counting the reference clock signal and outputting integer time data;
and the fractional time detection array is connected with the delay phase-locked loop and is used for receiving the equal-interval co-frequency clock cluster signal, the start signal and the stop signal, quantizing the start signal and the stop signal by taking the equal-interval co-frequency clock cluster signal as a reference, and outputting fractional time data.
In one embodiment of the present invention, further comprising:
the decoder is connected with the integer time detection array and the fractional time detection array and is used for decoding the address signals and outputting address codes;
and the integration compensation processing module is connected with the decoder, the integer time detection array and the fraction time detection array, and is used for performing integration compensation processing on the integer time data and the fraction time data and outputting integration compensation data according to the address code.
In one embodiment of the invention, the integer time sense array includes a counter and a register, wherein,
the counter is used for counting the reference clock signal when the start signal is received; and outputting the integer time data when the stop signal is received;
and the register is connected with the counter and is used for caching the integer time data.
In an embodiment of the present invention, the register is further connected to the decoder and the integrated compensation processing module, and is configured to output the integer time data to the integrated compensation processing module according to the address code.
In one embodiment of the invention, the fractional time detection array comprises a start fractional measurement array and a stop fractional measurement array, wherein,
the start fraction measuring array is connected with the delay phase-locked loop and the integrated compensation processing module and is used for quantizing the start signal by taking the equidistant same-frequency clock cluster signal as a reference and outputting first fraction time data;
the stop fraction measurement array is connected with the delay phase-locked loop and the integrated compensation processing module and is used for quantizing the stop signal by taking the equal-interval same-frequency clock cluster signal as a reference and outputting second fraction time data.
In an embodiment of the present invention, the stop score measurement array is further connected to the decoder, and is configured to output the second score time data to the integrated compensation processing module according to the address code.
In an embodiment of the present invention, the decoder is configured to decode the address signal when the stop signal quantization completion signal is received.
Another embodiment of the present invention provides a time-to-digital conversion method based on a delay locked loop, including the steps of:
receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal;
counting the reference clock signal and outputting integer time data;
receiving a start signal and a stop signal, quantizing the start signal and the stop signal by taking the equally spaced co-frequency clock cluster signals as a reference, and outputting fractional time data;
when the stop signal quantization completion signal is received, decoding the address signal and outputting an address code;
and performing integration compensation processing on the integer time data and the fraction time data, and outputting integration compensation data according to the address code.
In one embodiment of the present invention, counting the reference clock signal and outputting integer time data includes:
counting the reference clock signal when the start signal is received; and outputting the integer time data according to the address code when the stop signal is received.
In an embodiment of the present invention, quantizing the start signal and the stop signal with reference to the equally spaced co-frequency clock cluster signal, and outputting fractional time data, includes:
quantizing the start signal by taking the equally-spaced co-frequency clock cluster signal as a reference, and outputting first fractional time data;
and quantizing the stop signal by taking the equal-interval same-frequency clock cluster signal as a reference, and outputting the second fractional time data according to the address code.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention adopts the integer time detection array and the fractional time detection array to carry out multi-channel measurement on the multi-phase clock generated by a Delay-Locked Loop (DLL for short), greatly improves the accuracy and the stability of the measurement, improves the anti-jamming capability of a time-to-digital converter (TDC), simplifies the complexity of a decoding circuit, reduces the power consumption area of the whole TDC and has wide application prospect in the field of planar array type detection laser radar in a mode that the measurement output of the integer time detection array and the fractional time detection array is one-hot code.
2. The delay phase-locked loop has the advantages of low jitter, low phase noise, feedback stability and the like, so that the delay phase-locked loop has good robustness, stable delay can be generated, and the problem of clock delay change caused by the changes of a manufacturing process, power supply voltage and environment temperature in a TDC is solved; and the DLL can provide stable multi-phase clock signals with small area power consumption through time delay, load matching and area power consumption optimization.
Drawings
FIG. 1 is a waveform schematic diagram of a single channel detection digital clock converter provided by the prior art;
fig. 2 is a block diagram of a digital-to-time converter based on a delay locked loop according to an embodiment of the present invention;
fig. 3 is a block diagram of a delay locked loop according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a digital-to-time converter based on a delay locked loop according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 2, fig. 2 is a block diagram of a digital-to-time converter based on a delay locked loop according to an embodiment of the present invention, including: a delay locked loop 100 and a TDC measurement section, wherein,
the delay phase-locked loop 100 receives a reference clock signal, delays the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputs the reference clock signal and the equal-interval same-frequency clock cluster signal;
further, referring to fig. 3, fig. 3 is a schematic block diagram of a delay locked loop according to an embodiment of the present invention, where the delay locked loop 100 is composed of a phase detector 101, a charge pump 102, a filter 103, and a delay chain 104; the phase detector 100 receives a reference clock signal and a delayed clock signal (for example, the delayed clock signal is delayed by one clock cycle), compares the phases of the reference clock signal and the delayed clock signal, and outputs a pulse signal proportional to the phase difference between the two input signals; the charge pump 102 is a voltage controllable charge pump, the charge pump 102 receives the pulse signal, determines whether to pump the charge into the filter 103 or pump the charge out of the filter 103 according to the pulse signal generated by the phase detector 101, and converts the pulse signal into a voltage signal; the filter 103 receives the voltage signal, processes the voltage signal according to the loop requirement, generates a loop control signal to control the delay chain 104, and determines the delay period of the delay chain 104 until outputting a stable control signal; when the control signal of the filter 103 is stable, the delay chain 104 receives the stable control signal, delays the reference clock signal according to the control signal, outputs the reference clock signal to the integer time detection array, outputs a group of equally spaced same-frequency clock signals to the fractional time detection array, and simultaneously outputs the last delayed clock signal of the equally spaced same-frequency clock signals to the phase discriminator 101 for comparison with the reference clock signal; when the control signal of the filter 103 is unstable, the delay chain 104 outputs the non-equidistant co-frequency clock signal, and the non-equidistant co-frequency clock signal returns to the phase detector 101 for re-delaying.
Furthermore, the reference clock signal is a signal, the equal-interval common-frequency clock cluster signals are a group of multi-phase clock signals which are based on the reference clock signal and sequentially delay the same clock period, the frequency of the group of multi-phase clock signals is the same, and the group of multi-phase clock signals comprises at least two equal-interval common-frequency clock signals; for example, the first delayed clock signal is spaced 312ps from the reference clock signal, the second delayed clock signal is also spaced 312ps from the first delayed clock signal, the third delayed clock signal is also spaced 312ps from the second delayed clock signal, and so on.
Further, the frequency of the equal-interval same-frequency clock cluster signal is the same as that of the reference clock signal.
The delay locked loop has the advantages of low jitter, low phase noise, feedback stability and the like, so that the delay locked loop has good robustness, stable delay can be generated, and the problem of clock delay change caused by the change of a manufacturing process, power supply voltage and environment temperature in the TDC is solved; and the DLL consists of a phase discriminator, a charge pump, a filter and a controllable delay chain, and the modules can provide stable multi-phase clock signals with small area power consumption through time delay, load matching and area power consumption optimization.
The TDC measuring part is used for measuring laser time of flight (TOF) and consists of an integer time detection array 200 and a fractional time detection array 300, wherein the integer time detection array 200 is connected with the delay phase-locked loop 100 and is used for receiving a reference clock signal, counting the reference clock signal and outputting integer time data, and the output integer time data is multi-bit data and comprises at least two data; the fractional time detection array 300 is connected to the delay locked loop 100, and is configured to receive an equal-interval co-frequency clock cluster signal, a start signal, and a stop signal, quantize the start signal and the stop signal by using the equal-interval co-frequency clock cluster signal, and output fractional time data.
Further, the integer time detection array 200 includes a plurality of integer time detection points, the fractional time detection array 300 includes a plurality of fractional time detection points, and the integer time detection array 200 and the fractional time detection array 300 correspond to an array of photoelectric conversion units (avalanche diodes, APDs) in the lidar receiver, respectively.
Further, the fractional time detection array 300 is composed of an edge detection circuit and a decoding circuit of the multi-phase clock sampling signal (i.e. the equal-interval same-frequency clock cluster signal of the embodiment of the present invention).
The embodiment of the invention adopts the integer time detection array and the fractional time detection array to carry out multi-channel measurement on the multi-phase clock generated by the DLL, greatly improves the accuracy and the stability of the measurement, improves the anti-jamming capability of a time-to-digital converter (TDC), simplifies the complexity of a decoding circuit and reduces the power consumption area of the whole TDC by adopting a mode that the measurement output of the integer time detection array and the fractional time detection array is one-hot code, and has wide application prospect in the field of planar array type detection laser radars.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a digital-to-time converter based on a delay-locked loop according to an embodiment of the present invention, wherein a signal line with "/" indicates that the signal is multi-bit data, and a signal line without "/" indicates that the signal is one-bit data; the digital clock converter includes a delay locked loop 100, an integer time detection array 200, and a fractional time detection array 300.
Further, the integer time detection array 200 includes a counter 201 and a register 202,
the counter 201 receives a start signal, a stop signal and a reference clock signal, and when the counter 201 receives the start signal, the counter 201 starts counting the reference clock signal; when the counter 201 receives the stop signal, the counter 201 stops counting the reference clock signal, and outputs the counted integer time data to the register 202; specifically, because the stop signal is a group of data and the counter can only store one piece of data, when the counter receives the first stop signal, the counter records the count of the current reference clock signal to obtain the first integer time data and outputs the first integer time data to the register; when the counter receives the intermediate stop signal, recording the counting of the current reference clock signal to obtain first integer time data, and outputting the first integer time data to the register; when the counter receives the last stop signal, the counter stops counting the reference clock and outputs the last integer time data to the register.
In an embodiment of the present invention, since the DLL outputs the reference clock signal and the equal-interval same-frequency clock cluster signal at the same time after receiving the reference clock signal, the counter may receive the reference clock signal provided by the DLL or directly receive the reference clock signal that does not pass through the DLL.
The register 202 is connected to the register 201, and is used for receiving the integer time data and buffering the integer time data in the register 202.
In the embodiment of the invention, the integer time detection array adopts the multiplexing of the counter, so that the measurement accuracy can be improved, and the measurement efficiency can be improved; the register is adopted to buffer integer time data, so that the system can conveniently read and clear the data.
Further, the fractional time detection array 300 includes a start fractional time detection array 301 and a stop fractional time detection array 302, wherein,
the Start fractional time detection array 301 is connected to the delay locked loop and the integrated compensation processing module, and is configured to receive a Start signal and an equally spaced co-frequency clock cluster signal; when a Start signal is received, the Start fractional time detection array 301 determines the relative position of the Start signal and an equal-interval co-frequency clock cluster signal by taking the equal-interval co-frequency clock cluster signal as a reference, so as to quantize the Start signal, and quantize the Start signal to obtain first fractional time data, and the Start fractional time detection array 301 outputs the first fractional time data, which is multi-bit data and includes at least two pieces of data.
The Stop fraction time detection array 302 is connected with a delay phase-locked loop and an integration compensation processing module and is used for receiving Stop signals and clock cluster signals with same frequency at equal intervals; when the Stop signal is received, the Stop fractional time detection array 302 determines the relative position of the Stop signal and the equal-interval co-frequency clock cluster by taking the equal-interval co-frequency clock cluster signal as a reference, so as to quantize the Stop signal and obtain second fractional time data, the Stop fractional time detection array 302 outputs the second fractional time data, and the second fractional time data is multi-bit data and comprises at least two pieces of data.
In a specific embodiment, the system controls the laser transmitter to trigger a Start signal when emitting laser, and the Start signal starts a counter in the TDC and the Start fractional time detection array to Start timing; when the laser is reflected back through the target and passes through the photoelectric conversion module part to generate a Stop signal, the Stop signal enables the counter to Stop counting on one hand, and on the other hand, the Stop signal reaches the Stop fractional time detection array to be quantized, after the quantization is completed, the TDC stops timing and outputs a time interval quantization value between the start signal and the Stop signal.
In a specific embodiment, the start signals triggering all TDC channels to start timing are uniform, so the start signals input to the counter 201 and the start fraction measurement array 301 are the same signal; each channel in the TDC has a respective stop signal, and each stop signal corresponds to a laser signal reflected from a different location in the target, so that the signals input into the register 202 and the stop score measurement array 302 are a set of stop signals.
In one embodiment, a reset is required before each measurement of the TDC to clear previously retained measurements, and the measurements are saved after each measurement until reset.
In a specific embodiment, the TDC array adopts an integer timing multiplexing method and a fractional timing one-hot code output mode, so that the complexity of a decoding circuit is simplified, the consumption of area and power consumption is reduced, and the TDC array is particularly suitable for the application of area array detection laser radars.
Referring to fig. 4, the digital-to-time converter of the embodiment of the invention further includes: a decoder 400 and an integrated compensation processing module 500, wherein,
the decoder 400 is configured to receive an address signal, decode the address signal, and output an address code, where the address code is in the form of a unique hot code, and the address code is used to address and locate data in the register 202, the stop fractional measurement array 302, and the integer compensation processing module 500;
specifically, the decoder is configured to decode the address signal and output an address code when the stop signal quantization completion signal is received.
Specifically, after the stop signal is quantized, the system control unit receives the stop signal quantization completion signal and sends the stop signal quantization completion signal to the decoder, and the decoder receives the stop signal, decodes the stop signal and outputs an address code; in another embodiment of the invention, after the stop signal is quantized, the stop score measuring array sends the stop signal quantized signal to the decoder, and the decoder receives the stop signal, decodes the stop signal and outputs the address code.
Further, the register 202 is also connected to the decoder and the integrated compensation processing module, and when receiving the address code, the register 202 outputs the integer time data to the integrated compensation processing module 500 according to the addressing location of the address code.
Further, the stop score measurement array 302 is further connected to the decoder and the integrated compensation processing module, and when receiving the address code, the stop score measurement array 302 outputs the second measurement data read to the integrated compensation processing module 500 according to the addressing location of the address code.
In a specific embodiment, the TDC array is read by using address decoding, and the system can change the address line interface to read the measured value in each array channel, and each channel is independent and has high flexibility.
The integration compensation processing module 500 is connected to the decoder, the register 202 and the stop fractional measurement array 302, and is configured to receive the integer time data, the fractional time data (including the first fractional time data and the second fractional time data) and the address code, perform integration compensation processing on the integer time data and the fractional time data, and output integration compensation data to a subsequent device according to addressing location of the address code.
The embodiment of the invention adopts the integer time detection array and the fractional time detection array to carry out multi-channel measurement on the multi-phase clock generated by the DLL, greatly improves the accuracy and stability of the measurement, improves the anti-jamming capability of the TDC, simplifies the complexity of a decoding circuit, reduces the power consumption area of the whole TDC and has wide application prospect in the field of planar array type detection laser radars in a mode that the measurement output of the integer time detection array and the fractional time detection array is one-hot codes.
The delay locked loop has the advantages of low jitter, low phase noise, feedback stability and the like, so that the delay locked loop has good robustness, stable delay can be generated, and the problem of clock delay change caused by the change of a manufacturing process, power supply voltage and environment temperature in the TDC is solved; and the DLL can provide stable multi-phase clock signals with small area power consumption through time delay, load matching and area power consumption optimization.
The embodiment of the invention also provides a time-to-digital conversion method based on the delay locked loop, which comprises the following steps:
receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal;
counting the reference clock signal and outputting integer time data;
receiving a start signal and a stop signal, quantizing the start signal and the stop signal by taking the equally spaced co-frequency clock cluster signals as a reference, and outputting fractional time data;
when the stop signal quantization completion signal is received, decoding the address signal and outputting an address code;
and performing integration compensation processing on the integer time data and the fraction time data, and outputting integration compensation data according to the address code.
Specifically, counting the reference clock signal and outputting integer time data includes:
counting the reference clock signal when the start signal is received; when the stop signals are received, recording the current counting of the reference clock signals, and when all the stop signals are received, stopping counting of the reference clock signals and outputting the integer time data;
and outputting the integer time data according to the address code.
Specifically, quantizing the start signal and the stop signal with the equal-interval co-frequency clock cluster signal as a reference, and outputting fractional time data, including:
quantizing the start signal by taking the equally-spaced co-frequency clock cluster signal as a reference, and outputting first fractional time data;
and quantizing the stop signal by taking the equal-interval same-frequency clock cluster signal as a reference, and outputting the second fractional time data according to the address code.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A delay locked loop based time to digital converter, comprising:
the delay phase-locked loop is used for receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal;
the integer time detection array is connected with the delay phase-locked loop, comprises a plurality of integer time detection points and is used for receiving the reference clock signal, the start signal and the stop signal, counting the reference clock signal and outputting integer time data, wherein the integer time data are multi-bit data;
and the fractional time detection array is connected with the delay phase-locked loop and comprises a plurality of fractional time detection points which are used for receiving the equal-interval same-frequency clock cluster signals, the start signals and the stop signals, quantizing the start signals and the stop signals by taking the equal-interval same-frequency clock cluster signals as a reference, and outputting fractional time data which is multi-bit data.
2. The delay-locked loop based time-to-digital converter of claim 1, further comprising:
the decoder is connected with the integer time detection array and the fractional time detection array and is used for decoding the address signals and outputting address codes;
and the integration compensation processing module is connected with the decoder, the integer time detection array and the fraction time detection array, and is used for performing integration compensation processing on the integer time data and the fraction time data and outputting integration compensation data according to the address code.
3. The delay locked loop based time to digital converter of claim 2, wherein the integer time detection array comprises a counter and a register, wherein,
the counter is used for counting the reference clock signal when the start signal is received; and outputting the integer time data when the stop signal is received;
and the register is connected with the counter and is used for caching the integer time data.
4. The dll-based time-to-digital converter of claim 3, wherein the register is further coupled to the decoder and the integrated compensation processing module, and is configured to output the integer time data to the integrated compensation processing module according to the address code.
5. The delay-locked loop based time-to-digital converter of claim 2, wherein the fractional-time detection array comprises a start fractional measurement array and a stop fractional measurement array, wherein,
the start fraction measuring array is connected with the delay phase-locked loop and the integrated compensation processing module and is used for quantizing the start signal by taking the equidistant same-frequency clock cluster signal as a reference and outputting first fraction time data;
the stop fraction measurement array is connected with the delay phase-locked loop and the integrated compensation processing module and is used for quantizing the stop signal by taking the equal-interval same-frequency clock cluster signal as a reference and outputting second fraction time data.
6. The dll-based time-to-digital converter of claim 5, wherein the stop fractional measurement array is further coupled to the decoder for outputting the second fractional time data to the integrated compensation processing module according to the address code.
7. The delay-locked loop based time-to-digital converter as claimed in claim 6, wherein said decoder is adapted to decode said address signal when said stop signal quantization complete signal is received.
8. A time-to-digital conversion method based on a delay-locked loop is characterized by comprising the following steps:
receiving a reference clock signal, delaying the reference clock signal to generate an equal-interval same-frequency clock cluster signal, and outputting the reference clock signal and the equal-interval same-frequency clock cluster signal;
counting the reference clock signal and outputting integer time data, wherein the integer time data are multi-bit data;
receiving a start signal and a stop signal, quantizing the start signal and the stop signal by taking the equally spaced co-frequency clock cluster signals as a reference, and outputting fractional time data, wherein the fractional time data is multi-bit data;
when the stop signal quantization completion signal is received, decoding the address signal and outputting an address code;
and performing integration compensation processing on the integer time data and the fraction time data, and outputting integration compensation data according to the address code.
9. The delay-locked loop based time-to-digital conversion method of claim 8, wherein counting the reference clock signal and outputting integer time data comprises:
counting the reference clock signal when the start signal is received; and outputting the integer time data according to the address code when the stop signal is received.
10. The method according to claim 8, wherein the quantizing the start signal and the stop signal with reference to the equally spaced co-frequency clock cluster signals and outputting fractional time data comprises:
quantizing the start signal by taking the equally-spaced co-frequency clock cluster signal as a reference, and outputting first fractional time data;
and quantizing the stop signal by taking the equal-interval same-frequency clock cluster signal as a reference, and outputting second fractional time data according to the address code.
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| CN201811126007.2A CN109521666B (en) | 2018-09-26 | 2018-09-26 | Time-to-digital converter based on delay locked loop |
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| CN115390423B (en) * | 2022-08-22 | 2023-07-25 | 西安电子科技大学 | High-precision multi-event time-to-digital converter and conversion method |
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