CN109491158B - Display panel and display device - Google Patents
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- CN109491158B CN109491158B CN201811367434.XA CN201811367434A CN109491158B CN 109491158 B CN109491158 B CN 109491158B CN 201811367434 A CN201811367434 A CN 201811367434A CN 109491158 B CN109491158 B CN 109491158B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention relates to a display panel and a display device, comprising a gate drive circuit, wherein the gate drive circuit comprises a multi-stage gate drive unit, continuous multi-stage gate drive units are arranged in a specific time period, effective scanning signals are output by the gate drive units, the display panel also comprises a virtual gate line, the virtual gate line is arranged in front of first-row pixels in the display panel with a lower gate structure, is arranged behind last-row pixels in the display panel with an upper gate structure, and inputs a specific pulse signal on the virtual gate line when the display device with the lower gate structure is scanned reversely and the display device with the upper gate structure is scanned forwards, so that the potential difference caused by the coupling effect of all pixels on the display panel under the same gray scale is the same. The display panel and the display device solve the problem that the bright lines of the first line or the last line under the same gray scale picture are caused by the difference between the coupling effect of the first line or the last line of pixels and other pixels.
Description
Technical Field
The invention relates to the technical field of display driving, in particular to a display panel and a display device
Background
Liquid Crystal Display (LCD) devices have many advantages such as being light and thin, saving energy, and having no radiation, and thus have gradually replaced conventional Cathode Ray Tube (CRT) displays. Liquid crystal displays are widely used in high definition digital televisions, desktop computers, Personal Digital Assistants (PDAs), notebook computers, mobile phones, digital cameras, and other electronic devices.
Taking a Thin Film Transistor (TFT) liquid crystal display device as an example, it includes: the liquid crystal display panel comprises a plurality of gate lines and a plurality of data lines, two adjacent gate lines and two adjacent data lines are crossed to form a pixel unit, and each pixel unit at least comprises a thin film transistor. And the driving circuit includes: a gate drive circuit (gate drive circuit) and a source drive circuit (source drive circuit). With the pursuit of cost reduction and improvement of manufacturing processes of liquid crystal display devices by manufacturers, it has become possible to dispose a driver integrated circuit chip, which is originally disposed outside a liquid crystal display panel, on a glass substrate of the liquid crystal display panel, for example, by disposing a Gate driver integrated circuit on an Array substrate (GIA), the manufacturing process of the liquid crystal display device is simplified, the manufacturing cost is reduced, and a narrow frame of the liquid crystal display panel can be realized.
The basic working principle of the liquid crystal display panel and the driving circuit is as follows: the gate driving circuit on the array substrate sends a gate driving signal to the gate lines through the pull-up transistors electrically connected with the gate lines, the TFTs in each row are sequentially turned on, and then the source driving circuit simultaneously charges the pixel units in a whole row to the voltages required by the pixel units so as to display different gray scales. That is, the thin film transistor of the first row is first turned on by the gate driving circuit of the first row through the pull-up transistor thereof, and then the pixel cells of the first row are charged by the source driving circuit. When the pixel units in the first row are charged, the grid driving circuit turns off the thin film transistors in the row, then the grid driving circuit in the second row turns on the thin film transistors in the second row through the pull-up transistors of the grid driving circuit in the second row, and the source driving circuit charges and discharges the pixel units in the second row. In this sequence, when the pixel cells in the last row are charged, the charging is started again from the first row.
With the development of the technology and the market demand, when the array substrate produced by a plurality of manufacturers is scanned, a plurality of grid lines are simultaneously opened to charge a plurality of rows of pixel units, so that the high refresh rate of the picture can be realized, and the display quality of the picture is further improved. However, charging the pixel cells of a plurality of rows by simultaneously turning on a plurality of gate lines inevitably brings about some problems. Specifically, as shown in fig. 1 and fig. 2, fig. 1 shows a pixel unit array with an upper gate structure on an array substrate, except for a last row of pixel electrodes, pixel electrodes of other rows are all located between a gate scanning line of the current row and a gate scanning line of a next row, a first parasitic capacitance Cg _ own and a second parasitic capacitance Cg _ next are formed, and only one end of the second parasitic capacitance Cg _ next of the last row of pixels is connected to a Dummy gate line (Dummy gate), wherein a potential on the Dummy gate line is generally a voltage value Vcom of a common electrode, and the potential is constant. Similarly, in the pixel unit array of the lower gate structure, one end of the second parasitic capacitance Cg _ next of the first row of pixels is connected to the Dummy gate line (Dummy gate), so that when the display panels of the two structures respectively perform the forward scanning and the reverse scanning, the coupling of the last (first) row of pixels is different from the coupling of the other pixels, thereby causing different potentials, and therefore, the last (first) row has a bright line problem under the same gray scale. As shown in fig. 2, at point a, the nth Gate scan line Gate _ N _ 1 and the nth Gate scan line Gate _ N both output a high level, the level signal on the nth Gate scan line Gate _ N is switched from a low level to a high level, and the Pixel electrode Pixel _ N-1 in the N-1 th row is coupled by the signal on the nth Gate scan line Gate _ N, so that the potential is pulled high, but the Pixel _ N-1 in the N-1 th row is still in a charging state, and the potential change caused by the coupling is quickly leveled. At point C, the level signal on the nth Gate scan line Gate _ N is switched from high level to low level, and at this time, coupled by the nth Gate scan line Gate _ N, the potential of the Pixel electrode Pixel _ N-1 is pulled low (about several hundred millivolts), and at this time, the Gate scan line Gate _ N-1 is turned off, and the Pixel electrode Pixel _ N-1 is in a potential maintaining state, and the potential cannot be recovered. For the last row of pixels, one end of the second parasitic capacitance Cg _ next of the last row of pixels is connected to the Dummy gate line (Dummy gate), and the potential connected to the Dummy gate line is the common voltage Vcom, and is constant, so that the coupling condition between the point a and the point C does not exist, therefore, under the same gray scale condition, the final maintained potential of the last row of pixels Pixel _ N +1 is different from the final maintained potential of other pixels, thereby showing the problem of end bright line.
Disclosure of Invention
The main technical problem to be solved by the present invention is to provide a display panel and a display device, which can solve the problem that the first row or the last row of pixels of the display panel is located at a relatively special position, and in the display panel in which adjacent gate scanning lines are scanned simultaneously, the coupling effect of the first row or the last row of pixel electrodes is different from that of the other rows of pixels, so that the pixel electrode voltage is different from that of the other pixels in the same gray scale image, and macroscopically shows that the first row or the last row of pixels is bright when the gate driving circuit in the display panel with the lower gate structure is reversely scanned or the gate driving circuit in the display panel with the upper gate structure is positively scanned, thereby improving the quality of the image.
In order to achieve the above object, in a first aspect, an embodiment of the present invention provides a display panel, including an array substrate, where a scan line and a data line are arranged on the array substrate, a transistor and a pixel electrode connected to the transistor are connected to a cross portion of the array substrate, and a gate driving circuit is further arranged on the array substrate, where the gate driving circuit includes multiple stages of gate driving units, each stage of gate driving unit is configured to output a scan signal to drive each row of scan lines corresponding to each stage of the gate driving unit on the display panel, and in a specific time period, there are multiple stages of the gate driving units outputting scan signals with an active level, and the array substrate further includes:
the display device comprises a virtual grid line, wherein the virtual grid line is arranged in front of a first row of pixels in a display panel of a lower grid structure and arranged behind a last row of pixels in the display panel of an upper grid structure, and receives a pulse signal when the display device of the lower grid structure is scanned reversely or the display device of the upper grid structure is scanned forwards, and the time point of switching the pulse signal from an effective level to an ineffective level is later than the time point of switching the adjacent scanning signal from the effective level to the ineffective level in the same frame.
Further, a time point at which the pulse signal is switched from the inactive level to the active level is not earlier than a time point at which the adjacent scan signal is switched from the inactive level to the active level.
Further, when the distance between the dummy gate line and the adjacent scanning line is equal to the distance between the other two adjacent scanning lines, the pulse amplitude of the pulse signal is equal to the pulse amplitude of the adjacent scanning signal;
when the distance between the virtual gate line and the adjacent scanning line is smaller than the distance between the other two adjacent scanning lines, the pulse amplitude of the pulse signal is smaller than that of the adjacent scanning signal;
when the distance between the dummy gate line and the adjacent scanning line is greater than the distance between two other adjacent scanning lines, the pulse amplitude of the pulse signal is greater than the pulse amplitude of the adjacent scanning signal.
Further, the pulse width of the pulse signal is the same as the pulse width of the scan signal.
Further, in the same frame, a difference between a time point at which the pulse signal is switched from the active level to the inactive level and a time point at which an adjacent scanning signal is switched from the active level to the inactive level is equal to a difference between a time point at which the adjacent scanning signal is switched from the active level to the inactive level and a time point at which the scanning signal on the opposite side is switched from the active level to the inactive level.
Further, in the same frame, a difference between a time point at which the adjacent scanning signal is switched from the inactive level to the active level and a time point at which the pulse signal is switched from the inactive level to the active level is equal to a difference between a time point at which the scanning signal on the opposite side is switched from the inactive level to the active level and a time point at which the adjacent scanning signal is switched from the inactive level to the active level.
Further, in a period of time, the gate driving units of every two adjacent stages simultaneously output the scan signals.
Further, the active level is a high level.
Furthermore, the array substrate is further provided with a source electrode driving circuit which is used for outputting data signals to each row of data lines to enable the image picture to display the same gray scale.
In addition, to achieve the above object, a second aspect of embodiments of the present invention provides a display device including the display panel according to the first aspect of embodiments.
The display panel and the display device provided by the invention are characterized in that a virtual gate line is arranged and a specific pulse signal is applied, before the first row of pixels in the display panel with the lower grid structure or after the last row of pixels in the display panel with the upper grid structure, and performing reverse scanning on the display device with the lower grid structure, or when the display device with the upper grid structure is scanned in the forward direction, a specific pulse signal is input on the virtual grid line, wherein a time point when the pulse signal is switched to the low level at the high level is later than a time point when the scanning signal in the endmost row is switched to the low level at the high level, therefore, the potential difference of each pixel on the display panel caused by the coupling effect is the same under the same gray scale, and the problem that the first line or the last line of pixels of the display panel is bright due to the fact that the first line or the last line of pixels is different from other pixels under the same gray scale picture is solved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows an equivalent circuit diagram of an electrical structure of a pixel of a display panel in which an upper gate structure is present.
Fig. 2 is a voltage waveform diagram showing changes in the potential of the pixel electrode due to the coupling effect between the last row pixel and the other pixels in the equivalent circuit diagram shown in fig. 1.
Fig. 3 is a schematic structural diagram of a display panel having an upper gate structure according to a first embodiment of the present invention.
Fig. 4 shows voltage waveform diagrams of the last row pixels and other row pixels shown in fig. 3.
FIG. 5 shows a timing diagram of scanning signals and waveforms of pixel electrode potentials in each row according to a second embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a display panel having a lower gate structure according to a third embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a display panel having an upper gate structure according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be further described with reference to the accompanying drawings.
First, in the arrangement of the display panel of the present invention, "first row" and "last row" refer to the arrangement of the physical structure, and do not vary depending on the scanning method, and "row" and "column", "horizontal" and "vertical" are generally the horizontal and vertical arrangements of the display panel, respectively, but are not limited thereto, and may be reversed from the horizontal relation, and therefore, "row", "column", "horizontal" and "vertical" in the present invention are not particularly limited to the direction. And the numerical designation in each embodiment represents the same class, not just a specific part of a certain row.
First embodiment
Specifically, referring to fig. 3 and 4, as shown in fig. 3, the display panel of the present invention includes an array substrate, on which a plurality of scan lines 12 (only three gates N-1, Gate N, and Gate N +1 are shown in the figure, but the present invention is not limited thereto) are disposed and are cross-insulated, a data line 11, and a dummy Gate line 15, a switching element and a pixel electrode 13 connected to the switching element are connected to the intersection portion, a gate driving circuit is further provided on the array substrate, for supplying a scan signal to the scan lines 12, the gate driving circuit includes a plurality of stages of gate driving units 14, each stage of gate driving unit 14 includes a shift register, for outputting a scan signal to drive each row of scan lines 12 corresponding to each stage of the gate driving unit on the display panel, and at a certain period of time, there is a continuous multi-stage gate driving unit 14 outputting an effective scanning signal. Specifically, fig. 3 shows a display panel with an upper gate structure, that is, each row of scanning lines 12 is located above the corresponding row of pixel electrodes 13, in the display panel with the upper gate structure, the virtual gate line 15 is disposed behind the last row of pixels, and when a display device with the upper gate structure is scanned in the forward direction, a specific pulse signal is input to the virtual gate line 15 to solve the coupling difference of the last row of pixels, that is, the pulse signal corresponds to the scanning signal output by the gate driving unit, so that the coupling of the last row of pixels is consistent with the coupling of the pixels between the scanning signals output by the two adjacent stages of gate driving units. Specifically, the timing at which the pulse signal active level is switched to the inactive level is later than the timing at which the scanning signal active level in the adjacent scanning line (last row scanning line in the upper gate structure) is switched to the inactive level within the same frame.
Specifically, the embodiment specifically describes that each two adjacent gate driving units simultaneously output an effective gate driving signal, and the effective gate driving signal is at a high level, as shown in fig. 3 and fig. 4.
In the present embodiment, the time point at which the invalid level of the pulse signal is switched to the valid level is not earlier than the time point at which the invalid level of the scanning signal in the adjacent scanning line (last row in the top Gate structure) is switched to the valid level in the same frame, for example, in fig. 4, the time point at which the invalid level of the scanning signal on the scanning line Gate N is switched to the valid level is not earlier than the time point at which the invalid level of the scanning signal on the scanning line Gate N-1 is switched to the valid level, and accordingly, the time point at which the invalid level of the pulse signal on the Dummy Gate line (Dummy Gate)15 is switched to the valid level is not earlier than the time point at which the invalid level of the scanning signal on the scanning line Gate N +1 is switched to the valid level.
In the present embodiment, the distance between the dummy gate line 15 and the scanning line 12 of the last row is equal to the distance between the other adjacent scanning lines 12, and the pulse amplitude of the pulse signal applied to the dummy gate line 15 is equal to the pulse amplitude of the scanning signal applied to the last row. However, the object of the present invention can also be achieved by adjusting the distance and the high-low level voltage difference accordingly, that is, when the distance between the dummy gate line 15 and the scan line 12 in the last row is smaller than the distance between the other adjacent scan lines 12, the pulse amplitude of the pulse signal applied to the dummy gate line 15 is smaller than the pulse amplitude of the scan signal in the last row, and when the distance between the dummy gate line 15 and the scan line 12 in the last row is larger than the distance between the other adjacent scan lines 12, the pulse amplitude of the pulse signal applied to the dummy gate line 15 is larger than the pulse amplitude of the scan signal in the last row.
In one embodiment, the pulse width of the pulse signal is the same as the pulse widths of the other scan signals.
Preferably, in the same frame, a difference between a time point at which the pulse signal is switched from the active level to the inactive level and a time point at which an adjacent scanning signal (where the adjacent scanning signal is unique) is switched from the active level to the inactive level is equal to a difference between a time point at which the adjacent scanning signal is switched from the active level to the inactive level and a time point at which an opposite-side scanning signal (where the opposite-side scanning signal is unique) is switched from the active level to the inactive level, and a difference between a time point at which the adjacent scanning signal is switched from the inactive level to the active level and a time point at which the pulse signal is switched from the inactive level to the active level is equal to a difference between a time point at which the opposite-side scanning signal is switched from the inactive level to the active level and a time point at which the adjacent scanning signal is switched from the inactive level to the active level, for example, referring to fig. 3 to fig. 4, in the same frame, the difference between the time point at which the pulse signal on the Dummy Gate line (Dummy Gate)15 is switched from the active level to the inactive level and the time point at which the adjacent scanning signal Gate N +1 is switched from the active level to the inactive level is equal to the difference between the time point at which the adjacent scanning signal Gate N +1 is switched from the active level to the inactive level and the time point at which the scanning signal Gate N on the opposite side is switched from the active level to the inactive level (not shown), and a difference between a time point at which the adjacent scanning signal Gate N +1 is switched from the inactive level to the active level and a time point at which the pulse signal is switched from the inactive level to the active level is equal to a difference between a time point at which the opposite-side scanning signal Gate N is switched from the inactive level to the active level and a time point at which the adjacent scanning signal Gate N +1 is switched from the inactive level to the active level (not shown).
Specifically, the pulse signal applied to the dummy gate line 15 in the present embodiment is derived from a pulse signal in the system circuit of the display device, such as an STV signal in the gate driving circuit, meeting the above requirements.
As shown in fig. 4, for the coupling effect of the last row of pixels, the coupling effect at the point a1 and the point C1 is the same as the coupling effect of other adjacent rows, for example, the coupling of the last row of pixels between the scan line Gate N +1 and the Dummy Gate line (Dummy Gate) is the same as the coupling of the pixels between the scan line Gate N-1 and the scan line Gate N. Therefore, the display panel of the embodiment can well solve the problem of different pixel electrode potentials caused by different couplings, so that the display panel cannot show bright lines macroscopically.
It should be noted that the setting and connection of the clock signal and the STV signal shown in fig. 3 are only related to a specific scanning manner, that is, the scanning of each row of pixel units by multiple scanning lines is simultaneously realized, and the implementation of the function of the present invention is not affected.
The display panel according to the embodiment of the present invention is configured to provide the dummy gate line 15 and apply a specific pulse signal, specifically, after the last line of pixels is provided in the display panel having the upper gate structure, and when the display panel having the upper gate structure is scanned in the forward direction, the specific pulse signal is input to the dummy gate line 15, and when the specific pulse signal is scanned on the screen, a time point at which the pulse signal is switched from the active level to the inactive level is later than a time point at which the adjacent scanning signal is switched from the active level to the inactive level in the same frame, and a time point at which the pulse signal is switched from the inactive level to the active level is not earlier than a time point at which the adjacent scanning signal is switched from the inactive level to the active level. And correspondingly adjusting the pulse amplitude of the pulse signal through the distance between the virtual gate line and the last row of scanning lines, thereby realizing the effect that the distance and the pulse amplitude are the same as those of other scanning lines. Therefore, the invention can make the potential difference of each pixel on the display panel caused by the coupling effect under the same gray scale by arranging the virtual gate line and applying the specific pulse signal, thereby solving the problem of bright line at the last line of the display panel under the same gray scale picture because the last line of the pixels of the display panel has difference with other pixels due to the coupling effect.
Second embodiment
The specific structure of the display panel in this embodiment is substantially the same as that of the display panel in the above embodiment, and the differences are the phase setting of the CLOCK signal CLOCK of each gate driving unit and the connection manner of the STV signal, so that 4 scan lines can scan each row of pixel units at the same time. Since the circuit structure for realizing this function is not the invention point of the present invention, it is not specifically developed, and only the timing chart of the four scan lines scanned simultaneously and the coupling difference of each Pixel electrode generated thereby are analyzed, as shown in fig. 5, the waveforms of the signal of the scan line and the Pixel electrode potential of the display panel with the upper gate structure are illustrated, when the four scan lines are scanned simultaneously, the influence on each row of Pixel electrodes is also limited to the scan line adjacent to each row of Pixel electrodes, as shown in fig. 5, the potential of the Pixel electrode Pixel _ N-2 of the N-2 th row is coupled by the scan signal of the N-1 st row at the point B, the potential is pulled high, but is still in the charging state, the potential is quickly leveled, and the potential is pulled low by the coupling of the scan signal of the N-1 st row at the point D, and the N-2 nd row is in the maintaining state at this time, the potential cannot be recovered. Similarly, the potential of the Pixel electrode Pixel _ N-1 in the N-1 th row also has the corresponding E point and F point, the finally maintained potential is the same, the description of the N-th row is also omitted, but for the potential of the Pixel electrode in the last row, N +1 th row, since the potential of Dummy gate in the prior art is usually the common voltage, the voltage is constant, and the above coupling effect cannot be generated, as shown in the figure, the pull-down is not performed again after the K point, the finally maintained potential of the Pixel in the row at the same gray scale is different from the potential of the pixels in other rows, and at this time, the pulse signal applied to the Dummy gate line Dummy gate in the above embodiment according to the display panel being the upper gate or the lower gate structure generates the same coupling effect as that generated by the other pixels, so as to achieve the object of the present invention. The present invention is not limited to a display panel in which only two adjacent scan lines are scanned simultaneously.
Third embodiment
As shown in fig. 6, the display panel of the present invention includes an array substrate, wherein cross-insulated scan lines 12 (only three gates N-1, Gate N, and Gate N +1 are shown in the figure, but the present invention is not limited thereto), data lines 11, and dummy Gate lines 15 are disposed on the array substrate, a switching element and a pixel electrode 13 connected to the switching element are connected to a cross portion, a Gate driving circuit is further disposed on the array substrate, and is configured to provide a scan signal to the scan lines 12, the Gate driving circuit includes a multi-stage Gate driving unit 14, each stage of the Gate driving unit 14 includes a shift register, and is configured to output a scan signal to drive each row of the scan lines 12 corresponding to each stage of the Gate driving unit on the display panel, and in a specific time period, there is a continuous multi-stage Gate driving unit 14 that outputs an effective scan signal.
Specifically, fig. 6 shows a display panel of a bottom gate structure, that is, each row of scanning lines 12 is located below the pixel electrodes 13 of the row, in the display panel of the bottom gate structure, the dummy gate line 15 is provided before the pixels of the first row, and when a display device of the bottom gate structure is scanned in the reverse direction, a specific pulse signal is input to the dummy gate line 15, and the time point at which the active level of the pulse signal is switched to the inactive level in the same frame is later than the time point at which the scanning signal in the adjacent scanning line (the first row in the bottom gate structure) is switched from the active level to the inactive level.
Specifically, the present embodiment specifically explains the case where each two adjacent gate driving units simultaneously output the effective gate driving signal, and the effective gate driving signal is at a high level
In the present embodiment, the time point at which the pulse signal inactive level is switched to the active level is not earlier than the time point at which the scan signal inactive level in the adjacent scan line (first row in the bottom gate structure) is switched to the active level in the same frame screen.
In the present embodiment, the distance between the dummy gate line 15 and the scan line 12 of the first row (i.e., the N +1 th row in fig. 6) is equal to the distance between the other adjacent scan lines 12, and the pulse amplitude of the pulse signal applied to the dummy gate line 15 is equal to the pulse amplitude of the scan signal applied to the last row. However, the object of the present invention can also be achieved by adjusting the distance and the high-low level voltage difference accordingly, that is, when the distance between the virtual gate line 15 and the scan line 12 in the first row is smaller than the distance between the other adjacent scan lines 12, the pulse amplitude of the pulse signal applied to the virtual gate line 15 is smaller than the pulse amplitude of the scan signal in the first row, and when the distance between the virtual gate line 15 and the scan line 12 in the first row is larger than the distance between the other adjacent scan lines 12, the pulse amplitude of the pulse signal applied to the virtual gate line 15 is larger than the pulse amplitude of the scan signal in the first row.
In one embodiment, the pulse width of the pulse signal is the same as the pulse widths of the other scan signals.
Preferably, in the same frame, a difference between a time point at which the pulse signal is switched from the active level to the inactive level and a time point at which the adjacent scanning signal is switched from the active level to the inactive level is equal to a difference between a time point at which the adjacent scanning signal is switched from the active level to the inactive level and a time point at which the scanning signal on the opposite side is switched from the active level to the inactive level, and a difference between a time point at which the adjacent scanning signal is switched from the inactive level to the active level and a time point at which the pulse signal is switched from the inactive level to the active level is equal to a difference between a time point at which the scanning signal on the opposite side is switched from the inactive level to the active level and a time point at which the adjacent scanning signal is switched from the inactive level to the active level.
Specifically, the pulse signal applied to the dummy gate line 15 in the present embodiment is derived from a pulse signal in the system circuit of the display device, which meets the above requirements.
It should be noted that the setting and connection of the clock signal and the STV signal shown in fig. 6 are only related to a specific scanning manner, that is, scanning of each row of pixel units by multiple scanning lines is simultaneously achieved, which does not affect the implementation of the function of the present invention, and the application scenario mentioned in the second embodiment is also applicable to the lower gate structure in the lower gate structure, which is the same as the upper gate structure, and is not described herein again.
The display panel provided by the embodiment of the invention is provided with the dummy gate line 15 and applies a specific pulse signal, specifically, before the first row of pixels in the display panel with the lower gate structure, and, when a display panel of a lower gate structure is reversely scanned, a specific pulse signal is inputted on the dummy gate line 15, the time point of the pulse signal switching from the active level to the inactive level is later than the time point of the scanning signal switching from the active level to the inactive level of the first row in the same frame when the frame is scanned, the time point of the pulse signal switching from the inactive level to the active level is not earlier than the time point of the first line scanning signal switching from the inactive level to the active level, and correspondingly adjusting the pulse amplitude of the pulse signal through the distance between the virtual gate line and the first row of scanning lines, thereby realizing the effect that the distance and the pulse amplitude are the same as those of other scanning lines. Therefore, the invention can make the electric potential difference of each pixel on the display panel caused by the coupling effect under the same gray scale by arranging the virtual gate line and applying the specific pulse signal, thereby solving the problem that the first line of pixels of the display panel is bright due to the difference of the coupling effect on the first line of pixels and other pixels under the same gray scale picture.
Fourth embodiment
As shown in fig. 7, the display panel in this embodiment is substantially the same as the display panel in the first embodiment, except that the pulse signal applied to the dummy gate line is from the additional signal generating device 16, so that the coupling of the last row of pixels is the same as the coupling of the pixels between the scan signals of the two adjacent stages of gate driving units, rather than the pulse signal existing in the first embodiment, that is, for the foregoing embodiment, the pulse signal can be generated by the additional signal generating device and applied to the dummy gate line, wherein for the specific panel structure and working principle, please refer to the description of the display panel above, which is not repeated herein.
Fifth embodiment
The 5 th embodiment of the present invention provides a display device, which includes a display panel, wherein the structure and the working principle of the display panel are described with reference to the display panel in the above embodiments, which are not repeated herein.
The display device provided by the invention is provided with a virtual gate line and applies a specific pulse signal, in particular, when the display panel of a lower gate structure is arranged in front of the first row of pixels, the display panel of an upper gate structure is arranged in back of the last row of pixels, the display device of the lower gate structure is scanned in reverse direction, and the display device of the upper gate structure is scanned in forward direction, the specific pulse signal is input on the virtual gate line, when the specific pulse signal is scanned in a picture, the time point of the low level switching high level of the pulse signal is not earlier than the time point of the low level switching high level of the scanning signal in the line at the most end part (namely the first row or the last row), and the time point of the high level switching low level of the pulse signal is later than the time point of the high level switching low level of the scanning signal in the line at the most end part (namely the first row or the last row), and correspondingly adjusting the pulse amplitude of the pulse signal through the distance between the virtual gate line and the first row or the last row of scanning lines, thereby realizing the effect that the distance and the pulse amplitude are the same as those of other scanning lines. The potential difference of each pixel on the display panel caused by the coupling effect under the same gray scale can be the same by arranging the virtual gate line and applying the specific pulse signal, so that the problem of bright lines of the first line or the last line of the pixels of the display panel under the same gray scale picture due to the difference of the coupling effect on the first line or the last line of the pixels and other pixels is solved, and further other adverse effects such as increasing a frame, reducing an effective display area and the like caused by the bright lines are avoided.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (9)
1. A display panel comprises an array substrate, wherein the array substrate is provided with scanning lines and data lines which are insulated in a crossed mode, the crossed parts of the array substrate are connected with transistors and pixel electrodes connected with the transistors, the array substrate is further provided with a grid driving circuit, the grid driving circuit comprises a plurality of stages of grid driving units, each stage of grid driving unit is used for outputting scanning signals to drive each stage of scanning lines corresponding to the grid driving unit on the display panel, and continuous multistage scanning signals of effective levels output by the grid driving unit exist in a certain time period, and the array substrate is characterized by further comprising:
the display device comprises a virtual gate line, a virtual gate line and a control circuit, wherein the virtual gate line is arranged in front of a first row of pixels in a display panel of a lower gate structure, is arranged behind a last row of pixels in the display panel of an upper gate structure, and receives a pulse signal when the display device of the lower gate structure is scanned reversely or the display device of the upper gate structure is scanned forwards, and the time point of switching the pulse signal from an effective level to an ineffective level is later than the time point of switching an adjacent scanning signal from an effective level to an ineffective level in the same frame;
wherein when the distance between the dummy gate line and the adjacent scanning line is equal to the distance between two other adjacent scanning lines, the pulse amplitude of the pulse signal is equal to the pulse amplitude of the adjacent scanning signal;
when the distance between the virtual gate line and the adjacent scanning line is smaller than the distance between the other two adjacent scanning lines, the pulse amplitude of the pulse signal is smaller than that of the adjacent scanning signal;
when the distance between the dummy gate line and the adjacent scanning line is greater than the distance between two other adjacent scanning lines, the pulse amplitude of the pulse signal is greater than the pulse amplitude of the adjacent scanning signal.
2. The display panel according to claim 1, wherein a point of time at which the pulse signal is switched from the inactive level to the active level is not earlier than a point of time at which the adjacent scan signal is switched from the inactive level to the active level.
3. The display panel according to claim 1, wherein a pulse width of the pulse signal is the same as a pulse width of the scan signal.
4. The display panel according to claim 1, 2 or 3, wherein a difference between a time point at which the pulse signal is switched from an active level to an inactive level and a time point at which the adjacent scanning signal is switched from an active level to an inactive level is equal to a difference between a time point at which the adjacent scanning signal is switched from an active level to an inactive level and a time point at which the scanning signal on the opposite side is switched from an active level to an inactive level in the same frame.
5. The display panel according to claim 1, 2 or 3, wherein a difference between a time point at which the adjacent scanning signal is switched from the inactive level to the active level and a time point at which the pulse signal is switched from the inactive level to the active level is equal to a difference between a time point at which the scanning signal on the opposite side is switched from the inactive level to the active level and a time point at which the adjacent scanning signal is switched from the inactive level to the active level in the same frame.
6. The display panel according to claim 1, wherein the gate driving units of every two adjacent stages simultaneously output the active scan signals for a period of time.
7. The display panel according to claim 1, wherein the active level is a high level.
8. The display panel of claim 1, wherein the array substrate is further provided with a source driving circuit for outputting data signals to each row of data lines to display the same gray scale on the image frame.
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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| US10854684B2 (en) | 2016-02-18 | 2020-12-01 | Boe Technology Group Co., Ltd. | Pixel arrangement structure and driving method thereof, display substrate and display device |
| US11448807B2 (en) | 2016-02-18 | 2022-09-20 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, fine metal mask set and manufacturing method thereof |
| US11747531B2 (en) | 2016-02-18 | 2023-09-05 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, fine metal mask set and manufacturing method thereof |
| US11233096B2 (en) | 2016-02-18 | 2022-01-25 | Boe Technology Group Co., Ltd. | Pixel arrangement structure and driving method thereof, display substrate and display device |
| CN110137213A (en) | 2018-02-09 | 2019-08-16 | 京东方科技集团股份有限公司 | Pixel arrangement structure and its display methods, display base plate |
| CN114994973B (en) | 2018-02-09 | 2023-04-28 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN112186022A (en) | 2018-02-09 | 2021-01-05 | 京东方科技集团股份有限公司 | Pixel arrangement structure, display substrate and display device |
| US11574960B2 (en) | 2018-02-09 | 2023-02-07 | Boe Technology Group Co., Ltd. | Pixel arrangement structure, display substrate, display device and mask plate group |
| EP4006983A4 (en) | 2019-07-31 | 2022-11-16 | BOE Technology Group Co., Ltd. | Display substrate and preparation method therefor, display panel, and display apparatus |
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