CN109474551B - DC offset calibration circuit - Google Patents
DC offset calibration circuit Download PDFInfo
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- CN109474551B CN109474551B CN201710801003.9A CN201710801003A CN109474551B CN 109474551 B CN109474551 B CN 109474551B CN 201710801003 A CN201710801003 A CN 201710801003A CN 109474551 B CN109474551 B CN 109474551B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
- H04B2001/305—Circuits for homodyne or synchrodyne receivers using dc offset compensation techniques
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
A DC offset calibration circuit includes: an analog DC offset cancellation unit, which is used for receiving the output signal of the first amplifier through the integrator and outputting the feedback signal to the first amplifier, so that the first amplifier outputs the amplified signal with fixed DC offset; and a digital DC offset eliminating unit, which is used for receiving the amplified signal with fixed DC offset through the second amplifier and outputting the amplified signal to the comparator, and is used for judging the DC offset of the output signal of the second amplifier and outputting the amplified signal to the digital circuit, the digital circuit is used for generating a logic result according to the DC offset and outputting the logic result to the digital-to-analog converter, and the digital-to-analog converter outputs a corresponding second feedback signal to the second amplifier according to the logic result so as to correct the DC offset of the second amplifier.
Description
Technical Field
The present invention relates to a calibration circuit, and more particularly, to a dc offset calibration circuit using common analog and digital dc offset calibration methods.
Background
Since most of the general wireless communication systems are direct conversion (direct conversion) transceiver architectures, a problem of direct current offset (DC offset) often occurs. The dc offset is mainly generated by mixing of the oscillating signal during the frequency conversion process, and the dc offset may distort or saturate the signal of the post-stage circuit (such as filter/amplifier), thereby reducing the overall performance of the wireless communication system.
The traditional method mostly adopts a pure digital mode to eliminate the DC offset of a filter or an amplifier. For example, the dc offset is digitally removed by using a comparator (comparator) to determine the magnitude of the dc offset, and using a digital circuit to adjust the dc offset of the amplifier after determining the result. The advantage of digital cancellation of dc offset is fast processing, but the disadvantage is that the dc offset of the output changes when the temperature changes or the input signal changes, so the dc offset of the amplifier needs to be adjusted constantly as the received signal changes. Therefore, the conventional digital dc offset calibration circuit still has its disadvantages.
Disclosure of Invention
The invention discloses a DC offset calibration circuit, which is used for calibrating DC offset (DC offset) in a multi-level mode and comprises the following components: an analog DC offset cancellation unit, comprising an analog integrator and a first amplifier, wherein the first amplifier is used for receiving an analog signal with a DC offset, and the analog integrator is used for receiving an output signal of the first amplifier and outputting a first feedback signal to the first amplifier, so that the first amplifier outputs an amplified signal with a fixed DC offset; and a digital DC offset cancellation unit connected to the analog DC offset cancellation unit for receiving the amplified signal with fixed DC offset output from the analog DC offset cancellation unit, wherein the digital DC offset cancellation unit comprises a comparator, a digital circuit, a digital-to-analog converter and a second amplifier, the second amplifier is used for receiving the amplified signal with fixed DC offset, the comparator receives an output signal of the second amplifier, and is used for judging the DC offset of the output signal and outputting the DC offset to the digital circuit, the digital circuit is used for generating a logic result according to the DC offset and outputting the logic result to the digital-to-analog converter, and the digital-to-analog converter is used for outputting a corresponding second feedback signal to the second amplifier according to the logic result, for correcting the DC offset of the second amplifier.
The invention also discloses a wireless signal transceiver, comprising: a signal processing unit, which comprises a mixer for mixing a received high-frequency signal with local oscillation frequency and converting the mixed signal into an intermediate-frequency signal; and a DC offset calibration circuit for calibrating DC offset (DC offset) of the IF signal in a multi-level manner, comprising: an analog DC offset cancellation unit, comprising an analog integrator and a first amplifier, wherein the first amplifier is used for receiving an analog signal with a DC offset, and the analog integrator is used for receiving an output signal of the first amplifier and outputting a first feedback signal to the first amplifier, so that the first amplifier outputs an amplified signal with a fixed DC offset; and a digital DC offset cancellation unit connected to the analog DC offset cancellation unit for receiving the amplified signal with fixed DC offset output from the analog DC offset cancellation unit, wherein the digital DC offset cancellation unit comprises a comparator, a digital circuit, a digital-to-analog converter and a second amplifier, the second amplifier is used for receiving the amplified signal with fixed DC offset, the comparator receives an output signal of the second amplifier, and is used for judging the DC offset of the output signal and outputting the DC offset to the digital circuit, the digital circuit is used for generating a logic result according to the DC offset and outputting the logic result to the digital-to-analog converter, and the digital-to-analog converter is used for outputting a corresponding second feedback signal to the second amplifier according to the logic result, for correcting the DC offset of the second amplifier.
Drawings
FIG. 1 is a block diagram of a transceiver according to an embodiment of the present invention
FIG. 2 is a diagram of a DC offset calibration circuit according to an embodiment of the present invention
Description of reference numerals:
RF high frequency signal
LO local oscillator frequency
IN amplified signal
Output signal
IF intermediate frequency signal
CLK clock signal
FB feedback signal
10 Signal processing unit
20 DC offset calibration circuit
20A analog DC offset cancellation unit
20B digital DC offset cancellation unit
30 signal output unit
100 transceiver
102 mixer
200 filter or amplifier
202 transductive amplifier
204 integrator
206 comparator
208 digital circuit
210 static current generator
Detailed Description
Referring to fig. 1, fig. 1 is a block diagram of a transceiver in a wireless communication device according to an embodiment of the invention. The DC offset calibration circuit provided by the invention can be applied to a transceiver and is used for correcting the DC offset of an internal circuit of the transceiver so as to enable the transceiver to output a real signal. As shown in fig. 1, the transceiver 100 includes a signal processing unit 10, a dc offset calibration circuit 20 (including an analog dc offset cancellation unit 20A and a digital dc offset cancellation unit 20B), and a signal output unit 30. It is noted that the dc offset calibration circuit 20 of the present invention eliminates dc offset of the internal circuits of the transceiver 100 through multi-level dc offset calibration. Briefly, the analog dc offset cancellation unit 20A of the dc offset calibration circuit 20 is used to provide an analog signal with a fixed dc offset to the digital dc offset cancellation unit 20B. Since the signal received by the digital dc offset cancellation unit 20B is a signal with a fixed dc offset, the digital dc offset cancellation unit 20B only needs to correct the dc offset once, and can output a real signal to a subsequent circuit (not shown in the figure), and the signal received does not need to be corrected continuously because the signal has different dc offsets (such as a temperature-affected signal change).
In detail, referring to fig. 2, fig. 2 is a schematic diagram of a dc offset calibration circuit 20 according to an embodiment of the invention. The high frequency signal RF is mixed with the local oscillator frequency LO by the mixer 102, and then converted into an intermediate frequency signal IF (this process can be executed by the signal processing unit 10 shown in fig. 1), and has a Dc offset (Dc offset). The dc offset will be amplified along with the signal amplified by the amplifier, which will saturate the output of the amplifier or affect the processing distortion of the filter. Therefore, the present invention first performs dc offset correction of the intermediate frequency signal IF in the first stage by the analog dc offset cancellation unit 20A. The analog dc offset cancellation unit 20A includes a transconductance amplifier 202 and an analog integrator 204. IN order to eliminate the dc offset of the output signal of the transconductance amplifier 202, the analog integrator 204 is disposed between the output end and the input end of the transconductance amplifier 202, and the input end of the analog integrator 204 is connected to the output end of the transconductance amplifier 202 for receiving the output signal of the transconductance amplifier 202 and extracting the dc offset of the output signal, and then pulling the output signal back to the input end of the transconductance amplifier 202 to cancel the intermediate frequency signal IF, so as to obtain the amplified signal IN with a fixed dc offset. In brief, when the intermediate frequency signal IF with dc offset is input to the transconductance amplifier 202, the analog integrator 204 outputs the feedback signal FB to the input terminal of the transconductance amplifier 202 according to the output signal of the transconductance amplifier 202, so as to eliminate the dc offset output by the transconductance amplifier 202.
As shown IN fig. 2, the amplified signal IN is then input to a digital dc offset cancellation unit 20B. The present invention performs the second stage dc offset correction by the digital dc offset cancellation unit 20B. The digital dc offset cancellation unit 20B includes a comparator 206(comparator), a digital circuit 208, a static current generator 210, and a filter/amplifier 200. The comparator 206 is used for comparing the output signal of the filter/amplifier 200 with a reference level to output the comparison result. The digital circuit 208 performs binary search operation (binary search) according to the comparison result of the comparator 206, and sets each bit value from the Most Significant Bit (MSB) to the Least Significant Bit (LSB) in sequence, such as setting to 0 or 1. Then, the quiescent current generator 210 adjusts the output current according to the bit value set by the digital circuit 208, so as to eliminate the dc offset 208 output by the filter/amplifier 200. It is noted that the digital circuit can be implemented by linear search or binary search algorithms, which are well known in the art and will not be described herein.
As can be seen from the above description, the main concept of the present invention is to accumulate the dc offset information about the transconductance amplifier 202 through the analog integrator 204, and pull the output of the transconductance amplifier 202 back to the input to compare with the mixer 102 to remove the dc offset accumulated before the transconductance amplifier 202 (i.e. the dc offset correction of the first stage). Thus, the dc offset seen at the receiving end of the filter/amplifier 200 is a fixed value and does not change (e.g. temperature or caused change) with the previous stage signal, which is equivalent to locking the dc offset of the previous stage. The dc offset of the filter/amplifier 200 is then removed (i.e., second stage dc offset correction) by means of the comparator 206, the digital circuit 208 and the quiescent current generator 210.
In summary, the present invention provides a common analog and digital method for correcting the dc offset. The DC offset calibration circuit of the invention can keep the characteristics of high digital mode calibration speed and high analog mode calibration stability when performing DC offset calibration, therefore, the DC offset calibration circuit of the invention can not be performed when receiving and transmitting signals, and the DC offset of the output end of the amplifier is changed all the time because the gain of the high-frequency signal end is changed all the time, and the whole system needs to be calibrated at any time.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (8)
1. A DC offset calibration circuit for calibrating DC offset in a multi-level manner, comprising:
an analog DC offset cancellation unit, comprising an analog integrator and a first amplifier, wherein the first amplifier is used for receiving an analog signal with a DC offset, and the analog integrator is used for receiving an output signal of the first amplifier and outputting a first feedback signal to the first amplifier, so that the first amplifier outputs an amplified signal with a fixed DC offset; and
a digital DC offset cancellation unit connected to the analog DC offset cancellation unit for receiving the amplified signal with a fixed DC offset output from the analog DC offset cancellation unit, the digital DC offset cancellation unit includes a comparator, a digital circuit, a digital-to-analog converter and a second amplifier, wherein the second amplifier is used for receiving the amplified signal with fixed DC offset, the comparator is used for receiving an output signal of the second amplifier, judging the DC offset of the output signal and outputting the output signal to the digital circuit, the digital circuit is used for generating a logic result according to the DC offset and outputting the logic result to the digital-to-analog converter, and the digital-to-analog converter is used for outputting a corresponding second feedback signal to the second amplifier according to the logic result so as to correct the direct current offset of the second amplifier.
2. The dc offset calibration circuit of claim 1, wherein the first amplifier is a transconductance amplifier.
3. The dc offset calibration circuit of claim 1, wherein the digital-to-analog converter is a static current generator.
4. The dc offset calibration circuit of claim 1, wherein the analog signal is an intermediate frequency signal obtained by mixing a high frequency signal.
5. A wireless signal transceiver, comprising:
a signal processing unit for sending out an analog signal; and
a DC offset calibration circuit for calibrating DC offset of the analog signal in a multi-level manner, comprising:
an analog DC offset cancellation unit, comprising an analog integrator and a first amplifier, wherein the first amplifier is used for receiving the analog signal with DC offset, and the analog integrator is used for receiving an output signal of the first amplifier and outputting a first feedback signal to the first amplifier, so that the first amplifier outputs an amplified signal with fixed DC offset; and
a digital DC offset cancellation unit connected to the analog DC offset cancellation unit for receiving the amplified signal with a fixed DC offset output from the analog DC offset cancellation unit, the digital DC offset cancellation unit includes a comparator, a digital circuit, a digital-to-analog converter and a second amplifier, wherein the second amplifier is used for receiving the amplified signal with fixed DC offset, the comparator is used for receiving an output signal of the second amplifier, judging the DC offset of the output signal and outputting the output signal to the digital circuit, the digital circuit is used for generating a logic result according to the DC offset and outputting the logic result to the digital-to-analog converter, and the digital-to-analog converter is used for outputting a corresponding second feedback signal to the second amplifier according to the logic result so as to correct the direct current offset of the second amplifier.
6. The wireless signal transceiver of claim 5, wherein the signal processing unit comprises a mixer for mixing a received high frequency signal with the local oscillation frequency and converting the mixed signal into an intermediate frequency signal as the analog signal.
7. The wireless signal transceiver of claim 5, wherein the first amplifier is a transductor amplifier.
8. The wireless signal transceiver of claim 5, wherein the digital-to-analog converter is a quiescent current generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710801003.9A CN109474551B (en) | 2017-09-07 | 2017-09-07 | DC offset calibration circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710801003.9A CN109474551B (en) | 2017-09-07 | 2017-09-07 | DC offset calibration circuit |
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| CN109474551A CN109474551A (en) | 2019-03-15 |
| CN109474551B true CN109474551B (en) | 2021-11-19 |
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| CN201710801003.9A Active CN109474551B (en) | 2017-09-07 | 2017-09-07 | DC offset calibration circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112825487B (en) * | 2019-11-18 | 2024-03-15 | 深圳市中兴微电子技术有限公司 | Radio frequency receiving link and radio frequency transceiver |
| CN113727266B (en) * | 2021-09-02 | 2022-11-01 | 苏州纳芯微电子股份有限公司 | MEMS microphone control circuit and electronic equipment |
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2017
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| US7667631B1 (en) * | 2006-12-19 | 2010-02-23 | Actel Corporation | Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded analog comparators |
| EP2198521A1 (en) * | 2007-09-26 | 2010-06-23 | Medtronic, Inc. | Chopper-stabilized analog-to-digital converter |
| CN101286961A (en) * | 2008-05-26 | 2008-10-15 | 华为技术有限公司 | Correcting device and method for direct current off-set outputted by equipment |
| CN106093547A (en) * | 2016-08-04 | 2016-11-09 | 贵州电网有限责任公司电力科学研究院 | Rogowski coil current transformer measuring device and method based on auxiliary coil correction |
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