CN109471761B - Embedded real-time operating system time performance test system applying FPGA - Google Patents
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Abstract
The invention belongs to the technical field of software evaluation, and particularly relates to an embedded real-time operating system time performance testing system applying an FPGA. In order to accurately measure the time performance index of the embedded real-time operating system, the invention provides the time performance measuring system of the embedded operating system, which triggers an excitation signal and measures parameter configuration through an FPGA (field programmable gate array), runs a time performance test program on a target computer, receives a response signal, calculates a time interval through the FPGA, stores time interval data and forwards the data to an upper computer, and the upper computer performs time performance analysis. The technical scheme of the invention adopts a test scheme combining FPGA measurement and a target machine test function, realizes the timing function and the external excitation by the FPGA, reduces the system call in a test program, reduces the signal delay time and improves the flexibility of the time performance test of an embedded real-time operating system.
Description
Technical Field
The invention belongs to the technical field of software evaluation, and particularly relates to an embedded real-time operating system time performance testing system applying an FPGA.
Background
An embedded real-time operating system is a special-purpose computer operating system with strict requirements on real-time performance, which is real-time and achieves certainty of time performance and run time. The task switching time, the interrupt response time, the task preemption time and the semaphore delay time are important indexes reflecting the time performance of the embedded operating system.
The time performance test method of the embedded real-time operating system comprises a benchmark test method and a hardware method. The benchmark test method is a method that a series of performance benchmark test programs are defined, time data obtained according to the RTOS self time base, such as RhealStone, a process dispatching delay time method, a Hartstone method and an Lmbench method, are relatively quick, but frequent system scheduling in the benchmark test programs also enables a large amount of CPU time to be occupied, and test precision is affected. The hardware method mainly utilizes embedded development auxiliary equipment such as an oscilloscope, a logic analyzer and the like to be combined with a test program to test the time performance of the system, but the auxiliary equipment is only responsible for acquiring the measurement time and has poor flexibility.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide an embedded real-time operating system time performance test system applying FPGA to reduce the system call of test programs, reduce the signal delay time, improve the test precision and increase the test flexibility.
(II) technical scheme
In order to solve the technical problem, the invention provides an embedded real-time operating system time performance test system applying an FPGA, wherein the time performance test system is divided into an FPGA module and a tested end module;
the FPGA module comprises: the device comprises a work instruction signal generating module, a first time recording module, a response signal receiving module, a fourth time recording module, a first time interval operation module and a storage module;
the measured end module comprises: the work task execution module responds to the signal generation module;
wherein the content of the first and second substances,
the working instruction signal generating module is used for providing a working instruction signal for the target machine, and the first time recording module is used for recording the first time when the working instruction signal is sent out and taking the first time as a time measurement starting point;
the work task execution module is used for executing a corresponding work task according to the work instruction signal after the target machine receives the work instruction signal;
the response signal generation module is used for generating a response signal and outputting the response signal after the work task execution module finishes the work task;
the response signal receiving module is used for receiving the response signal;
the fourth time recording module is used for counting by adopting the self time reference of the FPGA module and recording the receiving time of the response signal, namely the fourth time, as a time measurement termination point;
the first time interval operation module is used for operating the time interval between the first time and the fourth time to obtain a first time interval;
the storage module stores and transmits a plurality of groups of measured time interval data to an upper computer;
and then the upper computer performs statistical analysis on the received time interval data to obtain a time performance test result.
The time performance test system is suitable for testing the performance indexes of task switching time, semaphore delay time, task preemption time and interrupt response time of the embedded real-time operating system.
Wherein the work instruction signal comprises: task switching signals, task preemption signals, and interrupt signals.
Wherein, the FPGA module further comprises: a second time interval operation module;
the measured end module further comprises: the second time recording module and the third time recording module;
the target machine receives a work instruction signal, the work task execution module executes a corresponding work task according to the work instruction signal and simultaneously performs time measurement related to the work task, the second time recording module is used for recording a second time when the work task starts to be executed, the third time recording module is used for recording a third time when the work task is finished, and the response signal generation module generates and outputs a response signal carrying the second time and the third time;
the second time interval operation module is used for operating the time interval between the second time and the third time to obtain a second time interval; the storage module stores and forwards the measured multiple groups of time interval data to the upper computer.
Wherein, in the working process of the working instruction signal generation module, the method comprises the following steps:
the upper computer configures configuration parameters of the working instruction signal;
the working instruction signal generating module receives configuration parameters of a working instruction signal of the upper computer;
and the working instruction signal generation module outputs corresponding working instruction signals according to the configuration parameters and sends the working instruction signals to the target machine.
The second time output by the second time recording module is output in the form of a starting level signal, and the third time output by the third time recording module is output in the form of a terminating level signal.
And the starting level signal and the ending level signal are respectively output by the second time recording module and the third time recording module in due time according to the task execution condition of the target.
Wherein the work instruction signal further comprises a timing excitation signal;
the starting level signal is generated by the second time recording module under the excitation of the timing excitation signal, and the ending level signal is timely responded and output by the third time recording module according to the task execution condition.
Wherein, the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
and the second time and the third time are respectively a starting level signal and a terminating level signal which are timely output by the target machine and are used as a starting point and a terminating point of time measurement.
Wherein, the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
and the second time and the third time are respectively a starting level signal generated by excitation of the excitation signal and an ending level signal timely responded and output by the target machine and serve as a starting point and an ending point of time measurement.
(III) advantageous effects
Compared with the prior art, the method measures the time performance of the embedded real-time operating system, realizes the external excitation and timing functions by the FPGA, realizes data statistical analysis by the upper computer, reduces the system call and signal delay time in the test process compared with a benchmark test method, improves the test precision, and improves the test flexibility compared with a hardware method.
Drawings
Fig. 1 is a schematic structural diagram of a test system according to the technical solution of the present invention.
Fig. 2 is a flowchart of a method for testing time performance index of an embedded real-time operating system using FPGA in the scheme of the present invention.
Fig. 3 is a flowchart of a task switching time performance index target machine testing procedure in the solution of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the problems of the prior art, the invention provides an embedded real-time operating system time performance test system applying an FPGA, as shown in FIGS. 1-3, the time performance test system is divided into an FPGA module and a tested end module;
the FPGA module comprises: the device comprises a work instruction signal generating module, a first time recording module, a response signal receiving module, a fourth time recording module, a first time interval operation module and a storage module;
the measured end module comprises: the work task execution module responds to the signal generation module;
wherein the content of the first and second substances,
the working instruction signal generating module is used for providing a working instruction signal for the target machine, and the first time recording module is used for recording the first time when the working instruction signal is sent out and taking the first time as a time measurement starting point;
the work task execution module is used for executing a corresponding work task according to the work instruction signal after the target machine receives the work instruction signal;
the response signal generation module is used for generating a response signal and outputting the response signal after the work task execution module finishes the work task;
the response signal receiving module is used for receiving the response signal;
the fourth time recording module is used for counting by adopting the self time reference of the FPGA module and recording the receiving time of the response signal, namely the fourth time, as a time measurement termination point;
the first time interval operation module is used for operating the time interval between the first time and the fourth time to obtain a first time interval;
the storage module stores and transmits a plurality of groups of measured time interval data to an upper computer;
and then the upper computer performs statistical analysis on the received time interval data to obtain a time performance test result.
The time performance test system is suitable for testing the performance indexes of task switching time, semaphore delay time, task preemption time and interrupt response time of the embedded real-time operating system.
Wherein the work instruction signal comprises: task switching signals, task preemption signals, and interrupt signals.
Wherein, the FPGA module further comprises: a second time interval operation module;
the measured end module further comprises: the second time recording module and the third time recording module;
the target machine receives a work instruction signal, the work task execution module executes a corresponding work task according to the work instruction signal and simultaneously performs time measurement related to the work task, the second time recording module is used for recording a second time when the work task starts to be executed, the third time recording module is used for recording a third time when the work task is finished, and the response signal generation module generates and outputs a response signal carrying the second time and the third time;
the second time interval operation module is used for operating the time interval between the second time and the third time to obtain a second time interval; the storage module stores and forwards the measured multiple groups of time interval data to the upper computer.
Wherein, in the working process of the working instruction signal generation module, the method comprises the following steps:
the upper computer configures configuration parameters of the working instruction signal;
the working instruction signal generating module receives configuration parameters of a working instruction signal of the upper computer;
and the working instruction signal generation module outputs corresponding working instruction signals according to the configuration parameters and sends the working instruction signals to the target machine.
The second time output by the second time recording module is output in the form of a starting level signal, and the third time output by the third time recording module is output in the form of a terminating level signal.
And the starting level signal and the ending level signal are respectively output by the second time recording module and the third time recording module in due time according to the task execution condition of the target.
Wherein the work instruction signal further comprises a timing excitation signal;
the starting level signal is generated by the second time recording module under the excitation of the timing excitation signal, and the ending level signal is timely responded and output by the third time recording module according to the task execution condition.
Wherein, the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
and the second time and the third time are respectively a starting level signal and a terminating level signal which are timely output by the target machine and are used as a starting point and a terminating point of time measurement.
Wherein, the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
and the second time and the third time are respectively a starting level signal generated by excitation of the excitation signal and an ending level signal timely responded and output by the target machine and serve as a starting point and an ending point of time measurement.
In addition, the invention also provides a time performance test method of the embedded real-time operating system applying the FPGA, the time performance test method is implemented based on a time performance test system, and the time performance test system is divided into an FPGA module and a tested end module;
the FPGA module comprises: the device comprises a work instruction signal generating module, a first time recording module, a response signal receiving module, a fourth time recording module and a first time interval operation module;
the measured end module comprises: the work task execution module responds to the signal generation module;
the time performance testing method comprises the following steps:
step 1: the working instruction signal generating module provides a working instruction signal for the target machine, and the first time recording module records the first time when the working instruction signal is sent out as a time measurement starting point;
step 2: the target machine receives the work instruction signal, the work task execution module executes a corresponding work task according to the work instruction signal, and after the work task is completed, the response signal generation module generates a response signal and outputs the response signal;
and step 3: a response signal receiving module receives the response signal;
and 4, step 4: the fourth time recording module counts by adopting the self time reference of the FPGA module, records the receiving time of the response signal, namely the fourth time, and takes the fourth time as a time measurement termination point;
and 5: the first time interval operation module operates the time interval between the first time and the fourth time to obtain a first time interval; the storage module stores and transmits a plurality of groups of measured time interval data to an upper computer;
step 6: and the upper computer performs statistical analysis on the received time interval data to obtain a time performance test result.
The time performance testing method is suitable for testing the performance indexes of task switching time, semaphore delay time, task preemption time and interrupt response time of the embedded real-time operating system.
Wherein, in step 1, the work instruction signal includes: task switching signals, task preemption signals, and interrupt signals.
Wherein, the FPGA module further comprises: a second time interval operation module;
the measured end module further comprises: the second time recording module and the third time recording module;
the step 2 comprises the following steps: the target machine receives the working instruction signal, the working task execution module executes a corresponding working task according to the working instruction signal and simultaneously performs time measurement related to the working task, the second time recording module records second time when the working task starts to be executed, the third time recording module records third time when the working task is finished, and the response signal generation module generates and outputs a response signal carrying the second time and the third time;
the step 4 comprises the following steps: the second time interval operation module operates the time interval between the second time and the third time to obtain a second time interval; the storage module stores and forwards the measured multiple groups of time interval data to the upper computer.
Wherein, the step 1 comprises the following steps:
step 101: the upper computer configures configuration parameters of the working instruction signal;
step 102: the working instruction signal generating module receives configuration parameters of a working instruction signal of the upper computer;
step 103: and the working instruction signal generation module outputs corresponding working instruction signals according to the configuration parameters and sends the working instruction signals to the target machine.
Wherein, in the step 2:
the second time output by the second time recording module is output in the form of a starting level signal, and the third time output by the third time recording module is output in the form of a terminating level signal.
Wherein, in the step 2,
the starting level signal and the ending level signal are respectively output by the second time recording module and the third time recording module in due time according to the task execution condition of the target.
Wherein the work instruction signal further comprises a timing excitation signal;
in the step 2, the starting level signal is generated by the second time recording module under the excitation of the timing excitation signal, and the ending level signal is timely responded and output by the third time recording module according to the task execution condition of the target.
Wherein, in the step 4,
the second time interval operation module operates the time interval between the second time and the third time to obtain a second time interval,
the second time and the third time are respectively a starting level signal and a terminating level signal which are timely output by the target machine and are used as a starting point and a terminating point of time measurement.
Wherein, in the step 4,
the second time interval operation module operates the time interval between the second time and the third time to obtain a second time interval,
the second time and the third time are respectively a starting level signal generated by excitation of the excitation signal and an ending level signal timely responded and output by the target machine and serve as a starting point and an ending point of time measurement.
Example 1
The embodiment specifically describes the method for testing the time performance index of the embedded real-time operating system using the FPGA. The detection method is applied to the performance test of the interrupt response time of the embedded real-time operating system.
As shown in fig. 1, the time testing method includes the following steps:
step 1: the FPGA provides an excitation signal to the target machine, and the input excitation signal is an external interrupt source of the target machine. Step 1 comprises the following steps:
step 101, setting the frequency f, the signal duration t and the triggering times n of an interruption triggering signal on an upper computer, and determining the parameters of an interruption input source of a target machine;
step 102, sending the excitation input source configuration parameters to the FPGA
And 103, outputting an interrupt signal to the target machine by the FPGA according to the configuration parameters.
Step 2: running a performance test program on a target machine, and outputting a starting signal level and a terminating signal level of a measuring time;
here, the initial level signal required for time performance index measurement is generated by the excitation of the FPGA; the termination level signal is output by the test program response. The interrupt processing service program processes the interrupt signal and sends a feedback signal to the FPGA through the pin, so that the test process is more accurate, the interrupt service program does not do any other work and only feeds the signal back to the FPGA after receiving the interrupt.
And step 3: the FPGA receives the time measurement start signal level and the end signal level of the output of the target machine. The FPGA sends an excitation signal to the target machine as a time measurement starting point, and the target machine test program responds to an output end level signal as a time measurement end point.
And 4, step 4: the FPGA counts by adopting a self time reference, and measures the time interval of the initial signal level and the termination signal level;
and when the FPGA sends an interrupt signal to the target machine, the FPGA is used as a timing starting signal to start timing, a feedback signal of the target machine is received as an end signal to stop timing, and the obtained time is the response time of the interrupt request.
And 5: and the FPGA stores and forwards the measured multiple groups of time interval data to the upper computer.
And the FPGA measures the interrupt response time for many times, and the upper computer calculates to obtain a statistical result.
Step 6: the upper computer performs statistical analysis on the received time interval data, and the table 1 shows test results:
TABLE 1 interrupt response time
Example 2
The present example specifically describes the method for testing the time performance index of the embedded real-time operating system using the FPGA according to the present invention. The detection method is applied to the task switching time performance test of the embedded real-time operating system.
The time performance testing method comprises the following steps:
step 1: testing measurement parameter configuration for task switching time, and setting measurement times;
step 2: running a performance test program on a target machine, and outputting a starting signal level and a terminating signal level of a measuring time;
and the initial level signal and the termination level signal which need to be output during the task switching time performance measurement are both output by the test program at proper time. As shown in fig. 3:
(1) creating a task 1 and a task 2 which are connected with the same priority, and endowing the two tasks with the highest priority of the system in order to avoid the influence of other tasks of the system;
(2) after entering the circulation, the task 1 immediately abandons the operation and switches to the task 2;
(3) after the task 2 is activated, no work is done, and the task 1 is switched to;
(4) and repeating the steps 3 and 4.
When the task switching function enters and exits, outputting an initial level signal and a termination level signal to the FPGA;
and step 3: the FPGA receives the time measurement initial signal level and the termination signal level output by the target machine;
and 4, step 4: the FPGA counts by adopting a self time reference, and measures the time interval of the initial signal level and the termination signal level;
and 5: the FPGA stores the measured time interval data with fixed group number and transmits the data to the upper computer;
step 6: the upper computer performs statistical analysis on the received time interval data, and the table 2 shows test results:
TABLE 2 task switching time
Example 3
The embodiment provides a time performance index testing method of an embedded real-time operating system applying an FPGA, and the testing method is applied to time performance testing of the embedded real-time operating system.
The time performance testing method comprises the following steps:
step 1: the FPGA provides an excitation signal for the target machine;
step 2: the target machine responds to the excitation and outputs a response signal, and outputs a starting signal level and a terminating signal level of the measuring time;
and step 3: the FPGA receives the time measurement initial signal level and the termination signal level output by the target machine;
and 4, step 4: the FPGA counts by adopting a self time reference, and measures the time interval of the initial signal level and the termination signal level;
and 5: the FPGA stores and transmits a plurality of groups of measured time interval data to an upper computer;
step 6: the upper computer performs statistical analysis on the received time interval data;
wherein, the step 1 comprises the following steps:
step 1.1: the upper computer configures excitation parameters and measurement parameters of the FPGA;
step 1.2: the FPGA receives excitation configuration parameters and measurement parameter configuration of an upper computer;
step 1.3: and the FPGA outputs corresponding excitation signals according to the configuration parameters.
Wherein, the step 2 comprises two conditions:
(1): the initial level signal and the termination level signal which need to be output when the time performance index is measured are timely output by the target machine;
(2): the initial level signal required in the time performance index measurement is generated by FPGA excitation, and the termination level signal is timely responded and output by the target machine.
Wherein, the step 3 comprises two conditions:
(1): the FPGA receives a starting level signal and a terminating level signal which are timely output by a target machine and are used as a starting point and a terminating point of time measurement;
(2): the FPGA takes an excitation signal given to the target machine as a time measurement starting point, and the target machine responds to an output end level signal as a time measurement end point.
In conclusion, the invention measures the time performance of the embedded real-time operating system, realizes the functions of external excitation and timing by the FPGA, realizes data statistical analysis by the upper computer, reduces the system call and signal delay time in the test process compared with a benchmark test method, improves the test precision, and improves the test flexibility compared with a hardware method.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (1)
1. The time performance test system of the embedded real-time operating system applying the FPGA is characterized in that the time performance test system is divided into an FPGA module and a tested end module;
the FPGA module comprises: the device comprises a work instruction signal generating module, a first time recording module, a response signal receiving module, a fourth time recording module, a first time interval operation module and a storage module;
the measured end module comprises: the work task execution module responds to the signal generation module;
wherein the content of the first and second substances,
the working instruction signal generating module is used for providing a working instruction signal for the target machine, and the first time recording module is used for recording the first time when the working instruction signal is sent out and taking the first time as a time measurement starting point;
the work task execution module is used for executing a corresponding work task according to the work instruction signal after the target machine receives the work instruction signal;
the response signal generation module is used for generating a response signal and outputting the response signal after the work task execution module finishes the work task;
the response signal receiving module is used for receiving the response signal;
the fourth time recording module is used for counting by adopting the self time reference of the FPGA module and recording the receiving time of the response signal, namely the fourth time, as a time measurement termination point;
the first time interval operation module is used for operating the time interval between the first time and the fourth time to obtain a first time interval;
the storage module stores and transmits a plurality of groups of measured time interval data to an upper computer;
then, the upper computer carries out statistical analysis on the received time interval data to obtain a time performance test result;
the time performance test system is suitable for testing the performance indexes of task switching time, semaphore delay time, task preemption time and interrupt response time of the embedded real-time operating system;
the work instruction signal includes: a task switching signal, a task preemption signal and an interrupt signal;
the FPGA module further comprises: a second time interval operation module;
the measured end module further comprises: the second time recording module and the third time recording module;
the target machine receives a work instruction signal, the work task execution module executes a corresponding work task according to the work instruction signal and simultaneously performs time measurement related to the work task, the second time recording module is used for recording second time when the work task is started to be executed, the third time recording module is used for recording third time when the work task is finished to be executed, and the response signal generation module generates and outputs a response signal carrying the second time and the third time;
the second time interval operation module is used for operating the time interval between the second time and the third time to obtain a second time interval; the storage module stores and transmits a plurality of groups of measured time interval data to an upper computer;
in the working process of the working instruction signal generation module, the method comprises the following steps:
the upper computer configures configuration parameters of the working instruction signal;
the working instruction signal generating module receives configuration parameters of a working instruction signal of the upper computer;
the working instruction signal generation module outputs corresponding working instruction signals according to the configuration parameters and sends the working instruction signals to the target machine;
the second time output by the second time recording module is output in the form of an initial level signal, and the third time output by the third time recording module is output in the form of a termination level signal;
the starting level signal and the ending level signal are respectively output by the second time recording module and the third time recording module in due time according to the task execution condition of the target;
the work instruction signal further comprises a timing excitation signal;
the starting level signal is generated by the second time recording module under the excitation of the timing excitation signal, and the ending level signal is timely responded and output by the third time recording module according to the task execution condition of the target;
the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
the second time and the third time are respectively a starting level signal and a terminating level signal which are timely output by the target machine and are used as a starting point and a terminating point of time measurement;
the second time interval operation module operates the time interval between the second time and the third time to obtain the second time interval,
and the second time and the third time are respectively a starting level signal generated by excitation of the excitation signal and an ending level signal timely responded and output by the target machine and serve as a starting point and an ending point of time measurement.
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| CN106776272A (en) * | 2016-11-11 | 2017-05-31 | 西北工业大学 | Embedded system real-time performance testing method |
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