CN109467044B - Monolithically integrated CMOS and MEMS micro-heater and preparation method thereof - Google Patents
Monolithically integrated CMOS and MEMS micro-heater and preparation method thereof Download PDFInfo
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/00373—Selective deposition, e.g. printing or microcontact printing
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Abstract
The invention discloses a monolithic integrated CMOS and MEMS micro heater and a preparation method thereof, wherein the integrated CMOS and MEMS micro heater with a thermal film structure comprises: a heat insulating layer formed on the surface of the CMOS structure; an insulating layer I formed on the surface of the insulating layer; dry etching openings of pads for connection with the electrode posts on the heat insulating layer and the insulating layer I; electrode posts formed on the surface of the insulating layer I; forming a cavity and a suspended heating structure between the electrode columns; the heating structure comprises a supporting layer, an insulating layer, a step structure layer, a heating layer and a passivation layer from bottom to top in sequence; the insulating layer is covered on the supporting layer; the step structure layer is positioned on the insulating layer; the heating layer is covered on the composite structure comprising the supporting layer, the insulating layer and the step structure layer and covers the upper surface of the electrode column; a passivation layer covers the heating layer; the CMOS/ASIC circuit of the heat insulation layer is connected with the electrode post; the insulating layer I, the electrode column and the supporting layer jointly form a cavity of the suspended heater structure.
Description
Technical Field
The invention relates to the technical field of microelectronic devices and preparation thereof, in particular to a monolithically integrated CMOS and MEMS micro heater and a preparation method thereof.
Background
At present, the existing micro-heater preparation process mainly adopts a front-side or back-side bulk silicon etching process, and the connection mode of the micro-heater MEMS device and the readout circuits such as CMOS/ASIC and the like is mainly through a wire bonding-bonding packaging technology. The micro heater prepared by the process has the defects of large size, large power consumption, difficult array, large stress of a sensitive film, poor heat insulation, unsatisfactory high-temperature heat stability and the like. The development and the application of micro-devices such as micro-heating structure sensors, e.g. micro-gas sensors, micro-calorimeters, micro-barometers, micro-accelerometers, electronic noses and the like are restricted; the MEMS device and the CMOS circuit are independently prepared and then a wire bonding-bonding packaging mode is adopted, the size of the MEMS+CMOS integrated module cannot be reduced, the packaging process is prolonged in preparation period, and the yield is easily reduced in the packaging process.
With the recent development of modern microelectronics technology, micro-hotplates which are small in size, low in power consumption and easy to combine with other materials or devices are increasingly emphasized, but the use of micro-hotplates brings about certain thermal power loss and instability of devices.
In the prior art, in order to reduce heat consumption, a heat insulation groove with a front or back suspended structure is commonly adopted for realizing structural heat preservation. One commonly used structure for micro-hotplates is: a silicon dioxide (SiO 2) or silicon nitride (SiN) film layer is deposited on the upper surface of the substrate as an insulating layer, and a heat insulation groove is prepared on the lower surface of the silicon substrate by dry etching. And depositing a silicon nitride layer on the surface of the heating wire to serve as a passivation layer. For example, the processing method of the silicon-based micro-hotplate disclosed in CN 104541161A adopts a process of preparing an adiabatic slot on the back surface of a silicon substrate; the micro-heating plate manufactured by the method has the size of 600-1000 mu m, but the heating layer is supported by only one silicon nitride layer of a thin film structure after the heat insulation groove is etched by the method, and the thin film is supported by the supporting substrate at two ends, so that the stress control of the thin film structure is poor, the strength is insufficient, and the device is easy to break when the device is shocked or collided, so that the device is invalid. The other method is as follows: and preparing the heat insulation groove on the upper surface of the silicon substrate by wet etching. For example, CN 104176699A discloses a method for processing a silicon-based micro-hotplate, which adopts a process of preparing an insulating groove on the front surface of a silicon substrate. The micro-thermal plate described in the patent is characterized in that heat is isolated by utilizing a heat insulation groove mode, a certain insulating layer and a certain heat insulation layer are formed by a film growth mode, then a heating electrode and a test electrode layer are formed by sputtering, stripping and etching, and then a certain heat insulation groove structure is formed by etching from the front side. The micro heater prepared by the method for etching the front-side bulk silicon has the device size of 300-1000 mu m due to the limitation of the preparation process, and the process difficulty is larger than that of a thermal insulation groove prepared by etching the back-side bulk silicon. From the above, in the preparation process of the two micro-heaters, the two micro-heaters have larger power consumption, the micro-heater prepared by the front-side bulk silicon etching process is about 20mW, and the micro-heater prepared by the back-side bulk silicon etching process is 70mW to 80mW; in addition, in the processing process, the preparation of the heat insulation layer, the heating electrode layer and the test electrode layer is mainly realized by adopting a single-sided film compounding mode, so that the device is invalid due to the fact that the layers of the films are too many and stress is easy to generate. In summary, the two micro-heaters have the defects of hundreds to thousands of micrometers in size, high power consumption, high film stress and insufficient thickness, and have the advantages of small size, low power consumption, easy realization of array, high mechanical strength, good product yield and the like. In addition, the structural design and the manufacturing process of the MEMS and CMOS integrated manufacturing not only can reduce the later MEMS device and CMOS packaging process, shorten the manufacturing period of the MEMS and CMOS module and avoid the reduced product yield caused by the process, but also obviously reduce the size of the MEMS and CMOS module.
Disclosure of Invention
From the above description, it can be concluded that the conventional micro-heater manufacturing process has the following drawbacks: the micro-heater prepared by the front-side bulk silicon process and the micro-heater prepared by the back-side bulk silicon process are several hundred to thousands of micrometers in size, and the micro-heater has poor structural heat preservation performance and high power consumption; the micro heater prepared by the traditional front/back bulk silicon etching process is easy to cause device failure due to stress between films in the preparation process, and cannot realize the advantages of high heat preservation and insulation, high mechanical strength, high product yield and the like; in the process of preparing and packaging, the process difficulty of preparing the micro-heater by the front-side bulk silicon etching technology is high, the micro-heater prepared by the back-side bulk silicon etching method is easy to generate loss due to the back cavity structure in the packaging process, and both the micro-heaters have the characteristic of low yield. Namely, the micro heater prepared by the traditional method has the defects of large size, high power consumption, high process difficulty, low yield, high film stress, low mechanical strength and the like. In addition, it is obvious that the packaging method of post wire bonding in discrete preparation of MEMS device and CMOS/ASIC readout circuit has the disadvantages of longer product realization period, complex process and larger size of MEMS+CMOS module.
Aiming at the defects of the micro-heater prepared by the traditional process, the structure and the processing process are optimized by additionally providing the micro-heater with the integrated CMOS and MEMS thermal film structure, the preparation method thereof and the electronic nose array, and in addition, the micro-heater with the integrated CMOS and MEMS thermal film structure, the preparation method thereof and the electronic nose array can reduce the packaging process, integrate the process, shorten the preparation period, simplify the preparation/packaging process and reduce the size of the MEMS and CMOS module by integrating the MEMS and CMOS. The following characteristics are realized: the micro-heating device has the characteristics of small size (the suspended micro-heating structure can reach 17 mu m), good heat preservation and insulation performance, low power consumption (reaching several microwatts), simple process, high structural strength and capability of being arrayed, thus realizing an electronic nose array, realizing process integration by MEMS and CMOS integrated preparation, shortening the period, simplifying the preparation process and the like.
In order to achieve the above object, the preparation method of the monolithically integrated CMOS and MEMS micro-heater provided by the present invention comprises the following steps:
step S1: an insulating layer is prepared over the prepared CMOS or ASIC circuit and an opening in the insulating layer for the pad on the CMOS to connect to the electrode pillar is opened using dry etching.
Step S2, preparing an insulating layer I on the insulating layer, and opening an opening of the pad on the CMOS for connecting with the electrode pillar on the insulating layer I by dry etching.
Step S3: and coating a first photoresist layer required by the first Al layer and patterning.
Step S4: evaporating or sputtering a first Al layer.
Step S5: the first photoresist layer was stripped by a lift-off process and first layer electrode pillars were prepared.
Step S6: and coating a second photoresist layer required by the second Al layer and patterning.
And S7, evaporating or sputtering a second Al layer.
Step S8: and stripping the second photoresist layer by a lift-off process and preparing a second layer of electrode posts to obtain the final required electrode posts.
And S9, preparing a sacrificial layer on the surface of the silicon substrate containing the electrode column of the step S8.
Step S10: and preparing a supporting layer on the surfaces of the electrode posts and the sacrificial layer by adopting a chemical vapor deposition CVD method.
Step S11: and preparing an insulating layer II on the supporting layer by adopting a chemical vapor deposition CVD method.
Step S12: and preparing a step structure layer with stress release on the insulating layer II.
Step S13: and preparing a heating layer on the surface of the composite structure comprising the supporting layer, the insulating layer II and the step structure layer, wherein the heating layer covers the upper surface of the electrode column.
Step S14: a passivation layer is prepared on the heating layer.
Step S15: and releasing the sacrificial layer by adopting an isotropic wet etching or dry etching method to form a cavity, so as to manufacture the micro heater with the integrated CMOS and MEMS thermal film structure.
Preferably, the sacrificial layer material is: polyimide PI or silicon oxide SiO 2 or silicon nitride SiN or amorphous silicon a-Si or polysilicon poly-Si or metallic Cu or metallic Al.
The invention further provides a micro heater with a thermal film structure integrating CMOS and MEMS, comprising: a heat insulating layer and a heat insulating layer I are formed on the upper surface of the CMOS or ASIC circuit, and openings for the pad connected with the electrode posts are etched; electrode posts formed on the surface of the insulating layer I; forming a cavity and a suspended heating structure between the electrode columns; the heating structure comprises a supporting layer, an insulating layer II, a step structure layer, a heating layer and a passivation layer from bottom to top in sequence; wherein the insulating layer II covers the supporting layer; the step structure layer is positioned in the area right above the insulating layer II; the heating layer is covered on the composite structure comprising the supporting layer, the insulating layer II and the step structure layer and covers the upper surface of the electrode column; a passivation layer covers the heating layer; the insulating layer I, the electrode column and the supporting layer jointly form a cavity of the micro-heater with the thermal film structure integrating CMOS and MEMS, and the micro-heater is in a suspended structure.
Preferably, the heating layer is located in the area right above the cavity, the supporting layer, the insulating layer II and the step structure layer, and covers the upper surface of the electrode pillar.
Preferably, the material of the heat insulating layer is porous silicon, the thickness is 10-100 μm, and the porosity is 50-90%; the silicon wafer used for preparing the CMOS or ASIC circuit is monocrystalline silicon wafer with the thickness of 200 μm-500 μm; the insulating layer I is made of silicon oxide, and the thickness of the insulating layer I is 50 nm-2 mu m; the insulating layer II is made of silicon nitride SiN or silicon oxide SiO 2 or ceramic aluminum oxide Al 2O3, and the thickness is 50 nm-500 m.
Preferably, the step depth of the step structure layer is 100-1000 nm, the step line width is 1-50 μm, and the step gap width is 0.5-50 μm. The material is silicon oxide SiO 2/silicon nitride SiN.
Preferably, the material of the supporting layer is porous silicon/silicon oxide SiO 2/ceramic aluminum oxide Al2O3, and the thickness is 200 nm-5 mu m; when porous silicon is adopted, the porosity is 50-90%.
Preferably, the heating layer is made of TaAlN or polysilicon poly-Si or W or TiN or Mo or Pt film, and the thickness is 50-500 nm;
Preferably, the passivation layer is made of silicon nitride SiN or silicon oxide SiO 2 or polyimide PI, and the thickness is 50 nm-3 μm.
The invention further provides the electronic nose array, a plurality of the micro-heaters with the integrated CMOS and MEMS thermal film structures are arranged and prepared in different areas on the surface of a silicon wafer, and each micro-heater is connected with a CMOS/ASIC circuit below the micro-heater through an electrode column and a connection pad on the CMOS or ASIC circuit.
The beneficial effects are that: the micro-heater with the integrated CMOS and MEMS thermal film structure adopts the supporting layer, the insulating layer II and the step structure layer, so that the heat insulation performance of the micro-heater is improved, and the structural strength of the micro-heater is enhanced by the multiple composite structure; in structural design, the heat insulation layer and the insulation layer II on the surface of the CMOS/ASIC circuit further enhance the heat insulation performance of the device, and further improve the performances of heat preservation and low power consumption; the step structure layer has the effect of stress release, has the effect similar to a spring in the heating process, and enhances the structural strength of the micro heater; the bridge type thermal film micro-heater is prepared by a surface silicon technology, the micro-heating structure can reach 17 mu m, compared with a micro-heater prepared by a bulk silicon etching technology (the size is hundreds to thousands of mu m), the bridge type thermal film micro-heater has the advantages of greatly reducing the structural size, having the characteristic of easy array, and having the advantages of reducing the size and easy realization in the aspect of preparing an electronic nose. The step-by-step coating technology overcomes the defect of one-step coating (the one-step coating of the electrode column has the height limitation), increases the height of the electrode column, and can improve the electrical conductivity and the yield; compared with the method of bulk silicon etching, the preparation of the cavity of the micro-heater with the integrated CMOS and MEMS thermal film structure is realized by preparing the sacrificial layer and releasing the sacrificial layer later, and the sacrificial layer material and the corresponding etching technology selected in the preparation process of the micro-heater with the bridge thermal film structure have the characteristics of mature process, simple etching process and the like, so that the micro-heater with the surface bulk silicon technology has the advantages of easy realization and simple process, greatly reduces the process difficulty compared with the preparation process of the micro-heater with the front/back bulk silicon etching technology, and improves the product yield of the micro-heater. Has the advantages of practicability and realization.
Drawings
FIG. 1 is a top view of a micro-heater of the integrated CMOS and MEMS thermal film structure of the present invention.
Fig. 2 is a step stress relief structure (ring shape) of the micro-heater of the integrated CMOS plus MEMS thermal film structure of the present invention.
Fig. 3 is a step stress relief structure (loop shape) of the integrated CMOS plus MEMS thermal film structured micro-heater of the present invention.
Fig. 4 is a diagram of an electronic nose array structure according to the present invention.
Fig. 5 is a top view of an electronic nose array according to the present invention.
FIG. 6 is a schematic diagram of a CMOS/ASIC circuit of the present invention.
Fig. 7 is a schematic diagram of a step S1 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 8 is a schematic diagram of a step S2 of the method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 9 is a schematic diagram of a step S3 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 10 is a schematic diagram of a step S4 of the method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
FIG. 11 is a schematic diagram of a step S5 of a method for fabricating a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 12 is a schematic diagram of a step S6 of the method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 13 is a schematic diagram of a step S7 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 14 is a schematic diagram of a step S8 of the method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 15 is a schematic diagram of a step S9 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 16 is a schematic diagram of a step S10 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
FIG. 17 is a schematic diagram of a step S11 of a method for fabricating a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
Fig. 18 is a schematic diagram of a step S12 of a method for fabricating a micro-heater with a thermal film structure for integrated CMOS and MEMS according to the present invention.
Fig. 19 is a schematic diagram of a step S13 of a method for manufacturing a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention.
FIG. 20 is a schematic diagram of a step S14 of a method for fabricating a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention. (before release of sacrificial layer)
FIG. 21 is a schematic diagram of a step S15 of a method for fabricating a micro-heater with a thermal film structure integrated with CMOS and MEMS according to the present invention. (after release of the sacrificial layer).
The attached drawings are identified:
1. A CMOS/ASIC circuit; 2. a heat insulating layer; 3. an insulating layer I; 4. an electrode column; 41. a first Al layer; 42. a second Al layer; 5. a sacrificial layer; 51. a first photoresist layer; 52. a second photoresist layer; 6. a support layer; 7. an insulating layer II; 8. a step structure layer; 9. a heating layer; 10. a passivation layer; 12. a cavity.
Detailed Description
In order to make the technical problems solved by the invention, the technical scheme adopted and the technical effects achieved clearer, the invention is further described in detail below with reference to the accompanying drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present invention are shown in the accompanying drawings.
Examples
1. Structure of the
Referring to fig. 1 and 21, the micro-heater of the present embodiment includes: a heat insulating layer 2 and an insulating layer I3 formed on the upper surface of the CMOS or ASIC circuit 1, and openings for pads connected with the electrode posts 4 are etched on the heat insulating layer 2 and the insulating layer I3 in a dry method; an electrode post 4 formed on the surface of the insulating layer I3; a cavity 12 and a suspended heating structure are formed between the electrode columns; the heating structure comprises a supporting layer 6, an insulating layer II 7, a step structure layer 8, a heating layer 9 and a passivation layer 10 from bottom to top in sequence; wherein the insulating layer II 7 covers the supporting layer 6; the step structure layer 8 is positioned in the area right above the insulating layer II 7; the heating layer 9 is covered on the composite structure comprising the supporting layer 6, the insulating layer II 7 and the step structure layer 8 and covers the upper surface of the electrode column 4; a passivation layer 10 covers the heating layer 9; the insulating layer I3, the electrode post 4 and the supporting layer 6 together form a cavity 12 of the micro heater with the integrated CMOS and MEMS thermal film structure, so that the heater forms a suspension structure.
Wherein the heating layer 9 is located in the region right above the supporting layer 6, the insulating layer ii 7 and the step structure layer 8, and the supporting layer 6, the insulating layer ii 7 and the step structure layer 8 can more stably support the heating layer 9, so as to effectively prevent the micro heater (abbreviated as device) from being broken due to no effective support when being impacted by vibration. Meanwhile, the step structure layer 8 can also effectively slow down the stress generated when the micro heater collides or the temperature changes sharply, avoid cracking and falling off caused by deformation and warping of the heating layer 9, effectively improve the stability and service life of the device during use, and ensure good heat insulation effect because the heating layer 9 is positioned in the area right above the cavity 12.
The effect of the step-like structure of the step-structure layer 8 on the stress relief and strength improvement is related to the choice of material, width and step pitch. On the premise of ensuring the process realization, the deeper the steps, the smaller the width and the smaller the spacing are, and the better the stress relief and strength improvement effects are.
In order to ensure that the step structure layer 8 can generate better supporting strength and heat insulation effect, the lower surface of the step structure layer 8 is covered with a layer of supporting layer 6, the material is porous silicon, the thickness of the porous silicon is 200 nm-5 mu m, the porosity is 50% -90%, and the porous silicon can also be silicon oxide/ceramic aluminum oxide, but the porous silicon is not limited to the porous silicon.
The material of the sacrificial layer 5 filled in the cavity 12 is porous silicon/polyimide PI or silicon oxide SiO 2 or silicon nitride SI 3N4 or amorphous silicon a-SI or polysilicon poly-SI or metal Cu or metal Al, etc., but is not limited thereto. Wherein, the porosity of the porous silicon is selected to be 50-90 percent.
In order to ensure that the step-shaped structure has better stress-relieving and strength-improving effects, the step depth of the step-shaped structure layer is 100-1000 nm, the step gap is 0.5-50 μm, the width is 1-50 μm, the step gap is preferably 1 μm in the embodiment, and the step width is preferably 1 μm.
Since the heating layer generally has higher conductivity, it is preferable to provide an insulating layer ii 7 on the supporting layer 6 for safety, and the insulating layer ii 7 may be silicon oxide SiO 2 or silicon nitride SiN, with a thickness of 50nm to 500nm.
The heating layer 9 may be a TaAlN thin film with a thickness of 50nm to 500nm.
The heating layer 9 may be, but not limited to, poly-Si/W/TiN/Mo/Pt.
Also, since the heating layer generally has high conductivity, it is preferable to provide a passivation layer 10 on the heating layer 9 for safety, and the passivation layer 10 may be SiN with a thickness of 50nm to 3 μm.
Preferably, the passivation layer 10 may also be silicon oxide SiO 2/polyimide PI.
The heating layer 9 and the passivation layer 10 are of a step structure; preferably, the step-like structure layer 8, the heating layer 9 and the passivation layer 10 each have a step-like spring-like structure.
To facilitate the routing of the heating layer 9, connection electrodes 11 are provided on the insulating layer 9 and connected to the electrode posts 4 for connection to readout circuits such as ASICs or CMOS.
To facilitate the preparation of the cavity 12, the cavity 12 is formed by releasing the sacrificial layer 5 that originally filled the cavity 12; the sacrificial layer 5 may be polyimide PI, silicon oxide SiO 2/silicon nitride SiN, amorphous silicon a-Si, polysilicon poly-Si, or the like, but is not limited thereto.
In order to facilitate the formation of the thermally insulating cavity 12, a porous silicon layer, i.e. the aforesaid insulating layer 2, is preferably prepared on the CMOS or ASIC circuit 1, with a thickness of 10 μm to 100 μm and a porosity of 50% to 90%. The CMOS/ASIC circuit 1 is preferably a silicon wafer, in particular a monocrystalline silicon substrate, with a thickness of 200 μm to 500 μm.
Referring to fig. 2 and 3, the stress relief step is annular or in a shape of a loop.
The integrated CMOS plus MEMS thermal film structure micro-heater structure of this embodiment can be sized to a length of 17 μm.
2. Parameter requirements
The parameters of each layer of the micro-heater with the integrated CMOS and MEMS thermal film structure in the embodiment are as follows:
1. CMOS/ASIC circuit: the thickness is 200 μm to 500 μm.
2. Insulation layer: porous silicon with thickness of 10-100 μm and porosity of 50-90%.
3. Insulating layer I: the thickness of the silicon oxide SiO 2 is 50 nm-2 μm.
4. Electrode column: the Al layer is plated by a step-by-step film plating method, and the thickness is 2-20 mu m.
5. Sacrificial layer: polyimide (PI) or silicon oxide SiO 2 or silicon nitride SIN or amorphous silicon a-Si or polysilicon poly-Si or metal Cu or metal Al, etc., with a thickness of 1 μm to 20 μm.
6. Support layer: the thickness of the porous silicon/silicon oxide SiO 2 or ceramic aluminum oxide Al 2O3 is 5-200 mu m, and the porosity is 50-90% when the porous silicon is used.
7. Insulating layer II: silicon nitride SiN or silicon oxide SiO 2 or ceramic aluminum oxide Al 2O3, and the thickness is 50 nm-500 nm.
8. Step structure layer: silicon nitride SiN or silicon oxide SiO 2, thickness 100 nm-3 μm, step line width: 100 nm-1000 nm, gap width: 0.5-50 μm.
9. And (3) a heating layer: taAlN or polysilicon poly-Si/W/TiN/Mo/Pt, etc. with the thickness of 50 nm-500 nm.
10. Passivation layer: silicon nitride SiN or silicon oxide SiO 2 or polyimide PI, 50 nm-3 μm thick three, electronic nose array
As shown in fig. 4 and 5, the heater array electronic nose using the surface silicon technology, each micro heater in the electronic nose is connected to the CMOS/ASIC circuit below the micro heater through the electrode pillars and the connection pad on the CMOS or ASIC circuit.
4. Preparation method
The preparation method of the micro-heater with the integrated CMOS and MEMS thermal film structure comprises the following steps:
referring to fig. 7, step S1: on the prepared CMOS or ASIC circuit 1 (structure is shown with reference to fig. 6) a thermal insulation layer 2 is prepared and on the thermal insulation layer 2 an opening for the pad on CMOS to be connected to the electrode pillar 4 is opened using dry etching.
Referring to fig. 8, step S2 is to prepare an insulating layer i 3 on the insulating layer 2 and open an opening for a pad on CMOS connected to the electrode pillar 4 using dry etching on the insulating layer i 3.
Referring to fig. 9, step S3: the first photoresist layer 51 required for the first Al layer 41 is coated and patterned.
Referring to fig. 10, step S4: the first Al layer 41 is evaporated or sputtered.
Referring to fig. 11, step S5: the first photoresist layer 51 is stripped by a lift-off process and a first layer electrode pillar is prepared.
Referring to fig. 12, step S6: a second photoresist layer 52 is applied and patterned as required for the second Al layer 42.
Referring to fig. 13, in step S7, the second Al layer 42 is evaporated or sputtered.
Referring to fig. 14, step S8: the second photoresist layer 52 is stripped by a lift-off process and a second layer of electrode pillars are prepared, resulting in the final desired electrode pillars.
Referring to fig. 15, step S9 is to prepare a sacrificial layer 5 on the surface of the silicon substrate containing the electrode pillars of step S8.
Referring to fig. 16, step S10: on the surfaces of the electrode posts 4 and the sacrificial layer 5, a support layer 6 is prepared by a chemical vapor deposition CVD method.
Referring to fig. 17, step S11: an insulating layer II 7 is prepared on the supporting layer 6 by adopting a chemical vapor deposition CVD method.
Referring to fig. 18, step S12: a step structure layer 8 with stress relief is prepared on top of the insulating layer ii 7.
Referring to fig. 19, step S13: and preparing a heating layer 9 on the surface of the composite structure comprising the supporting layer 6, the insulating layer II 7 and the step structure layer 8, wherein the heating layer 9 covers the upper surface of the electrode column 4.
Referring to fig. 20, step S14: a passivation layer 10 is prepared on the heating layer 9.
Referring to fig. 21, step S15: and releasing the sacrificial layer 5 by adopting an isotropic wet etching or dry etching method to form a cavity 12, so as to manufacture the micro-heater with the integrated CMOS and MEMS thermal film structure.
The method further comprises the following steps: before the first step, the upper CMOS or ASIC circuit 1 is boiled for 10 to 30 minutes by concentrated sulfuric acid, then the upper CMOS or ASIC circuit 1 is cleaned by solution such as deionized water, and then is dried by nitrogen.
In order to ensure a good heat insulation effect, the thickness of the porous silicon layer in the first step is 10-100 μm, preferably 100 μm; the porosity is 50% -90%, preferably 50%; the preparation method adopts a wet etching method.
In step S12, when the step structure layer 8 is prepared, the step structure layer 8 falls in the area right above the insulating layer ii 7, and the step structure can more stably support the heating layer 9, so that relatively large stress generated when the device is subjected to shock collision or abrupt temperature change is effectively slowed down, and cracking is prevented.
In order to ensure safety, a passivation layer 10 is disposed on the heating layer 9, and the passivation layer 10 is prepared in step S14 by the following method: a layer of silicon nitride SiN is deposited on the heating layer 9 by magnetron sputtering, which may have a thickness of 50nm to 3 μm, preferably 100nm to 2 μm.
Preferably, the passivation layer 10 may also be silicon oxide SiO 2/polyimide PI.
The method for preparing the cavity 12 in step S15 is isotropic wet etching or dry etching, where the method for dry etching specifically includes: the position and shape of the cavity 12 are defined by using photoresist as a mask layer, and then the cavity 12 is manufactured by using an isotropic wet etching or dry etching process.
5. Knot (S)
The invention has the following characteristics and advantages:
1. heating structure of surface silicon preparation technology: simple process and good properties.
2. Sacrificial polyimide PI/silicon oxide SiO 2 or silicon nitride SIN or amorphous silicon a-Si or polysilicon poly-Si or metal Cu or metal Al: the technology is mature, and the etching process is simple.
3. Step-by-step coating technology: the height of the electrode column (Al column) is increased by step sputtering/vapor plating, and the preparation limit height of the single-layer electrode column (Al column) is broken through, so that the electrical conductivity is increased, and the yield is improved.
4. Step structure layer: the thin film structure with the step shape can release stress, has the spring-like effect in the heating process, and can increase the strength of the heater.
5. The small-sized heating structure enables the small-sized electronic nose array to be realized.
Design of a supporting layer and a heat insulation layer at the bottom of the heating layer: the strength of the film is increased, and the film is thermally isolated.
And (3) a heating layer: taAlN or polysilicon poly-Si/W/TiN/Mo/Pt, etc.
6. CMOS and MEMS structure monolithic heating: the device has small volume, low power consumption and high integration level, can directly output digital signals, and can realize large-scale array.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments is modified or some or all of the technical features are replaced equivalently, so that the essence of the corresponding technical scheme does not deviate from the scope of the technical scheme of the embodiments of the present invention.
Claims (7)
1. A method of fabricating a monolithically integrated CMOS plus MEMS micro-heater comprising the steps of:
step S1: preparing a thermal insulation layer (2) on the prepared CMOS or ASIC circuit (1), and opening an opening of a pad on the CMOS for connection with an electrode pillar (4) on the thermal insulation layer (2) using dry etching;
Step S2, preparing an insulating layer I (3) on the insulating layer (2), and opening an opening of a pad on the CMOS for connecting with the electrode pillar (4) on the insulating layer I (3) by using dry etching;
Step S3: coating a first photoresist layer (51) required for the first Al layer (41) and patterning;
Step S4: evaporating or sputtering a first Al layer (41);
step S5: preparing a first layer of electrode columns through a lift-off process;
step S6: coating a second photoresist layer (52) required for the second Al layer (42) and patterning;
step S7, evaporating or sputtering a second Al layer (42);
Step S8: preparing a second layer of electrode columns through a lift-off process, and preparing the final required electrode columns (4);
step S9, preparing a sacrificial layer (5) on the surface of the silicon substrate containing the electrode column of the step S8;
step S10: preparing a supporting layer (6) on the surfaces of the electrode posts (4) and the sacrificial layer (5) by adopting a Chemical Vapor Deposition (CVD) method;
Step S11: preparing an insulating layer II (7) on the supporting layer (6) by adopting a Chemical Vapor Deposition (CVD) method;
Step S12: preparing a step structure layer (8) with stress release on the insulating layer II (7);
step S13: preparing a heating layer (9) on the surface of the composite structure comprising the supporting layer (6), the insulating layer II (7) and the step structure layer (8), wherein the heating layer (9) covers the upper surface of the electrode column (4);
step S14: preparing a passivation layer (10) on the heating layer (9);
step S15: and releasing the sacrificial layer (5) by adopting an isotropic wet etching or dry etching method to form a cavity (12) so as to manufacture the micro-heater with the integrated CMOS and MEMS thermal film structure.
2. The method of manufacturing a monolithically integrated CMOS plus MEMS micro-heater according to claim 1, wherein the sacrificial layer (5) material is: polyimide (PI) or silicon oxide (SiO 2) or silicon nitride (SiN) or amorphous silicon (a-Si) or polysilicon (poly-Si) or metallic Cu or metallic Al.
3. A monolithically integrated CMOS plus MEMS micro-heater, the integrated CMOS plus MEMS thermal film structured micro-heater comprising: a heat insulating layer (2) and an insulating layer I (3) formed on the upper surface of the CMOS or ASIC circuit (1), and openings for the pad connected with the electrode column (4) are etched on the heat insulating layer (2) and the insulating layer I (3) in a dry mode; an electrode pillar (4) formed on the surface of the insulating layer I (3); a cavity (12) and a suspended heating structure are formed between the electrode columns; the heating structure comprises a supporting layer (6), an insulating layer II (7), a step structure layer (8), a heating layer (9) and a passivation layer (10) from the position of the cavity to the upper part in sequence; wherein the insulating layer II (7) covers the supporting layer (6); the step structure layer (8) is positioned in the area right above the insulating layer II (7); the heating layer (9) is covered on the composite structure comprising the supporting layer (6), the insulating layer II (7) and the step structure layer (8) and covers the upper surface of the electrode column (4); a passivation layer (10) covers the heating layer (9); the insulating layer I (3), the electrode column (4) and the supporting layer (6) jointly form a cavity (12) of the micro heater with the integrated CMOS and MEMS thermal film structure, and the micro heater is in a suspended structure;
The step depth of the step structure layer (8) is 100-1000 nm, the step line width is 1-50 mu m, and the step gap width is 0.5-50 mu m;
The material of the supporting layer (6) is porous silicon or silicon oxide (SiO 2) or ceramic aluminum oxide (Al 2O3), and the thickness is 200 nm-5 mu m; when porous silicon is adopted, the porosity is 50% -90%;
the heating layer (9) is made of TaAlN or polysilicon (poly-Si) or W or TiN or Mo or Pt film, and the thickness is 50-500 nm.
4. A monolithically integrated CMOS and MEMS micro-heater according to claim 3, wherein the heating layer (9) is located in the area directly above the cavity (12), the support layer (6), the insulating layer ii (7) and the step structure layer (8) and covers the upper surface of the electrode pillars (4).
5. Monolithically integrated CMOS and MEMS micro-heater according to claim 3 or 4, wherein the material of the insulating layer (2) is porous silicon with a thickness of 10 μm-100 μm and a porosity of 50% -90%;
The silicon wafer used for preparing the CMOS or ASIC circuit (1) is a monocrystalline silicon wafer with the thickness of 200-500 mu m;
The insulating layer I (3) is made of silicon oxide (SiO 2) with the thickness of 50 nm-2 mu m;
the insulating layer II (7) is made of silicon nitride (SiN) or silicon oxide (SiO 2) or ceramic aluminum oxide (Al 2O3) and has a thickness of 50 nm-500 m.
6. Monolithically integrated CMOS and MEMS micro-heater according to claim 3 or 4, wherein the material of the passivation layer (10) is silicon nitride (SiN) or silicon oxide (SiO 2) or polyimide, with a thickness of 50 nm-3 μm.
7. An electronic nose array prepared by arranging a plurality of monolithically integrated CMOS and MEMS micro-heaters according to any one of claims 3 to 6 on different surface areas of a silicon wafer, each micro-heater being connected to a CMOS or ASIC circuit underneath the micro-heater by electrode pillars and connection pads on the CMOS or ASIC circuit.
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