CN109451317A - A kind of image compression system and method based on FPGA - Google Patents
A kind of image compression system and method based on FPGA Download PDFInfo
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
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- H—ELECTRICITY
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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Abstract
The invention belongs to field of image processings, are related to a kind of image compression system and method based on FPGA, which includes: interactive module, for receiving compression of images request, obtain the image data that image data and output to be compressed have been compressed；Image Acquisition scheduler module is split image data to be compressed, sorts；First cache module, for the image data after the sequence of cache image collection scheduling module segmentation；Compression algorithm module, for being compressed to the image data after segmentation sequence；Second cache module, for caching block of pixels and compressed image data to be compressed.Image compression system based on FPGA of the invention is set in FPGA, and all processes such as segmentation, sequence and compression of image data are completed in FPGA, is realized image compression system using FPGA, is greatly improved compression speed；Compression algorithm is optimized, reduction degree is improved.
Description
Technical field
The invention belongs to field of image processings, are related to a kind of image compression system and method based on FPGA.
Background technique
In recent years, constantly advancing with network technology, network information resource has become extremely abundant, various each
The information of sample is full of around people, announces the arriving of big data era.In order to meet user under limited conditions to net
The demand of network data resource, storing and transmitting again after being compressed to data just becomes to be highly desirable.Data are pressed
When the load of processor can not only be reduced by, which storing and transmitting again after contracting, can also save bandwidth and reduce the transmission of data
Between, improve the surfing of network.
Now, substantially Gzip algorithm used in server is all software realization, and software realization will necessarily occupy one
Partial cpu resource causes the waste of cpu resource unavoidably.Present FPGA (field programmable gate array) technology is sent out rapidly
Exhibition needs the process run on CPU that can be transferred to FPGA originally to realize identical effect, reduces system power dissipation.It is existing
1) technology, which has the following deficiencies:, can not fully rely on FPGA to realize image compression system, other chips is needed to participate in；2) algorithm
Compression ratio is high, but is distorted serious；3) general sram cache is used, memory rate is slower；4) need caching in FPGA multiple whole
Picture causes FPGA resource insufficient.
Summary of the invention
The present invention proposes a kind of image compression system and method based on FPGA to solve the above-mentioned problems, uses FPGA reality
Existing image compression system, greatly improves compression speed, optimizes compression algorithm, improve reduction degree.
To achieve the goals above, the technical scheme is that
A kind of image compression system based on FPGA, including interactive module, Image Acquisition scheduler module, the first caching mould
Block, compression algorithm module and the second cache module,
The interactive module obtains what image data and output to be compressed had been compressed for receiving compression of images request
Image data；
Described image collection scheduling module is for being split image data to be compressed, sorting；
First cache module is for the image data after the sequence of cache image collection scheduling module segmentation；
The compression algorithm module is used to compress the image data after segmentation sequence；
Second cache module is for caching compressed image data.
A kind of image compression system based on FPGA as described above, described image collection scheduling module is by figure to be compressed
As data are divided into multiple block of pixels of 8*8,16*16 or 32*32 pixel, and the pixel arrays A0, A1 that resequences, A2,
A3……An。
A kind of image compression system based on FPGA as described above, the compression algorithm module includes algorithm logic list
Member, read-write cell and format conversion unit, the arithmetic logic unit is for being arranged sample frequency, and the read-write cell is for reading
Image data to be compressed is write, the format conversion unit is used for compressing image data.
A kind of image compression system based on FPGA as described above, the compression algorithm module are adopted again using multiresolution
Sample compression algorithm compresses block of pixels.
A kind of image compression system based on FPGA as described above, first cache module and the second cache module are equal
It is stored using DDR.
A kind of image compression system based on FPGA as described above, described image collection scheduling module every time only segmentation,
Sort an image data, when the image data by compression complete when, then divide, sort next image data.
The invention also discloses a kind of method for compressing image based on FPGA, comprising the following steps:
Interactive module obtains image data to be compressed；
First image data to be compressed is divided, is sorted by Image Acquisition scheduler module；
Block of pixels after the compression segmentation sequence of compression algorithm module；
Second image data that Image Acquisition scheduler module is divided, sorts to be compressed, the compression segmentation of compression algorithm module
The n-th image data that block of pixels ... ... Image Acquisition scheduler module after sequence is divided, sorts to be compressed, compression algorithm mould
Block of pixels after block compression segmentation sequence, until all image datas to be compressed are completed in compression.
A kind of method for compressing image based on FPGA as described above, the interactive module directly interacts with DMA, acquisition to
The image data of compression
A kind of method for compressing image based on FPGA as described above, described image collection scheduling module is by be compressed the
The specific steps that one image data is split, sorts are as follows: Image Acquisition scheduler module is by first picture number to be compressed
According to being divided into multiple block of pixels of 8*8 or 16*16 pixel, and pixel arrays A0, A1, A2, A3 ... An caching of resequencing
In the first cache module, block of pixels A0, A1 of pixel array is read, is cached in the second cache module.
A kind of as described above method for compressing image based on FPGA, the compression algorithm module successively packed pixel block
Specific steps are as follows: compression algorithm module reads block of pixels A0, A1 being cached in the second cache module, is adopted again using multiresolution
Sample compression algorithm carries out packed pixel block, and the second cache module reads the block of pixels of pixel array in the first cache module at this time
A2, A3, and be cached in the second cache module；After compression algorithm module, which is compressed, completes block of pixels A0, A1, by compressed picture
Plain block A0, A1 caching and the second memory module, then read block of pixels A2, A3 being cached in the second cache module and are pressed
Contracting, the second cache module reads the block of pixels ... of pixel array in the first cache module in order at this time, until compression is completed
Whole block of pixels of the image data.
The invention has the benefit that
The present invention solves the case where compression of images occupies excess CPU resources, by the way of directly interacting with DMA, mentions
High transmission rate；Image compression system based on FPGA of the invention is set in FPGA, the segmentation of image data, sequence and
The all processes such as compression are completed in FPGA, are realized image compression system using FPGA, are greatly improved compression speed；It is excellent
Change compression algorithm, improves reduction degree.The present invention also uses pipeline processing mode, keeps whole system work more smooth,
Improve compression speed.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the image compression system of the invention based on FPGA.
Fig. 2 is the flow diagram of the method for compressing image of the invention based on FPGA.
Specific embodiment
In order to clarify the technical characteristics of the invention, below by specific embodiment, and its attached drawing is combined, to this hair
It is bright to be described in detail.According to following embodiments, the present invention may be better understood.However, those skilled in the art is easy
Understand, the following examples are only intended to illustrate the technical solution of the present invention more clearly, and it is of the invention to cannot be used as a limitation limitation
Protection scope.
Fig. 1 is a kind of structural schematic diagram of image compression system based on FPGA.As shown in Figure 1, a kind of based on FPGA's
Image compression system, including interactive module, Image Acquisition scheduler module, the first cache module, compression algorithm module and second are slow
Storing module.
The interactive module is interacted by AXI interface with DMA, for receiving compression of images request, obtains figure to be compressed
The image data compressed as data and output.When needing compressing image data, CPU sends compression of images to interactive module
Request, and image data to be compressed is stored to external DDR, after interactive module receives compression of images request, connection is generated with DMA
System, DMA read image data to be compressed from external DDR, are sent to the compression of images the present invention is based on FPGA by AXI interface
The AXI interface of system, interactive module obtain image data to be compressed.
Described image collection scheduling module is for being split image data to be compressed, sorting.Image Acquisition scheduling
Module calculates image data size to be compressed, and image data to be compressed is divided into the more of 8*8,16*16 or 32*32 pixel
A block of pixels, and pixel arrays A0, A1, A2, A3 ... An that resequences.The quantity of block of pixels are as follows: pixel/(2n*2n).Figure
As only one segmentation, sequence image data every time of collection scheduling module, when the image data is completed by compression, then divides, arranges
The next image data of sequence.
First cache module is for the image data after the sequence of cache image collection scheduling module segmentation.First caching
Module only caches the image data after a segmentation sequence every time.
The compression algorithm module is used to compress the image data after segmentation sequence.Compression algorithm module includes calculating
Method logic unit, read-write cell and format conversion unit, the arithmetic logic unit are used to that sampling number and sample frequency to be arranged,
The read-write cell is used for compressing image data for reading and writing image data to be compressed, the format conversion unit.Compression is calculated
Method module compresses block of pixels using RBC Algorithm compression algorithm.Sample frequency can be total in fpga chip
Line frequency is determined by the hardware and PLL of FPGA board, is arranged by PLL.Sampling number is sampled block of pixels
Number.
Second cache module is for caching image block to be compressed, and the compressed image data of caching.Second
Compressed image data is sent to external DDR by interactive module by cache module.
First cache module and the second cache module are all made of DDR storage, and memory rate is fast.
The image compression system based on FPGA further includes interrupt location, and interrupt location generates interruption before being compressed
It to CPU, notifies when CPU starts compressing image data, obtains the operating rights of DMA, when an image data is completed in compression
Afterwards, it generates and interrupts to CPU, notify there is compressed image data in external DDR in CPU.
The image compression system is realized that general a large amount of image data is stored in external DDR or hard disk by FPGA
In, in FPGA, one or two image data of one acquisition is split, and is divided to image data substep, is entirely being compressed
In the process, primary in image compression system only to cache one or two pictures, FPGA cost is saved, and three-level DDR is divided to store,
The entire image data compression procedure that splits uses multilevel pipelining.
Fig. 2 is a kind of flow diagram of method for compressing image based on FPGA.As shown in Fig. 2, a kind of based on FPGA's
Method for compressing image, comprising the following steps:
S1: interactive module receives compression of images request, obtains image data to be compressed:
The interactive module is interacted by AXI interface with DMA, for receiving compression of images request, obtains figure to be compressed
The image data compressed as data and output.When needing compressing image data, CPU sends compression of images to interactive module
Request, and image data to be compressed is stored to external DDR, after interactive module receives compression of images request, interrupt module to
CPU sends signal, and notice CPU starts compressing image data, obtains the operating rights of DMA, contacts with DMA generation, DMA is from outside
Image data to be compressed is read in DDR, is connect by the AXI that AXI interface is sent to the image compression system the present invention is based on FPGA
Mouthful, interactive module obtains image data to be compressed.
S2: first image data to be compressed is divided, is sorted by Image Acquisition scheduler module:
First image data to be compressed is divided into 8*8,16*16 or 32*32 pixel by Image Acquisition scheduler module
Multiple block of pixels, and pixel arrays A0, A1, A2, A3 ... An that resequences are cached in the first cache module, read pixel
Block of pixels A0, A1 of array is cached in the second cache module.
S3: the block of pixels after the compression segmentation sequence of compression algorithm module:
Compression algorithm module reads block of pixels A0, A1 being cached in the second cache module, using RBC Algorithm
Compression algorithm carry out packed pixel block, at this time the second cache module read the first cache module in pixel array block of pixels A2,
A3, and be cached in the second cache module；After compression algorithm module, which is compressed, completes block of pixels A0, A1, by compressed pixel
Then block A0, A1 caching and the second memory module read block of pixels A2, A3 being cached in the second cache module and are compressed,
The second cache module reads the block of pixels ... of pixel array in the first cache module in order at this time, until the figure is completed in compression
As whole block of pixels of data.Compressed image data is sent to external DDR by interactive module by the second cache module.
It after the image data is completed in compression, generates and interrupts to CPU, notify there is compressed figure in external DDR in CPU
As data.
S4: second image data that Image Acquisition scheduler module is divided, sorts to be compressed, the compression point of compression algorithm module
The n-th image data that block of pixels ... ... Image Acquisition scheduler module after cutting sequence is divided, sorts to be compressed, compression algorithm
Block of pixels after module compression segmentation sequence, until all image datas to be compressed are completed in compression.
Image data after the completion of all compressions is deposited in external DDR, waiting for CPU operation.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please, the protection scope of the application can not be limited with this.All equivalent change or modifications done according to the application Spirit Essence, all
It should contain in the protection scope of lid the application.
Claims (10)
1. a kind of image compression system based on FPGA, which is characterized in that including interactive module, Image Acquisition scheduler module,
One cache module, compression algorithm module and the second cache module,
The interactive module obtains the image that image data and output to be compressed have been compressed for receiving compression of images request
Data；
Described image collection scheduling module is for being split image data to be compressed, sorting；
First cache module is for the image data after the sequence of cache image collection scheduling module segmentation；
The compression algorithm module is used to compress the image data after segmentation sequence；
Second cache module is for caching compressed image data.
2. a kind of image compression system based on FPGA as described in claim 1, which is characterized in that described image collection scheduling
Image data to be compressed is divided into multiple block of pixels of 8*8,16*16 or 32*32 pixel, and pixel of resequencing by module
Array A0, A1, A2, A3 ... An.
3. a kind of image compression system based on FPGA as described in claim 1, which is characterized in that the compression algorithm module
Including arithmetic logic unit, read-write cell and format conversion unit, the arithmetic logic unit is described for sample frequency to be arranged
Read-write cell is used for compressing image data for reading and writing image data to be compressed, the format conversion unit.
4. a kind of image compression system based on FPGA as claimed in claim 3, which is characterized in that the compression algorithm module
Block of pixels is compressed using RBC Algorithm compression algorithm.
5. a kind of image compression system based on FPGA as described in claim 1, which is characterized in that first cache module
DDR storage is all made of with the second cache module.
6. a kind of image compression system based on FPGA as described in claim 1, which is characterized in that described image collection scheduling
Module every time only divide, sort an image data, when the image data by compression complete when, then divide, sort next figure
As data.
7. a kind of method for compressing image based on FPGA, which comprises the following steps:
Interactive module obtains image data to be compressed；
First image data to be compressed is divided, is sorted by Image Acquisition scheduler module；
Block of pixels after the compression segmentation sequence of compression algorithm module；
Second image data that Image Acquisition scheduler module is divided, sorts to be compressed, the compression segmentation sequence of compression algorithm module
The n-th image data that block of pixels ... ... Image Acquisition scheduler module afterwards is divided, sorts to be compressed, compression algorithm module pressure
The block of pixels after sequence is cut in division, until all image datas to be compressed are completed in compression.
8. a kind of method for compressing image based on FPGA as claimed in claim 7, which is characterized in that the interactive module is direct
It is interacted with DMA, obtains image data to be compressed.
9. a kind of method for compressing image based on FPGA as claimed in claim 7, which is characterized in that described image collection scheduling
The specific steps that first image data to be compressed is split, is sorted by module are as follows: Image Acquisition scheduler module will be wait press
First image data of contracting is divided into multiple block of pixels of 8*8 or 16*16 pixel, and the pixel arrays A0, A1 that resequences,
A2, A3 ... An are cached in the first cache module, read block of pixels A0, A1 of pixel array, are cached in the second cache module
In.
10. a kind of method for compressing image based on FPGA as claimed in claim 9, which is characterized in that the compression algorithm mould
The specific steps of block successively packed pixel block are as follows: compression algorithm module read the block of pixels A0 being cached in the second cache module,
A1 carries out packed pixel block using RBC Algorithm compression algorithm, and the second cache module reads the first cache module at this time
Block of pixels A2, A3 of middle pixel array, and be cached in the second cache module；It is compressed when compression algorithm module and completes block of pixels
After A0, A1, by compressed block of pixels A0, A1 caching and the second memory module, then reads and be cached in the second cache module
Block of pixels A2, A3 compressed, the second cache module reads the pixel of pixel array in the first cache module in order at this time
Block ..., until whole block of pixels of the image data are completed in compression.
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| CN111665756A (en) * | 2020-06-11 | 2020-09-15 | 合肥悦芯半导体科技有限公司 | Method and device for realizing sampling of asynchronous signals based on FPGA (field programmable Gate array), electronic equipment and readable storage medium |
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Application publication date: 20190308 |