CN109450616A - A method of improving SM4 Encryption Algorithm speed - Google Patents
A method of improving SM4 Encryption Algorithm speed Download PDFInfo
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- CN109450616A CN109450616A CN201811463847.8A CN201811463847A CN109450616A CN 109450616 A CN109450616 A CN 109450616A CN 201811463847 A CN201811463847 A CN 201811463847A CN 109450616 A CN109450616 A CN 109450616A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Storage Device Security (AREA)
Abstract
The present invention relates to a kind of method for improving SM4 Encryption Algorithm speed, technical characterstic be include: that 128 keys are converted into 32 round key, prepare the plaintext of encryption with when time round key 128 plaintexts of box do exclusive or and generate；The S box that aes algorithm is simulated using the S box of SM4 Encryption Algorithm will be converted in plain text；Transformed plaintext is converted to the ciphertext of generation 128 through T.The present invention has rational design, it utilizes the characteristic of intel instruction collection, by the S box of the S box simulation SM4 Encryption Algorithm of AES encryption algorithm, realize that SM4 Encryption Algorithm uses the function of Intel's AES instruction set, improve the encryption performance and processing speed of SM4 Encryption Algorithm, the performance of the close SM4 of state can be improved conscientiously under the scene for not being available encrypted card, it can extensive high-performance business scope.
Description
Technical field
The invention belongs to data confidential technique field, especially a kind of method for improving SM4 Encryption Algorithm speed.
Background technique
With the popularization of Chinese security strategy, it is widely used in respectively by the close SM4 Encryption Algorithm of the state of Chinese independent development
The security fields of a industry.But since optimization processing is not done in instruction set to SM4 Encryption Algorithm by CPU manufacturer, especially exist
On the highest Intel processors of occupation rate of market, SM4 Encryption Algorithm is all based on the soft realization of C language progress, realizes speed
Degree is slower, slower using other implementation method speed, and therefore, the encryption performance of SM4 is having high performance application scenarios performance
It is barely satisfactory.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, propose a kind of method for improving SM4 Encryption Algorithm speed,
Its encryption performance for improving SM4 Encryption Algorithm using the method for emulation transformation using the characteristic of intel instruction collection.
The present invention solves its technical problem and adopts the following technical solutions to achieve:
A method of improving SM4 Encryption Algorithm speed, comprising the following steps:
128 keys are converted into 32 round key by step 1, are prepared with when time round key 128 plaintexts of box do exclusive or and generate
The plaintext of encryption；
Step 2, the S box that aes algorithm is simulated using the S box of SM4 Encryption Algorithm, will be converted in plain text；
Step 3, the ciphertext that transformed plaintext is converted to generation 128 through T.
The concrete methods of realizing of the step 2 the following steps are included:
(1) converted using following multiple wire system, carry out SM4 Encryption Algorithm S box to AES encryption algorithm S box conversion:
SM4-S (x)=A2 (AES-S (A1 (x)))
A1 (x)=M1*x+C1
A2 (x)=M2*x+C2
In above-mentioned formula, C1, C2 are two 8 bit constants；M1, M2 are the binary constant matrix of two 8*8 respectively；
(2) the conversion of byte to byte is carried out using intel instruction collection aesenclast, the byte after being converted.
T in the step 3 is transformed to the linear transformation based on displacement.
The advantages and positive effects of the present invention are:
The present invention has rational design, utilizes the characteristic of intel instruction collection, by the S box simulation SM4 encryption of AES encryption algorithm
The S box of algorithm realizes that SM4 Encryption Algorithm uses the function of Intel's AES instruction set, improves the encryption of SM4 Encryption Algorithm
Energy and processing speed, can improve the performance of the close SM4 of state conscientiously under the scene for not being available encrypted card, can extensive high-performance industry
Business field.
Detailed description of the invention
Fig. 1 is process flow diagram of the invention；
Fig. 2 is the process flow diagram of S box transformation of the invention.
Specific embodiment
The embodiment of the present invention is further described below in conjunction with attached drawing.
A method of SM4 Encryption Algorithm speed being improved, as shown in Figure 1, comprising the following steps:
128 keys are converted into 32 round key by step 1, are prepared with when time round key 128 plaintexts of box do exclusive or and generate
The plaintext of encryption.
Step 2, the S box that aes algorithm is simulated using the S box of SM4 Encryption Algorithm, will be converted in plain text.
The AES instruction set that intel instruction is concentrated is instruction set of the Intel specifically for AES series of cryptographic algorithm optimization.
Exactly because AES has this instruction set, C language bring rate limitation can be jumped out, the performance of Encryption Algorithm is improved.Together
Sample SM4 Encryption Algorithm is also a kind of symmetric encipherment algorithm, it is that the grouping with 128 keys and 128 block sizes is close
Code, SM4 Encryption Algorithm are to carry out nonlinear change based on S box and draw a conclusion.Therefore, in order to use high performance AES instruction
Collection, we use the high property of Intel using affine transformation method and the S box of the S box of SM4 Encryption Algorithm simulation AES encryption algorithm
It can instruct after completing byte replacement, SM4 Encryption Algorithm uses Intel's AES instruction set.Under the conditions of same hardware, SM4 encryption
Algorithm uses speed after Intel's AES instruction set at least to realize 3 times of raising or more than pure C.
As shown in Fig. 2, the concrete methods of realizing of this step are as follows:
(1) it is converted using following multiple wire system, byte is converted to AES encryption algorithm through the S box of SM4 Encryption Algorithm before converting
S box:
SM4-S (x)=A2 (AES-S (A1 (x)))
A1 (x)=M1*x+C1
A2 (x)=M2*x+C2
Since the S box of AES and SM4 is fixed, may finally be completed by above-mentioned formula by Factoring Polynomials
Conversion.C1, C2 are two 8 bit constants in above-mentioned formula.M1, M2 are the binary constant matrix of two 8*8 respectively.Therefore we
The S box that can use SM4 Encryption Algorithm simulates the S box of aes algorithm.
(2) conversion of byte to byte is carried out using intel instruction collection aesenclast, the byte after being converted.
Aesenclast, which belongs to AES instruction set, to improve the speed of byte replacement in instruction level, improve SM4 to realize
The purpose of algorithm.
Step 3, the T after the transformation of S box by some column convert (fixed linear based on displacement converts) and ultimately generate
128 ciphertexts.
By above-mentioned treatment process, the encryption performance function that SM4 Encryption Algorithm is improved using intel instruction collection is realized.
The process of decryption is exactly the inverse operation of ciphering process, and processing mode is similar, and only round key is carried out using sequence
It is reverse.
It is emphasized that embodiment of the present invention be it is illustrative, without being restrictive, therefore packet of the present invention
Include and be not limited to embodiment described in specific embodiment, it is all by those skilled in the art according to the technique and scheme of the present invention
The other embodiments obtained, also belong to the scope of protection of the invention.
Claims (3)
1. a kind of method for improving SM4 Encryption Algorithm speed, it is characterised in that the following steps are included:
128 keys are converted into 32 round key by step 1, prepare encryption with when time round key 128 plaintexts of box do exclusive or and generate
Plaintext；
Step 2, the S box that aes algorithm is simulated using the S box of SM4 Encryption Algorithm, will be converted in plain text；
Step 3, the ciphertext that transformed plaintext is converted to generation 128 through T.
2. a kind of method for improving SM4 Encryption Algorithm speed according to claim 1, it is characterised in that: the step 2
Concrete methods of realizing the following steps are included:
(1) converted using following multiple wire system, carry out SM4 Encryption Algorithm S box to AES encryption algorithm S box conversion:
SM4-S (x)=A2 (AES-S (A1 (x)))
A1 (x)=M1*x+C1
A2 (x)=M2*x+C2
In above-mentioned formula, C1, C2 are two 8 bit constants；M1, M2 are the binary constant matrix of two 8*8 respectively；
(2) the conversion of byte to byte is carried out using intel instruction collection aesenclast, the byte after being converted.
3. a kind of method for improving SM4 Encryption Algorithm speed according to claim 1, it is characterised in that: in the step 3
T be transformed to the linear transformation based on displacement.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811463847.8A CN109450616A (en) | 2018-12-03 | 2018-12-03 | A method of improving SM4 Encryption Algorithm speed |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811463847.8A CN109450616A (en) | 2018-12-03 | 2018-12-03 | A method of improving SM4 Encryption Algorithm speed |
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| CN201811463847.8A Pending CN109450616A (en) | 2018-12-03 | 2018-12-03 | A method of improving SM4 Encryption Algorithm speed |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111526003A (en) * | 2020-04-09 | 2020-08-11 | 北京理工大学 | Data encryption method and device, storage medium and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160094340A1 (en) * | 2014-09-26 | 2016-03-31 | Intel Corporation | Instructions and logic to provide simd sm4 cryptographic block cipher functionality |
| CN105490802A (en) * | 2015-11-27 | 2016-04-13 | 桂林电子科技大学 | Improved SM4 parallel encryption and decryption communication method based on GPU (Graphics Processing Unit) |
| CN105515758A (en) * | 2015-11-27 | 2016-04-20 | 桂林电子科技大学 | Data parallel cryptographic communication method and system based on Modbus protocol |
-
2018
- 2018-12-03 CN CN201811463847.8A patent/CN109450616A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160094340A1 (en) * | 2014-09-26 | 2016-03-31 | Intel Corporation | Instructions and logic to provide simd sm4 cryptographic block cipher functionality |
| CN105490802A (en) * | 2015-11-27 | 2016-04-13 | 桂林电子科技大学 | Improved SM4 parallel encryption and decryption communication method based on GPU (Graphics Processing Unit) |
| CN105515758A (en) * | 2015-11-27 | 2016-04-20 | 桂林电子科技大学 | Data parallel cryptographic communication method and system based on Modbus protocol |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111526003A (en) * | 2020-04-09 | 2020-08-11 | 北京理工大学 | Data encryption method and device, storage medium and electronic equipment |
| CN111526003B (en) * | 2020-04-09 | 2021-08-27 | 北京理工大学 | Data encryption method and device, storage medium and electronic equipment |
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Application publication date: 20190308 |
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