CN109448779B - SI (service interface) testing method and device of Dual Port SSD (solid State disk) - Google Patents
SI (service interface) testing method and device of Dual Port SSD (solid State disk) Download PDFInfo
- Publication number
- CN109448779B CN109448779B CN201811353645.8A CN201811353645A CN109448779B CN 109448779 B CN109448779 B CN 109448779B CN 201811353645 A CN201811353645 A CN 201811353645A CN 109448779 B CN109448779 B CN 109448779B
- Authority
- CN
- China
- Prior art keywords
- clock
- target
- dual port
- test
- riser card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000009977 dual effect Effects 0.000 title claims abstract description 95
- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 239000007787 solid Substances 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000004891 communication Methods 0.000 claims abstract description 11
- 238000010998 test method Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 32
- 230000008878 coupling Effects 0.000 claims description 29
- 238000010168 coupling process Methods 0.000 claims description 29
- 238000005859 coupling reaction Methods 0.000 claims description 29
- 238000004590 computer program Methods 0.000 claims description 11
- 230000008054 signal transmission Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000003985 ceramic capacitor Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The application discloses an SI test method, device, medium and equipment of a Dual Port SSD, wherein the method comprises the following steps: leading out a first clock and a second clock on a controller in the target memory by using the target Riser card; the first clock and the second clock in the target Riser card are connected in advance through a wire; and establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card so as to perform SI test on the target Dual Port SSD by using the X4 jig. Obviously, by the method, the target Dual Port SSD can be subjected to SI test by using the lower-price X4 jig, so that the high purchase cost of the X2 jig is saved, and the test cost of the SI test on the Dual Port SSD is greatly reduced.
Description
Technical Field
The invention relates to the technical field of server testing, in particular to an SI testing method, device, medium and equipment of a Dual Port SSD.
Background
With the continuous development of internet technology, the application of SSD (Solid State Disk) is more and more extensive. In the prior art, when a Dual Port SSD is tested for SI (Signal Integrity), the Dual Port SSD can only be tested for SI by using the X2 jig, but the cost of the X2 jig is high, which results in high test cost of the Dual Port SSD, so how to perform SI test on the Dual Port SSD by using a better method to reduce the test cost of SI test on the Dual Port SSD is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides an SI testing method, apparatus, medium and device for a Dual Port SSD, so as to reduce the testing cost of SI testing the Dual Port SSD. The specific scheme is as follows:
an SI test method of a Dual Port SSD, comprising:
leading out a first clock and a second clock on a controller in the target memory by using the target Riser card; the first clock and the second clock in the target Riser card are connected in advance through a wire;
and establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card, so as to perform SI test on the target Dual Port SSD by using the X4 jig.
Preferably, after the process of performing SI test on the target Dual Port SSD by using the X4 jig, the method further includes:
and recording the result of the SI test to judge the signal transmission quality of the Dual Port in the target Dual Port SSD.
Preferably, the length of the trace is 150 +/-10 mils.
Preferably, the method further comprises the following steps:
when the SI test is carried out on the target Dual Port SSD by using the first clock on the controller, a first coupling capacitor on the first clock in the target Riser card is opened, and a second coupling capacitor on the second clock in the target Riser card is closed; wherein, the first coupling capacitor is a capacitor which is added to a first clock in the target Riser card in advance; the second coupling capacitor is a capacitor which is added to a second clock in the target Riser card in advance.
Preferably, the coupling capacitor is a village capacitor.
Preferably, the coupling capacitance is 20 uF.
Correspondingly, the embodiment of the invention also discloses an SI testing device of the Dual Port SSD, which comprises the following components:
the signal leading-out module is used for leading out a first clock and a second clock on the controller in the target memory by using the target Riser card; the first clock and the second clock in the target Riser card are connected in advance through a wire;
and the SI testing module is used for establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card, and carrying out SI testing on the target Dual Port SSD by using the X4 jig.
Accordingly, the present invention also discloses a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the SI testing method of Dual Port SSD as disclosed above.
Correspondingly, the invention also discloses an SI test device of the Dual Port SSD, which comprises:
a memory for storing a computer program;
a processor for implementing the steps of the SI test method of the Dual Port SSD as disclosed above when executing said computer program.
It can be seen that, in the present invention, the first clock and the second clock in the target Riser card are connected in advance through the routing, that is, the first clock and the second clock are combined, then two clocks in the controller can be led out through the target Riser card, when the target Riser card is used to establish the communication connection between the X4 fixture and the controller in the target memory, the Dual Port in the target Dual Port SSD can be SI tested through the X4 fixture, obviously, by the method of the present invention, the SI test can be performed on the Dual Port in the target Dual Port only by routing the first clock and the second clock in the target Riser card, and the SI test can be performed on the Dual Port in the target Dual Port by using the X4 fixture with a lower price, so that the test cost for SI test on the Dual Port is greatly reduced compared with the X2 fixture with a higher price in the prior art. Correspondingly, the SI testing device, the medium and the equipment of the Dual Port SSD have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart of an SI test method of a Dual Port SSD according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an SI test performed on a Dual Port SSD according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a first clock and a second clock connected by a trace on a target Riser card according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a coupling capacitor arranged on a target Riser card according to an embodiment of the present invention;
FIG. 5 is a block diagram of an SI testing apparatus of a Dual Port SSD according to an embodiment of the present invention;
fig. 6 is a structural diagram of an SI test apparatus of a Dual Port SSD according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, when the Dual Port SSD is SI tested, the Dual Port SSD can only be SI tested by using the X2 jig, but the X2 jig is expensive in manufacturing cost, which results in high testing cost of the Dual Port SSD. The invention aims to provide another method for SI test of the Dual Port SSD, so as to reduce the test cost of SI test of the Dual Port SSD. For a better understanding of the present invention, those skilled in the art will now make a detailed description of the present invention with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an embodiment of the present invention discloses an SI testing method for a Dual Port SSD, which includes:
step S11: leading out a first clock and a second clock on a controller in the target memory by using the target Riser card;
the first clock and the second clock in the target Riser card are connected in advance through a wire;
step S12: and establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card so as to perform SI test on the target Dual Port SSD by using the X4 jig.
It should be noted that, for any type of memory, a controller, a middle backplane and other board cards are usually disposed inside the memory, and in practical applications, the SSD is generally connected to the middle backplane of the memory through a Riser card (adapter card) to implement communication of the test signal.
As shown in fig. 2, which is a schematic structural diagram of connecting an SSD with a controller and a middle-back board through a Riser card, in fig. 2, a first clock and a second clock in the controller can be used to test the signal integrity of a Port in the SSD, in practical application, an X4 fixture can only lead out one clock in the controller, and a Dual Port SSD has two clocks, so that an X4 fixture cannot be used to perform an SI test on a Dual Port SSD.
In this embodiment, in order to solve this technical problem, a redesigned target Riser card is provided, as shown in fig. 3, in the target Riser card, a first clock and a second clock of the Riser card are connected in advance through a wire, and obviously, the purpose of this operation is to combine the first clock and the second clock in the target Riser card. It is contemplated that the first clock and the second clock on the controller in the target memory may be brought out using the target Riser card after the first clock and the second clock in the Riser card are connected together using the traces.
Moreover, after the target Riser card is used to establish communication connection between the X4 jig and the first clock and the second clock on the controller, the second clock in the controller can be connected to the X4 jig through the pin of the first clock in the controller, so that the Dual Port in the Dual Port SSD can be SI tested by using the X4 jig. Obviously, by the method in the embodiment, SI test can be performed on the Dual Port in the Dual Port SSD without purchasing an X2 jig, thereby significantly reducing the test cost for performing SI test on the Dual Port SSD.
In addition, the testing method provided by the embodiment is simple and easy to implement, a tester does not need to learn new testing skills additionally, and the SSD is not needed to be distinguished from the X4 type or the X2 type in the testing process, so that the testing experience of the tester is greatly improved.
It can be seen that, in this embodiment, a connection is established between the first clock and the second clock in the target Riser card in advance through the routing, that is, the first clock and the second clock are combined, then two ways of clocks in the controller can be led out through the target Riser card, and when the X4 jig is used to establish a communication connection with the controller in the target memory by using the target Riser card, an SI test can be performed on a Dual Port in the target Dual Port SSD through the X4 jig.
Based on the above embodiments, the present embodiment further describes and optimizes the above embodiments, specifically, the steps of: after the process of using the X4 fixture to perform SI test on the target Dual Port SSD, the method further includes:
the results of the SI test are recorded to determine the signal transmission quality of the Dual Port in the target Dual Port SSD.
It is conceivable that, if the signal transmission quality of the Dual Port in the target Dual Port SSD is too poor, the overall operation of the storage server is affected, so in this embodiment, to avoid this, the signal transmission quality of the Dual Port in the target Dual Port SSD is also determined according to the result of the SI test, and if the signal transmission quality of the Dual Port in the target Dual Port SSD is too poor, the use of the target Dual Port SSD in the actual application is avoided, so that unnecessary economic loss can be avoided.
In addition, in practical application, the specific application scenario of the target Dual Port SSD can be selected according to the signal transmission quality of the Dual Port in the target Dual Port SSD, thereby further improving the actual operating efficiency of the storage server.
Based on the above embodiments, the present embodiment further describes and optimizes the above embodiments, specifically, the length of the trace is 150 ± 10 mils.
According to measurement in practical application, the first clock and the second clock in the target Riser card are connected through the wires with the length of 150 +/-10 mils, obviously, the wires with the length of 150 +/-10 mils cannot influence the signal transmission quality of the target Riser card, and therefore the accuracy of the target Dual Port SSD SI test result can be ensured.
Based on the foregoing embodiments, the present embodiment further describes and optimizes the foregoing embodiments, and specifically, the SI testing method of the Dual Port SSD further includes:
when the first clock on the controller is used for carrying out SI test on the target Dual Port SSD, a first coupling capacitor on the first clock in the target Riser card is opened, and a second coupling capacitor on a second clock in the target Riser card is closed;
the first coupling capacitor is a capacitor which is added to a first clock in the target Riser card in advance; the second coupling capacitance is a capacitance previously added to the second clock in the target Riser card.
It is conceivable that, since the connection of the trace between the target Riser card and the controller may affect the Stub on the SI test result of the target Dual Port SSD, in this embodiment, in order to avoid this, the first coupling capacitor and the second coupling capacitor are added to the first clock and the second clock of the target Riser card in advance, respectively.
As shown in FIG. 4, when the target Dual Port SSD is SI tested with the first clock on the controller, then the first coupling capacitor on the first clock in the target Riser card is turned on and the second coupling capacitor on the second clock in the target Riser card is turned off. Therefore, the influence of the routing from the target Riser card to the controller on the SI test result of the target Dual Port SSD can be avoided. Of course, it is described here by taking an example when the first clock on the controller performs the SI test on the target Dual Port SSD, and if the second clock on the controller is used to perform the SI test on the target Dual Port SSD, the second coupling capacitor on the second clock in the target Riser card may be turned on, and the first coupling capacitor on the first clock in the target Riser card may be turned off, so as to avoid the influence of the trace between the target Riser card and the controller on the SI test result of the target Dual Port SSD. Obviously, the accuracy of the target Dual Port SSD SI test result can be further improved by the method in the embodiment.
In a preferred embodiment, the coupling capacitor is a village capacitor.
In this embodiment, the coupling capacitor is set as a village capacitor, and it can be understood that the village capacitor is a ceramic capacitor, and since no electrolyte is present in the ceramic capacitor, the ceramic capacitor is not only suitable for working at high temperature, but also has a long service life and high accuracy, and during the working process of the ceramic capacitor, defects in an oxide film can be automatically repaired or isolated, so that the insulating capability of the ceramic capacitor can be kept within a stable range.
In a preferred embodiment, the coupling capacitance is 20 uF.
A large number of practical verifications show that when the coupling capacitance is set to be 20uF, the Stub influence of the wiring between the target Riser card and the controller on the target Dual Port SSD SI test result can be avoided, and the test performance of the target Riser card cannot be influenced due to the fact that the set parameter of the coupling capacitance is too large. Therefore, in the present embodiment, the coupling capacitance is set to 20uF, thereby further ensuring the safety performance of the target Dual Port SSD during SI test.
Correspondingly, the embodiment of the invention also discloses an SI testing device of Dual Port SSD, as shown in fig. 5, including:
the signal leading-out module 21 is used for leading out a first clock and a second clock on the controller in the target memory by using the target Riser card; the first clock and the second clock in the target Riser card are connected in advance through a wire;
and the SI test module 22 is used for establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card so as to perform SI test on the target Dual Port SSD by using the X4 jig.
Correspondingly, the embodiment of the invention also discloses a computer readable storage medium, a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to realize the steps of the SI test method of the Dual Port SSD as disclosed in the foregoing.
Correspondingly, the embodiment of the invention also discloses an SI test device of a Dual Port SSD, as shown in fig. 6, comprising:
a memory 31 for storing a computer program;
a processor 32 for implementing the steps of the SI test method of the Dual Port SSD as disclosed above when executing the computer program.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The SI testing method, device, medium and apparatus of Dual Port SSD provided by the present invention are introduced in detail, and a specific example is applied in the text to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. An SI test method of a Dual Port SSD, comprising:
leading out a first clock and a second clock on a controller in the target memory by using the target Riser card; a first clock and a second clock in the target Riser card are connected in advance through a routing so as to combine the first clock and the second clock;
and establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card, so as to perform SI test on the target Dual Port SSD by using the X4 jig.
2. The SI test method of claim 1, wherein after the process of SI test of the target Dual Port SSD by the X4 jig, further comprising:
and recording the result of the SI test to judge the signal transmission quality of the Dual Port in the target Dual Port SSD.
3. The SI testing method of claim 1, wherein the length of the trace is 150 ± 10 mil.
4. The SI test method of any of claims 1 to 3, further comprising:
when the SI test is carried out on the target Dual Port SSD by using the first clock on the controller, a first coupling capacitor on the first clock in the target Riser card is opened, and a second coupling capacitor on the second clock in the target Riser card is closed; wherein, the first coupling capacitor is a capacitor which is added to a first clock in the target Riser card in advance; the second coupling capacitor is a capacitor which is added to a second clock in the target Riser card in advance.
5. The SI test method of claim 4, wherein the coupling capacitor is a village capacitor.
6. The SI testing method of claim 4, wherein the coupling capacitance is 20 uF.
7. An SI test device of a Dual Port SSD, comprising:
the signal leading-out module is used for leading out a first clock and a second clock on the controller in the target memory by using the target Riser card; a first clock and a second clock in the target Riser card are connected in advance through a routing so as to combine the first clock and the second clock;
and the SI testing module is used for establishing communication connection between the X4 jig and a first clock and a second clock on the controller by using the target Riser card so as to perform SI testing on the target Dual Port SSD by using the X4 jig.
8. A computer-readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, carries out the steps of the SI testing method of a Dual Port SSD according to any of the claims 1 to 6.
9. An SI test device for a Dual Port SSD, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the SI testing method of a Dual Port SSD, as claimed in any of claims 1 to 6, when executing said computer program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811353645.8A CN109448779B (en) | 2018-11-14 | 2018-11-14 | SI (service interface) testing method and device of Dual Port SSD (solid State disk) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811353645.8A CN109448779B (en) | 2018-11-14 | 2018-11-14 | SI (service interface) testing method and device of Dual Port SSD (solid State disk) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109448779A CN109448779A (en) | 2019-03-08 |
| CN109448779B true CN109448779B (en) | 2020-11-20 |
Family
ID=65552542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811353645.8A Active CN109448779B (en) | 2018-11-14 | 2018-11-14 | SI (service interface) testing method and device of Dual Port SSD (solid State disk) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109448779B (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201214456A (en) * | 2010-09-27 | 2012-04-01 | Jmicron Technology Corp | Solid-state disk with automated testing capability and automated testing method of solid-state disk |
| US10803970B2 (en) * | 2011-11-14 | 2020-10-13 | Seagate Technology Llc | Solid-state disk manufacturing self test |
| US20130311696A1 (en) * | 2012-05-18 | 2013-11-21 | Lsi Corporation | Storage processor for efficient scaling of solid state storage |
| US9430412B2 (en) * | 2013-06-26 | 2016-08-30 | Cnex Labs, Inc. | NVM express controller for remote access of memory and I/O over Ethernet-type networks |
| CN104021107A (en) * | 2014-06-27 | 2014-09-03 | 浪潮电子信息产业股份有限公司 | Design method for system supporting non-volatile memory express peripheral component interface express solid state disc (NVMe PCIE SSD) |
| WO2017195324A1 (en) * | 2016-05-12 | 2017-11-16 | 株式会社日立製作所 | Storage device |
| CN107704344A (en) * | 2017-09-14 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of full flash memory system of dual control based on NVMe |
| CN107943730A (en) * | 2017-12-06 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of system for supporting NVMe agreement PCIE signals |
-
2018
- 2018-11-14 CN CN201811353645.8A patent/CN109448779B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109448779A (en) | 2019-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111579972B (en) | Service life detection method for PCBA board-level component | |
| CN103367189A (en) | Test system and test method thereof | |
| CN103207366A (en) | Test system and test method of printed circuit board assembly | |
| CN112345982B (en) | Circuit element welding condition detection method and device | |
| CN109470974A (en) | A kind of testing lines system and method based on wireless technology | |
| CN202649371U (en) | Cable automatic detection device | |
| CN109448779B (en) | SI (service interface) testing method and device of Dual Port SSD (solid State disk) | |
| CN103760388A (en) | Four-wire test fixture and test method thereof | |
| US20120217977A1 (en) | Test apparatus for pci-e signals | |
| CN102692525A (en) | An assistant testing device for PCI card | |
| CN115356527A (en) | Fault detection method, device and equipment | |
| CN105425094A (en) | Short-circuit point detection method and apparatus of PCBA | |
| US20180136270A1 (en) | Product self-testing method | |
| EP1710593A2 (en) | Process for the preparation and automatic performance of sequence of measurements and tests on an electrical installation | |
| CN105652088B (en) | The test device of external interface contact impedance | |
| CN204302384U (en) | The testing arrangement of external interface contact impedance | |
| CN114706718A (en) | PCIe signal integrity verification method, device, equipment and medium | |
| CN209560007U (en) | A kind of testing lines system based on wireless technology | |
| CN211123130U (en) | Withstand voltage testing device | |
| CN113704152A (en) | PCIe slot interface switching equipment, test equipment, system and method | |
| US9360524B2 (en) | Testing system for serial interface | |
| CN113945826A (en) | Electronic board card testing method and device and medium | |
| CN103852675A (en) | On-line test fixture with pneumatic probes | |
| US20090256582A1 (en) | Test circuit board | |
| CN117310454B (en) | Chip testing method and related device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20201030 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 450018 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |