CN109425803B - Analog quantity disconnection fault detection method, system and acquisition device - Google Patents
Analog quantity disconnection fault detection method, system and acquisition device Download PDFInfo
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Abstract
The invention provides a method, a system and a collection device for detecting an analog quantity disconnection fault, which are used for generating a fault analog signal, carrying out analog-to-digital conversion on an input signal and the fault analog signal of each analog quantity channel and collecting data after the analog-to-digital conversion of each analog quantity channel at a set sampling frequency; and reading the converted data, taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog channel meets a set condition, comparing the difference of the sampling data of each analog channel with the reference value by using the set condition value, comparing the difference of the data acquired by the same analog-to-digital conversion channel of two adjacent samplings, and judging that the analog channel has the broken line fault if the difference obtained by the difference of the two samplings is smaller than the corresponding set value. The invention has strong real-time performance, high detection result accuracy and detection efficiency, reduces the risk of misoperation caused by analog quantity disconnection, and improves the stability and reliability of the operation of the relay protection device.
Description
Technical Field
The invention belongs to the field of relay protection automation of power engineering, and particularly relates to a method, a system and a collecting device for detecting an analog quantity disconnection fault.
Background
With the progress of the times, the rapid development of science and technology, and the great progress of new chip technology and computer network technology, the intellectualization of the automation field of the transformer substation is promoted, and with the emergence of electromechanical integrated equipment such as an intelligent switch, a photoelectric current-voltage transformer and the like, a relay protection device is continuously developed. At present, a relay protection device generally adopts a modular plug-in mode, alternating current transformers are integrated together to form an alternating current transformer plug-in, an AD sampling circuit and a CPU are integrated together to form a sampling and protection plug-in, the alternating current transformer plug-in and the sampling and protection plug-in are connected to a back plate through a connector for interconnection, and in the field of relay protection, an implementation method of alternating current analog quantity sampling mainly connects primary equipment element voltage or current to a secondary protection device after primary alternating current transformer conversion. The secondary AC mutual inductor in the protection device converts the input analog quantity again and then connects the converted analog quantity to the AD chip and the corresponding filter circuit for analog-to-digital conversion, and the converted digital quantity is transmitted to the CPU for operation and application.
However, frequent plugging and unplugging of the plug-in unit can cause abrasion to the connector, some inevitable physical vibration can cause looseness of pins of the alternating current transformer, and the abrasion of the connector and the looseness of the pins of the connector can cause disconnection of an analog quantity transmission link between the alternating current transformer and the acquisition and protection plug-in unit, so that abnormal analog quantity acquisition is caused to influence protection operation. Therefore, whether the analog quantity of the relay protection device is broken needs to be detected, the traditional detection equipment is generally a relay protection tester, the relay protection tester can output current and voltage signals, send out a switching signal and detect an input signal, and a detector compares display values of the relay protection tester and the relay protection device through visual inspection to judge whether the hardware of the relay protection device is good or bad. However, the tester needs to manually and continuously replace the connecting line between the relay protection tester and the relay protection device, and the testing efficiency is low; the evaluation of the test result needs manual evaluation, test items are easy to omit, the test evaluation standard is not easy to be unified, and the test is greatly influenced by human factors.
Disclosure of Invention
The invention aims to provide a method, a system and a collecting device for detecting an analog quantity disconnection fault, which are used for solving the problems of inaccurate detection and low detection efficiency of the analog quantity disconnection fault of a relay protection device in the prior art.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an analog quantity disconnection fault detection method comprises the following steps:
1) generating fault analog signals, performing analog-to-digital conversion on input signals of each analog quantity channel, acquiring data after analog-to-digital conversion of each analog quantity channel at a set sampling frequency, and performing analog-to-digital conversion on the fault analog signals;
2) reading sampling data after analog-to-digital conversion;
3) and taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition is to compare the sampling data of each analog quantity channel with the reference value in a difference mode, compare the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other in a difference mode, and judge that the analog quantity channel has the broken line fault if the difference values obtained by the difference of the two times are smaller than the corresponding set values.
Further, the fault simulation signal is a null shift signal.
Further, when the sampling of the continuous set times meets the set conditions, the analog quantity channel is judged to have the analog quantity disconnection fault.
Furthermore, the set sampling frequency refers to N times of the sampling frequency of the sampling device in normal operation, and N is more than or equal to 3.
The invention also provides an analog quantity disconnection fault detection system which comprises an AD chip, an FPGA, a fault analog signal generation device and analog quantity channels, wherein the AD chip is in communication connection with the FPGA, the fault analog signal generation device is used for generating fault analog signals, the AD chip is used for performing analog-to-digital conversion on input signals of all analog quantity channels, the FPGA sets sampling frequency for the AD chip, the data after the analog-to-digital conversion of all analog quantity channels are acquired by the set sampling frequency, and the sampled data after the analog-to-digital conversion are read; and taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition is to compare the sampling data of each analog quantity channel with the reference value in a difference mode, compare the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other in a difference mode, and judge that the analog quantity channel has the broken line fault if the difference values obtained by the difference of the two times are smaller than the corresponding set values.
Further, the fault simulation signal is a null shift signal.
Further, when the sampling of the continuous set times meets the set conditions, the analog quantity channel is judged to have the analog quantity disconnection fault.
Furthermore, the set sampling frequency refers to N times of the sampling frequency of the sampling device in normal operation, and N is more than or equal to 3.
Furthermore, the analog quantity channel is connected with the AD chip through the pre-filter circuit.
The invention also provides a collecting device, which comprises an AD chip, a CPU, an FPGA, a fault analog signal generating device and an analog quantity input interface, wherein the AD chip is in communication connection with the FPGA, the FPGA is in communication connection with the CPU, the fault analog signal generating device is used for generating a fault analog signal, the analog quantity input interface is used for inputting an analog quantity signal, the AD chip is used for performing analog-to-digital conversion on the input signal of each analog quantity channel, the CPU is used for controlling the FPGA to set a sampling frequency for the AD chip, collecting the data after the analog-to-digital conversion of each analog quantity channel by using the set sampling frequency, and reading the sampling data after the analog-to-digital conversion; the CPU takes the sampling data of the broken line fault analog signal as a reference value to judge whether the sampling data of each analog channel meets a set condition, the set condition refers to that the sampling data of each analog channel is compared with the reference value in a difference mode, the data acquired by the same analog-to-digital conversion channel of two adjacent sampling channels are compared in a difference mode, and if the difference values obtained by the difference of the two sampling channels are smaller than the corresponding set value, the broken line fault of the analog channel is judged to occur.
The invention has the beneficial effects that:
firstly, generating a fault analog signal, performing analog-to-digital conversion on input signals of each analog channel, acquiring data after the analog-to-digital conversion of each analog channel at a set sampling frequency, and performing analog-to-digital conversion on the fault analog signal; then reading sampling data after analog-to-digital conversion of each channel of each sampling; and finally, taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition refers to that the sampling data of each analog quantity channel is subjected to difference comparison with the reference value, the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other are subjected to difference comparison, and if the difference values obtained by the difference comparison twice are smaller than the corresponding set values, judging that the analog quantity channel has the broken line fault of the analog quantity. The invention has the advantages of stronger real-time performance, high detection result accuracy and high detection efficiency, further judges and detects the analog quantity by setting the sampling data of the frequency and the sampling times, reduces the risk of misoperation caused by the broken line of the analog quantity, and improves the stability and the reliability of the operation of the relay protection device.
Drawings
FIG. 1 is a schematic diagram of an analog quantity disconnection fault detection range;
FIG. 2 is a hardware block diagram of the analog quantity disconnection fault real-time diagnosis system of the present invention;
FIG. 3 is a flow chart of an FPGA implementation of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings:
the embodiment of the analog quantity disconnection fault detection system comprises the following steps:
an analog quantity disconnection fault detection system is shown in fig. 2 and comprises an alternating current transformer plug-in unit, a back board and a collection and protection plug-in unit. The acquisition and protection plug-in unit comprises an AD pre-filter circuit, an AD chip, an FPGA, a CPU, a corresponding peripheral circuit and a power supply. The AD chip is in communication connection with the FPGA through an SPI interface, and the FPGA is in communication connection with the CPU through an LBC bus. The alternating current transformer plug-in and the acquisition and protection plug-in realize analog input and output interconnection through the plug-in connector and the back plate. The input analog quantity of the acquisition and protection plug-in is connected to the analog quantity input end of the A/D chip after passing through the AD pre-filter circuit; the CPU is used for controlling the FPGA to set sampling frequency for the AD chip; selecting any one analog-to-digital conversion channel of the AD chip as a disconnection fault simulation channel, and collecting input analog quantity of each analog-to-digital conversion channel of the mutual inductor according to the set sampling frequency and the set collection times; the AD chip realizes the conversion from analog signals to digital signals under the control of the FPGA, stores the conversion result into an internal cache region, and reads the sampling data after analog-to-digital conversion of each channel sampled each time after the set time is met.
As shown in fig. 1, the analog quantity disconnection fault detection range is from the secondary side pin of the plug-in transformer of the alternating current transformer to the plug-in connector of the acquisition and protection, the element 1 is the secondary side pin of the alternating current transformer, the element 2 is the plug-in connector of the alternating current transformer, and the element 3 is the plug-in connector of the acquisition and protection. The element 1, the element 2, and the element 3 constitute an analog disconnection fault detection range.
The design scheme of the pre-filter circuit connected with each sampling channel adopts the same standard as the components, the connectors and the like.
The AD chip selected by the acquisition and protection plug-in is an AD chip with a multi-channel analog-to-digital conversion function. And selecting the first analog-to-digital conversion channel of the AD chip as a fault simulation channel. The fault simulation channels have the same pre-filter circuit but are not connected through connectors and AC transformer plugs. And taking the sampling data of the fault simulation channel as a reference for judging the sampling data of the analog quantity disconnection fault.
The fault simulation channel sampling value is distinguished from the characteristic of the sampling value under the condition that the protection device has no external input: the sampling value of the fault simulation channel is mainly a zero drift value generated under the influence of the pre-filter circuit, and the sampling value is almost 0 under the influence of the load of the AC transformer plug-in unit when no input is made to the external wiring of the device (namely, no input is made to the external wiring of the AC transformer plug-in unit).
Under the control of the CPU, the FPGA multiplies the sampling frequency under the premise of ensuring the sampling frequency required by the protection operation, calculates and preprocesses the sampling data of continuous multiple points, and outputs the diagnosis result of the disconnection fault to the CPU for processing. Specifically, when the CPU performs initialization configuration on the FPGA, the sampling frequency of the AD sampling function module inside the FPGA is set to be N times (N is greater than or equal to 3) of the sampling frequency actually required for normal operation. I.e. if the sampling frequency required for reliable operation of the protection device is 24 points per cycle, the AD actual sampling frequency is at least 72 points per cycle. The sampling data of each point acquired by the CPU is the data after N-point operation and pretreatment.
The method comprises the steps of preprocessing sampled data before transmitting the sampled data to a CPU every time, wherein control of an AD (analog-digital) chip and preprocessing of the sampled data are achieved through an FPGA (field programmable gate array), the parallel operation speed of the FPGA is high, and the data preprocessing capacity under a high sampling frequency is achieved.
The invention relates to an analog quantity disconnection fault diagnosis method, which specifically comprises the following steps:
1) after the system is powered on and the FPGA program is loaded, the CPU starts to perform initialization configuration on an AD sampling function module in the FPGA according to an agreed protocol, such as AD sampling frequency configuration and the like. The AD sampling frequency is configured to be more than 3 times the sampling frequency actually required for the guard operation. If the sampling data required by the protection operation is 24 points per cycle, i.e. the actual required sampling frequency is 1200 points per second, the sampling frequency configured by the CPU to the FPGA is at least 72 points per cycle, i.e. 3600 points per second. The embodiment of the invention sets the actual sampling frequency to be 4 times of the sampling frequency required by the normal operation of the relay protection, namely the sampling frequency is 4800 points per second.
2) And a starting timer is designed in the FPGA, a CONVST signal is output to the AD chip according to the sampling frequency set by the CPU, and the AD chip is started for sampling.
3) And after receiving the starting command, the AD chip performs analog-to-digital conversion on the analog quantities of all the analog-to-digital conversion channels, and the FPGA starts to read the sampling data after the analog-to-digital conversion from the AD chip by taking CONVST as a reference and waiting for time T. The time T is the maximum time required for the AD chip to complete analog-to-digital conversion.
4) And the FPGA starts to read sampling data from the AD chip one by one channel through the SPI interface. In this embodiment, the first analog-to-digital conversion channel of each AD chip is used as a fault simulation channel, and as other embodiments, other analog-to-digital conversion channels may also be selected as a disconnection fault simulation channel. In this embodiment, for example, data obtained after 4 times of analog-to-digital conversion is collected, and R is used for sampling data of a first analog-to-digital conversion channel of the AD chipi(i is 1,2,3,4), and the sampled data of the first analog-to-digital conversion channel of the AD chip is used as the judgment standard of the broken line fault of the analog quantity, and the data sampled by each other analog-to-digital conversion channel is VniAnd representing, wherein i is a sampling sequence number identifier, and n is an identifier of an analog-to-digital conversion channel.
As shown in fig. 3, after reading the data of the rest analog-to-digital conversion channels of the AD chip, the FPGA performs subtraction and absolute value operation with the reference value of the analog disconnection fault, that is, the sampled data of each channel sampled each time is subtracted from the reference value, and then the absolute value is represented as DVRni＝|Vni-RiAnd the difference of the data values of two adjacent samples of the same channel is expressed as DVVni＝|Vni-Vn(i-1)L, the sampled data of the 1 st analog-to-digital conversion channel (the first fault except the fault simulation channel) as sampled at the 1 st time is represented as V11The sampling data of the 1 st analog-to-digital conversion channel at the 1 st sampling is represented as V12And so on. Here, V is the result of the 1 st samplingn(i-1)Has no original data, so DVVni＝|Vni-Vn(i-1)And | calculating from the 2 nd sampling, and saving the calculation result. The FPGA sequentially reads and operates data of each effective analog-to-digital conversion channel, and temporarily stores results in an internal cache region, and the results can be realized by an internal register or Ram of the FPGA. After all channel data are read, the FPGA accumulates the sampling times and waits for the next sampling time to carry out the next samplingAnd (5) sampling and operation of the wheel.
5) After 4 times of accumulated sampling of FPGA, DVR is setniAnd DVVniJudging whether the absolute value of the difference between the two times is less than a set value TsetIf it is less than the set value TsetAnd judging that the analog quantity disconnection fault occurs. If DVRni<TsetI ═ 1,2,3,4, and DVVni<TsetIf both conditions of i ═ {2,3,4} are satisfied, Q is setn1, otherwise QnWhen the channel n is 0, the FPGA samples the data of the 4 th time of the channel n and the corresponding QnFraming according to a communication protocol appointed with the CPU, and transmitting to the CPU for application processing, wherein the data sampled for 1 st, 2 nd and 3 th times is mainly used for judging the analog quantity disconnection fault, namely for calculating and generating Qn, and the requirement of the CPU for protection operation can be met only by uploading the data sampled for 4 th time. If Q isnIf the value is 1, the CPU considers that the analog quantity of the corresponding channel n is broken, locks the channel data and triggers a protection alarm signal.
The FPGA chip and the AD chip of this embodiment are individually selected from Spartan6 series XC6SLX9 of Xilinx corporation and AD7606 of anal og DEVICES corporation, and each AD has 8 channels. For the protection device in the embodiment, the AD7606 nominal sampling range is plus or minus 10V, 16-bit sampling precision, two completely same analog input measurement results have an error within 6 increment ranges, a voltage value represented by each increment is 20V/65536, the performance difference of components used in an actual circuit is considered, the CPU selects the MPC8309 in the Powerpc series, and the interaction between the CPU and the FPGA adopts an interrupt plus query mode.
TsetFor practical detection of error range, the value is determined according to the precision of the selected AD chip, in this embodiment, T is takenset10(LSB), the LSB is the least significant bit. For an AD7606 chip, the analog input nominal range is-10V to +10V, the digital output range after conversion is 0-65535, and then 1LSB is (10V + 10V)/65536. The allowable deviation Tset in the patent is 10, i.e. 10 x (10V +10V)/65536, i.e. 10 LSBs, which is in fact theoretically trueTsetIf the obtained difference value is not 0, it is determined that the analog quantity has not failed to fail, and the set value is set to 10 so as not to cause false determination of the analog quantity disconnection fault, thereby increasing the possibility of correctly determining the analog quantity disconnection fault.
The invention also provides an analog quantity disconnection fault detection method, which comprises the steps of generating a fault analog signal, carrying out analog-to-digital conversion on the input signal of each analog quantity channel, collecting the data after the analog-to-digital conversion of each analog quantity channel at a set sampling frequency, and carrying out analog-to-digital conversion on the fault analog signal; reading sampling data after analog-to-digital conversion; and taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition is to compare the sampling data of each analog quantity channel with the reference value in a difference mode, compare the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other in a difference mode, and judge that the analog quantity channel has the broken line fault if the difference values obtained by the difference of the two times are smaller than the corresponding set values.
The invention also provides a collecting device, which comprises an AD chip, a CPU, an FPGA, a fault analog signal generating device and an analog quantity input interface, wherein the AD chip is in communication connection with the FPGA, the FPGA is in communication connection with the CPU, the fault analog signal generating device is used for generating a fault analog signal, the analog quantity input interface is used for inputting the analog quantity signal, the AD chip is used for performing analog-to-digital conversion on the input signal of each analog quantity channel, the CPU is used for controlling the FPGA to set a sampling frequency for the AD chip, collecting the data after the analog-to-digital conversion of each analog quantity channel by using the set sampling frequency, and reading the sampled data after the analog-to-digital conversion of each channel sampled each time; the CPU takes the sampling data of the broken line fault analog signal as a reference value, judges whether the sampling data of each analog quantity channel meets set conditions, the set conditions refer to that the sampling data of each analog quantity channel is compared with the reference value in a difference mode, the data acquired by the same analog-to-digital conversion channel of two adjacent sampling channels are compared in a difference mode, and if the difference values obtained by the difference of the two times are smaller than the corresponding set values, the analog quantity channel is judged to have the broken line fault.
The analog quantity disconnection fault detection method, the analog quantity disconnection fault detection system and the analog quantity disconnection fault detection device have the advantages of being high in real-time performance, high in detection result accuracy and detection efficiency, further judging and detecting the analog quantity through the sampling data with the set frequency and the set sampling times, reducing the risk of misoperation caused by analog quantity disconnection, and improving the stability and the reliability of operation of a relay protection device.
The specific embodiments are given above, but the present invention is not limited to the above-described embodiments. The basic idea of the present invention lies in the above basic scheme, and it is obvious to those skilled in the art that no creative effort is needed to design various modified models, formulas and parameters according to the teaching of the present invention. Variations, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the invention, and still fall within the scope of the invention.
Claims (10)
1. An analog quantity disconnection fault detection method is characterized by comprising the following steps:
1) generating fault analog signals, performing analog-to-digital conversion on input signals of each analog quantity channel, acquiring data after analog-to-digital conversion of each analog quantity channel at a set sampling frequency, and performing analog-to-digital conversion on the fault analog signals;
2) reading sampling data after analog-to-digital conversion;
3) and taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition is to compare the sampling data of each analog quantity channel with the reference value in a difference mode, compare the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other in a difference mode, and judge that the analog quantity channel has the broken line fault if the difference values obtained by the difference of the two times are smaller than a set value.
2. The analog quantity disconnection fault detection method according to claim 1, wherein the fault analog signal is a null shift signal.
3. The method according to claim 1, wherein when the sampling for the continuous set times satisfies the set condition, it is determined that the analog disconnection fault occurs in the analog channel.
4. The method for detecting the analog quantity disconnection fault according to claim 1, wherein the set sampling frequency is N times of the sampling frequency of the sampling device in normal operation, and N is more than or equal to 3.
5. An analog quantity disconnection fault detection system is characterized by comprising an AD chip, an FPGA, a fault analog signal generation device and analog quantity channels, wherein the AD chip is in communication connection with the FPGA, the fault analog signal generation device is used for generating fault analog signals, the AD chip is used for performing analog-to-digital conversion on input signals of all analog quantity channels, the FPGA sets sampling frequency for the AD chip, the data after the analog-to-digital conversion of all analog quantity channels are collected at the set sampling frequency, and the sampled data after the analog-to-digital conversion are read; and taking the sampling data of the broken line fault analog signal as a reference value, judging whether the sampling data of each analog quantity channel meets a set condition, wherein the set condition is to compare the sampling data of each analog quantity channel with the reference value in a difference mode, compare the data acquired by the same analog-to-digital conversion channel sampled twice adjacent to each other in a difference mode, and judge that the analog quantity channel has the broken line fault if the difference values obtained by the difference of the two times are smaller than a set value.
6. The analog quantity disconnection fault detection system of claim 5, wherein the fault analog signal is a null shift signal.
7. The system according to claim 5, wherein when the sampling for the continuous set times satisfies the set condition, it is determined that the analog disconnection fault occurs in the analog channel.
8. The system for detecting the analog quantity disconnection fault as claimed in claim 5, wherein the set sampling frequency is N times of the sampling frequency of the sampling device in normal operation, and N is more than or equal to 3.
9. The system for detecting the disconnection fault of the analog quantity according to claim 5, further comprising a pre-filter circuit, wherein the analog quantity channel is connected with the AD chip through the pre-filter circuit, the pre-filter circuit is used for generating a null shift value, and the sampling data of the fault analog signal mainly consists of the null shift value.
10. The acquisition device is characterized by comprising an AD chip, a CPU, an FPGA, a fault analog signal generation device and an analog input interface, wherein the AD chip is in communication connection with the FPGA, the FPGA is in communication connection with the CPU, the fault analog signal generation device is used for generating a fault analog signal, the analog input interface is used for inputting an analog signal, the AD chip is used for performing analog-to-digital conversion on input signals of analog channels, the CPU is used for controlling the FPGA to set sampling frequency for the AD chip, acquiring data after analog-to-digital conversion of the analog channels at the set sampling frequency and reading the sampled data after analog-to-digital conversion; the CPU takes the sampling data of the broken line fault analog signal as a reference value to judge whether the sampling data of each analog channel meets a set condition, the set condition refers to that the sampling data of each analog channel is compared with the reference value in a difference mode, the data acquired by the same analog-to-digital conversion channel of two adjacent sampling channels are compared in a difference mode, and if the difference values obtained by the difference of the two sampling channels are smaller than a set value, the analog channel is judged to have the broken line fault.
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