CN109379180A - Aes algorithm implementation method, device and solid state hard disk - Google Patents
Aes algorithm implementation method, device and solid state hard disk Download PDFInfo
- Publication number
- CN109379180A CN109379180A CN201811565309.XA CN201811565309A CN109379180A CN 109379180 A CN109379180 A CN 109379180A CN 201811565309 A CN201811565309 A CN 201811565309A CN 109379180 A CN109379180 A CN 109379180A
- Authority
- CN
- China
- Prior art keywords
- key
- ciphertext
- initial
- encryption
- recyclable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Storage Device Security (AREA)
Abstract
The present invention relates to art of cryptography, a kind of aes algorithm implementation method, device and solid state hard disk are provided, which comprises the initial key according to input carries out InvAddRoundKey to the plaintext of input and obtains initial ciphertext；Round key is carried out according to initial key to handle to obtain first key；The first encryption is carried out according to initial ciphertext and obtains the first ciphertext, wherein the first encryption has N number of clock cycle, and each clock cycle corresponds to M recyclable interative computation, wherein N is the positive integer that the positive integer greater than 1, M are more than or equal to 2；The second encryption is carried out according to the first ciphertext and first key to obtain and corresponding final ciphertext in plain text.The present invention passes through the iteration twice completed at least AES encryption algorithm flow within a clock cycle, the clock cycle of a complete AES encryption algorithm flow consumption is considerably reduced, to increase substantially the arithmetic speed of single AES arithmetic element.
Description
Technical field
The present invention relates to art of cryptography, hard in particular to a kind of aes algorithm implementation method, device and solid-state
Disk.
Background technique
Realize that the AES arithmetic element of AES encryption algorithm when hardware circuit is realized, considers that the timing control of hardware circuit is patrolled
Volume, an iteration operation in a clock cycle completion AES encryption algorithm is generallyd use, and a complete AES encryption is calculated
Method process at least needs 10 iteration, i.e., at least time-consuming 10 clock cycle.By taking the key length of 128bit as an example, in clock frequency
Rate be 200Mhz when, then the speed of single AES arithmetic core be 128bit/ (10*5ns), i.e. 0.32G/ seconds.This speed for
The current overwhelming majority is related to for the application of data storage being inadequate.Existing solution generallys use multiple AES fortune
It calculates unit and improves arithmetic speed in a manner of external assembly line, but existing solution is due to increasing AES arithmetic element
Number, so as to cause the increase of chip area and the increase of hardware resource cost.
Summary of the invention
The embodiment of the present invention is designed to provide a kind of aes algorithm implementation method, device and solid state hard disk, by one
The iteration twice at least AES encryption algorithm flow is completed in a clock cycle, considerably reduces a complete AES encryption
The clock cycle of algorithm flow consumption, to increase substantially the arithmetic speed of single AES arithmetic element.
To achieve the goals above, technical solution used in the embodiment of the present invention is as follows:
In a first aspect, being applied to solid state hard disk, the side the embodiment of the invention provides a kind of aes algorithm implementation method
Method includes: to carry out InvAddRoundKey according to plaintext of the initial key inputted to input to obtain initial ciphertext；According to initial key into
Row round key handles to obtain first key, wherein round key processing has N number of clock cycle, and each clock cycle corresponds to M next round
Key generates operation, wherein N is the positive integer that the positive integer greater than 1, M are more than or equal to 2；It is carried out according to initial ciphertext
First encryption obtains the first ciphertext, wherein the first encryption has N number of clock cycle, and each clock cycle corresponds to M times
Recyclable interative computation, wherein N is the positive integer that the positive integer greater than 1, M are more than or equal to 2；According to the first ciphertext and
First key carries out the second encryption and obtains and corresponding final ciphertext in plain text.
Second aspect, the embodiment of the invention also provides a kind of aes algorithm realization devices, are applied to solid state hard disk, described
Device includes initial encryption module, first key generation module, the first encrypting module and the second encrypting module.Wherein, initial to add
Close module is used to carry out InvAddRoundKey to the plaintext of input according to the initial key of input to obtain initial ciphertext；First key generates
Module is used to carry out round key according to initial key to handle to obtain first key, wherein round key processing has N number of clock week
Phase, each clock cycle correspond to M round key and generate operation, wherein N is more than or equal to 2 for the positive integer greater than 1, M
Positive integer；First encrypting module obtains the first ciphertext for carrying out the first encryption according to initial ciphertext, wherein first adds
Close processing has N number of clock cycle, and each clock cycle corresponds to M recyclable interative computation, wherein N is just whole greater than 1
Number, M are the positive integer more than or equal to 2；Second encrypting module adds for carrying out second according to the first ciphertext and first key
Close processing obtains and corresponding final ciphertext in plain text.
The third aspect, the embodiment of the invention also provides a kind of solid state hard disk, the solid state hard disk includes microprocessor, deposits
Reservoir, flash memory, AES arithmetic element, microprocessor and memory, flash memory and state AES arithmetic element and are electrically connected；Memory is used for
Storing initial key；Flash memory is for storing final ciphertext；Microprocessor is read initial close in memory for receiving in plain text
Key is input to AES arithmetic element, to execute: carrying out according to the initial key of input and the plaintext control AES arithmetic element of input
InvAddRoundKey obtain initial ciphertext and according to initial key control AES arithmetic element carry out round key handle to obtain first it is close
Key, wherein round key processing has N number of clock cycle, and each clock cycle correspond to the generation operation of M round key, wherein N is
It is more than or equal to 2 positive integer and to control AES arithmetic element according to initial ciphertext and carry out the greater than 1 positive integer, M
One encryption obtains the first ciphertext, wherein the first encryption has N number of clock cycle, and each clock cycle corresponds to M times can
Loop iteration operation, wherein N is the first ciphertext of positive integer and foundation that the positive integer greater than 1, M are more than or equal to 2
And first key control AES arithmetic element carries out the second encryption and obtains and corresponding final ciphertext in plain text.
Compared with the prior art, a kind of aes algorithm implementation method, device and solid state hard disk provided in an embodiment of the present invention, it is first
First, the plaintext that microprocessor receiving host issues；Then, microprocessor reads initial key from memory, according to input
Initial key and the plaintext of input carry out InvAddRoundKey and obtain initial ciphertext, next, controlling AES operation list according to initial key
Member carries out round key and handles to obtain first key, wherein round key processing has N number of clock cycle, and each clock cycle corresponds to M
Secondary round key generates operation, wherein N is the positive integer that the positive integer greater than 1, M are more than or equal to 2；Next, according to first
Beginning ciphertext control AES arithmetic element carries out the first encryption and obtains the first ciphertext, wherein when the first encryption has N number of
Clock period, each clock cycle correspond to M recyclable interative computation, wherein N is to be greater than or wait for the positive integer greater than 1, M
In 2 positive integer, finally, according to the first ciphertext and first key control AES arithmetic element carry out the second encryption obtain with
Final ciphertext is stored in flash memory by corresponding final ciphertext in plain text.Compared with prior art, the embodiment of the present invention is by one
The iteration twice at least AES encryption algorithm flow is completed in the clock period, considerably reduces a complete AES encryption algorithm
The clock cycle of process consumption, to increase substantially the arithmetic speed of single AES arithmetic element.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, special embodiment below, and appended by cooperation
Attached drawing is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows the block diagram of solid state hard disk provided in an embodiment of the present invention.
Fig. 2 shows a kind of aes algorithm implementation method flow charts provided in an embodiment of the present invention.
Fig. 3 shows the exemplary diagram of the first encryption provided in an embodiment of the present invention.
Fig. 4 shows that the embodiment of the invention provides another aes algorithm implementation methods.
Fig. 5 shows the block diagram of aes algorithm realization device provided in an embodiment of the present invention.
Fig. 6 shows the cell schematics of the first encrypting module provided in an embodiment of the present invention.
Fig. 7 shows the cell schematics of the second encrypting module provided in an embodiment of the present invention.
Fig. 8 shows the structural block diagram of multiple AES arithmetic elements provided in an embodiment of the present invention
Icon: 100- solid state hard disk；101- microprocessor；102- memory；103- flash memory；104-AES arithmetic element；
200-AES algorithm realization device；201- initial encryption module；202- first key generation module；The first encrypting module of 203-；
The first encryption unit of 2031-；The first iteration unit of 2032-；The second encrypting module of 204-；2041- Key generating unit；2042-
Second encryption unit；2043- secondary iteration unit；The final ciphertext generation unit of 2044-.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
Fig. 1 is please referred to, Fig. 1 shows the block diagram of solid state hard disk 100 provided in an embodiment of the present invention, solid state hard disk
100 include microprocessor 101, memory 102, flash memory 103, AES arithmetic element 104, and microprocessor 101 and memory 102 dodge
103, AES arithmetic element 104 is deposited to be electrically connected.
Microprocessor 101 can be specific integrated circuit, field programmable gate array or other programmable logic device,
Discrete gate or transistor logic, discrete hardware components.It can receive the plaintext that host issues and control AES arithmetic element
104 realize or execute disclosed each method, step and the logic diagram in the embodiment of the present invention.
Memory 102 is nonvolatile memory, is used for storing initial key, which is not solid state hard disk 100
Except host as it can be seen that dedicated for storing initial key.
Flash memory 103 is non-volatile memory medium, for storing to the final ciphertext generated after encrypting in plain text.
AES arithmetic element 104 can be logic circuit, for being carried out according to the initial key of input to the plaintext of input
AES encryption.
First embodiment
Referring to figure 2., Fig. 2 shows a kind of aes algorithm implementation method flow charts provided in an embodiment of the present invention.Processing side
Method the following steps are included:
Step 101, InvAddRoundKey is carried out according to plaintext of the initial key of input to input obtain initial ciphertext.
In embodiments of the present invention, it needs to store to the data of solid state hard disk 100 for user in plain text, it is hard in order to reinforce solid-state
The safety of data on disk 100, the microprocessor 101 of solid state hard disk 100 are first after receiving the plaintext that user is issued by host
Can first aes algorithm encryption be carried out to plaintext, then store encrypted data into the flash memory 103 of solid state hard disk 100 again.It adopts
It to encryption is carried out in plain text is realized by AES arithmetic element 104 with aes algorithm, therefore, microprocessor 101 first will storage
The initial key stored in device 102 is read, and then will be input to AES arithmetic element 104 with initial key in plain text and be carried out AES encryption
Final ciphertext is obtained after operation, and final ciphertext is stored into flash memory 103.
The length of the plaintext of AES encryption be it is fixed, be 128bit, constitute the byte matrix of a 4x4, each member in matrix
The length of element is a byte length, and the length of key can be 128bit, 192bit or 256bit.AES encryption process packet
An InvAddRoundKey of beginning, intermediate repeatedly recyclable interative computation are included, last time not loop iteration operation can follow
Before ring iterative operation, an InvAddRoundKey is carried out to plaintext according to initial key first and obtains initial ciphertext, it then will be initial
The input that ciphertext and initial key are recycled interative computation as first time continues subsequent arithmetic.
Step 102, it carries out round key according to initial key to handle to obtain first key, wherein round key processing has N number of
Clock cycle, each clock cycle correspond to M round key and generate operation, wherein N is positive integer greater than 1, M be greater than or
Positive integer equal to 2.
In embodiments of the present invention, each clock cycle carries out M round key and generates operation and M recyclable interative computation
It corresponds, the intermediate result that each round key generation operation obtains is for the input pair as corresponding recyclable interative computation
The input ciphertext of the recyclable interative computation is encrypted, and the m times round key generates the key of the generation of operation as the m+1 times
Round key generates the input of operation, each clock cycle last time round key generate key that operation obtains as it is next when
The round key in clock period generates the input of operation, and it is first key that the M time round key, which generates the key that operation obtains, this is first close
One of input of the key as the second cryptographic calculation.
Step 103, the first encryption is carried out according to initial ciphertext and obtain the first ciphertext, wherein the first encryption tool
Have N number of clock cycle, each clock cycle corresponds to M recyclable interative computation, wherein N is positive integer greater than 1, M be greater than
Or the positive integer equal to 2.
In embodiments of the present invention, the length of key is different, and the number for being recycled interative computation is also different, for example, working as
When key length is 128bit, the number for being recycled interative computation is 9 times, when key length is 192bit, is recycled iteration
The number of operation is 11 times, and when key length is 256bit, the number for being recycled interative computation is 13 times, still, regardless of close
Key length is how many, finally all can once not loop iteration operation, be recycled interative computation include 4 steps, be respectively as follows: word
Section transformation (SubBytes), row displacement (ShiftRows), column mixing (Mixcolumns) and InvAddRoundKey (AddRoundKey),
Wherein, byte transformation is that each byte is substituted in look-up table with the method for look-up table and is corresponded to by non-linear replacement function
Character string, row displacement is that row each in matrix is carried out to circulating displacement, and column mixing is with a normal Matrix Multiplication with previous
Obtained matrix is walked, so that each element is the weighted sum of all elements of the element column, InvAddRoundKey in matrix
It is that each byte in matrix and the secondary round key are done into XOR operation, each round key generates scheme by key and generates, most
The operation for once including the steps that default step afterwards includes being respectively: byte transformation, row displacement and InvAddRoundKey.Of the invention real
It applies in example, the recyclable iteration that each clock cycle needs the number of the round key generated and each clock cycle to need to carry out is transported
The number of calculation is equal, needs to generate how many a round key and just carries out how many times round key generating algorithm to the key of input, every time
The round key that round key generating algorithm generates, it is every to carry out a round key life as the input of round key generating algorithm next time
A round key can be obtained at algorithm.The initial input of first encryption is initial ciphertext and initial key, including N*M times
Recyclable interative computation, wherein N is the number of clock cycle, is greater than 1 positive integer, and M is what each clock cycle completed
The number of recyclable interative computation, is greater than or equal to 2 positive integer, is recycled under the output conduct of interative computation each time
The input of primary recyclable iteration, for example, N is 4, M 2, i.e. it includes 4 clock cycle, Mei Geshi that the first encryption, which has altogether,
The clock period includes 2 recyclable interative computations, and Fig. 3 shows the exemplary diagram of the first encryption provided in an embodiment of the present invention,
In Fig. 3, the first encryption includes altogether 4 clock cycle, and each clock cycle includes 2 recyclable interative computations, and first
The initial input of encryption is initial ciphertext and initial key, each clock cycle carry out 2 recyclable interative computations it
Before, 2 round key are also generated, a round key generating algorithm is carried out to initial key first and obtains first round key, so
A round key generating algorithm is carried out to first round key afterwards and obtains second round key, is carrying out being recycled iteration for the first time
Initial ciphertext and first round key are inputted when operation, and first time is recycled obtained the first interim ciphertext of interative computation and the
Input of two round key as second of recyclable interative computation, finally obtain the output of first clock cycle first face
Shi Miwen continues to be iterated the recyclable interative computation of each clock cycle, until the operation of N number of clock cycle is completed,
The interim ciphertext of the first of the output of n-th clock cycle is the first ciphertext, and the round key finally generated in the n-th clock cycle is made
For first key.
It should be noted that the first encryption continues N number of clock cycle, wherein the clock cycle is that AES completes a base
The chronomere of this movement, in embodiments of the present invention, in each clock cycle, AES logical unit is completed at least twice
Recyclable interative computation, can also will in each clock cycle in the case where hardware performance allows in practical application scene
AES logical unit is designed to complete recyclable interative computation three times or more than three times.
Step 104, it is obtained according to the first ciphertext and first key the second encryption of progress corresponding with plaintext final close
Text.
In embodiments of the present invention, the operation that the second encryption is related to is in addition to including that last time not transport by loop iteration
Can also include recyclable interative computation except calculation, the number of specific recyclable interative computation can according to aes algorithm can
The difference of the number for the recyclable interative computation that the total degree of loop iteration operation and the first encryption include is calculated, example
Such as, aes algorithm includes 9 recyclable interative computations and 1 not loop iteration operation, and the first encryption has 4 clock weeks
Phase, corresponding 2 recyclable interative computations of each clock cycle, therefore, the first encryption completes 4*2=8 times altogether and is recycled
Interative computation there remains 9-8=1 recyclable interative computation and not carry out, at this point, the second encryption includes successively being recycled repeatedly
For operation and successively not loop iteration operation, and so on, when aes algorithm includes 9 recyclable interative computations and is not recycled for 1 time
Interative computation, the first encryption have 3 clock cycle, and each clock cycle corresponds to 3 recyclable interative computations, at this point,
Second encryption can not include recyclable interative computation, only include last time not loop iteration operation, similarly, when
Aes algorithm includes 11 recyclable interative computations and 1 not loop iteration operation, and the first encryption has 3 clock cycle,
Corresponding 3 recyclable interative computations of each clock cycle, at this point, the second encryption is including 2 recyclable interative computations and most
Primary not loop iteration operation afterwards.
Aes algorithm implementation method provided in an embodiment of the present invention, by completing at least AES encryption within a clock cycle
Iteration twice in algorithm flow considerably reduces the clock cycle of a complete AES encryption algorithm flow consumption, thus
Increase substantially the arithmetic speed of single AES arithmetic element 104.
Further, on the basis of Fig. 2, a kind of possible implementation is given below, Fig. 4 shows implementation of the present invention
Example provides another aes algorithm implementation method, and referring to figure 4., this method, step 103 includes the first encryption sub-step (step
103-1) and the first iteration sub-step (step 103-2, step 103-3 and step 103-4), specific as follows:
Step 103-1, according to initial ciphertext and initial key carry out recyclable interative computation in the nth clock period and
Round key in the nth clock period generates operation, obtains the centre that the recyclable interative computation in the nth clock period obtains
Round key in ciphertext and nth clock period generates the intermediate key that operation obtains；The n is just whole less than or equal to N-1
Number.
In embodiments of the present invention, as an implementation, nth clock is carried out according to initial ciphertext and initial key
Recyclable interative computation in period and the round key in the nth clock period generate operation, obtain in the nth clock period
Round key in the intermediate ciphertext and nth clock period that recyclable interative computation obtains generates the intermediate key that operation obtains
Implementation method may include that first key generates sub-step, the second encryption sub-step and secondary iteration sub-step, wherein first is close
Key generates sub-step
M next round cipher key calculation is carried out using round key generating algorithm according to initial key, obtains M the first temporary keys,
Wherein, first temporary key is calculated in each round key.
In embodiments of the present invention, M recyclable interative computation is completed in order to match to unify in a clock cycle, needed one
M the first temporary keys are generated in a clock cycle, it, can to guarantee in each recyclable interative computation of a clock cycle
The result of this recyclable interative computation is obtained to input corresponding first temporary key and the first interim ciphertext.
Second, which encrypts sub-step, includes:
Firstly, according to the genesis sequence of the first temporary key, obtained from the first temporary key m-th first it is interim close
Key；M is the positive integer less than or equal to M-1；
It is recycled secondly, carrying out recyclable interative computation to initial ciphertext according to m-th of first temporary keys and obtaining the m times
The interim ciphertext of the first of interative computation.
In embodiments of the present invention, the sequence of the recyclable interative computation in each clock cycle generates suitable with round key
Sequence is consistent.
Secondary iteration sub-step includes:
The first interim ciphertext that the m times recyclable interative computation is obtained as the m+1 times recyclable interative computation just
Beginning ciphertext；Until the first interim ciphertext for obtaining the M times recyclable interative computation is as intermediate close when the number of iterations reaches M
Text, the first temporary key that M next round cipher key calculation is generated is as intermediate key.
Step 103-2, when the intermediate ciphertext for obtaining interative computation recyclable in the nth clock period is as (n+1)th
The initial ciphertext of interative computation input is recycled in the clock period；
Step 103-3, when the intermediate key for generating operation based on the round key in the nth clock period obtains (n+1)th
Round key in the clock period generates the initial key of operation input, generates operation based on the round key in (n+1)th clock cycle
Obtained intermediate key, the recyclable interative computation in (n+1)th clock cycle of iteration；
Step 103-4, until obtaining the recyclable interative computation in the n-th clock cycle when the number of iterations reaches N
Intermediate ciphertext is as the first ciphertext and the intermediate key for obtaining the round key generation operation in the n-th clock cycle as first
Key；
Step 104 includes that the second key generates sub-step (step 104-1, step 104-2), third encryption sub-step (step
Rapid 104-3, step 104-4, step 104-5), third iteration sub-step (step 104-6, step 104-7) and final ciphertext it is raw
At sub-step (step 104-8), specifically include:
Step 104-1, total number of keys K needed for obtaining the second encryption, wherein K=preset value-M*N；
In embodiments of the present invention, preset value is related with key length, and when key length is 128bit, preset value is
10, when key length is 192bit, preset value 12, when key length is 256bit, preset value 14.
Step 104-2, it is calculated according to first key using the round key that round key generating algorithm carries out K times, wherein every time
Second temporary key is calculated in round key；
In embodiments of the present invention, the algorithm that the second temporary key and the first temporary key use all is that round key generates calculation
The key that clock cycle each in first encryption processing step generates is known as by method, for ease of description, the embodiment of the present invention
The key that clock cycle each in second encryption processing step generates is known as the second temporary key by one temporary key, and first adds
The number for the key that each period generates in close processing step is the same, and each period generates in the second encryption processing step
The number of key can be different, for example, aes algorithm includes 9 recyclable interative computations and 1 not loop iteration operation,
First encryption has 3 clock cycle, each clock cycle corresponding 3 recyclable interative computations, the second encryption, only
Including not loop iteration operation for the last time, therefore, in the first encryption processing step, each clock cycle need to generate the
The number of one temporary key is 3, and in the second encryption processing step, each clock cycle needs the second temporary key generated
Number be 1.
Step 104-3, when K is 1, using the second temporary key of k-th as the second key, using the first ciphertext as second
Ciphertext；
In embodiments of the present invention, K means that the second encryption only includes successively not loop iteration operation for 1, does not wrap
Recyclable interative computation is included, at this time, it is only necessary to generate second temporary key, and second temporary key is close as second
Key, using the first ciphertext of the first encryption as the second ciphertext.
Step 104-4, it when K is greater than 1, according to the genesis sequence of the second temporary key, is obtained from the second temporary key
K-th of second temporary keys；K is the positive integer less than or equal to K-1；
In embodiments of the present invention, K, which is greater than 1, means that the second encryption includes K-1 recyclable interative computation and one
Secondary not loop iteration operation.
Step 104-5, the recyclable interative computation of kth time is carried out to the first ciphertext according to k-th of second temporary keys to obtain
Second interim ciphertext of kth time；
Step 104-6, using the second interim ciphertext of kth time as+1 the first ciphertext of kth, iteration kth+1 time recyclable
Interative computation；
Step 104-7, until the number of iterations reaches K-1 times, using the K-1 times the second temporary key as the second key and
Using the second of the K-1 times the interim ciphertext as the second ciphertext；
Step 104-8, not loop iteration operation is carried out according to second the second ciphertext of key pair obtain final ciphertext.
In embodiments of the present invention, by being completed at least AES encryption algorithm flow within a clock cycle twice
Iteration, and generate identical with corresponding the number of iterations round key within a clock cycle, compared with prior art, with
It is lower the utility model has the advantages that
The clock cycle of a complete AES encryption algorithm flow consumption is considerably reduced, to increase substantially list
The arithmetic speed of a AES arithmetic element 104.
Referring to figure 5., Fig. 5 shows the block diagram of aes algorithm realization device 200 provided in an embodiment of the present invention.
Aes algorithm realization device 200 is applied to solid state hard disk 100 comprising initial encryption module 201；First encrypting module 203；The
One encryption unit 2031；First iteration unit 2032；Second encrypting module 204；Key generating unit 2041；Second encryption unit
2042；Secondary iteration unit 2043；Final ciphertext generation unit 2044.
In embodiments of the present invention, initial encryption module 201 is for executing step 101.
In embodiments of the present invention, first key generation module 202 is for executing step 102.
In embodiments of the present invention, the first encrypting module 203 is for executing step 103.
Please referring to Fig. 6, Fig. 6 shows the cell schematics of the first encrypting module 203 provided in an embodiment of the present invention, and first
Encrypting module 203 includes the first encryption unit 2031, the first iteration unit 2032, wherein the first encryption unit 2031 is for holding
Row step 103-1, the first iteration unit 2032 is for executing step 103-2~step 103-4.
In embodiments of the present invention, the second encrypting module 204 is for executing step 104.
Please referring to Fig. 7, Fig. 7 shows the cell schematics of the second encrypting module 204 provided in an embodiment of the present invention, and second
Encrypting module 204 includes that Key generating unit 2041, the second encryption unit 2042, secondary iteration unit 2043 and final ciphertext are raw
At unit 2044, wherein Key generating unit 2041 is for executing step 104-1~step 104-2, the second encryption unit 2042
For step 104-3~step 104-5, secondary iteration unit 2043 is final close for executing step 104-6~step 104-7
Literary generation unit 2044 is for executing step 104-8.
Aes algorithm realization device 200 provided in an embodiment of the present invention, firstly, according to defeated under the control of microprocessor 101
The initial key entered carries out InvAddRoundKey to the plaintext control AES arithmetic element 104 of input and obtains initial ciphertext, secondly, micro-
It carries out round key according to initial key control AES arithmetic element 104 under the control of processor 101 to handle to obtain first key, so
Afterwards, the first encryption is carried out according to initial ciphertext control AES arithmetic element 104 under the control of microprocessor 101 obtain the
One ciphertext, finally, the controller in microprocessor 101 is carried out according to the first ciphertext and first key control AES arithmetic element 104
Second encryption obtains final ciphertext corresponding with plaintext, to realize corresponding technical effect.
It should be noted that the cryptographic calculation being related in all modules and unit that aes algorithm realization device 200 includes
It is that microprocessor 101 controls the realization of AES arithmetic element 104.
The prior art generallys use multiple AES arithmetic elements 104 and carries out flowing water to improve the efficiency of AES encryption operation
Line operation, and then the arithmetic speed of AES encryption operation is improved, it is that 128bit needs 9 recyclable interative computations and 1 for key
The scene of secondary not loop iteration operation, conventionally, as each clock cycle carries out once recyclable interative computation, because
This, generallys use 10 AES arithmetic elements 104, and each AES arithmetic element 104 does once recyclable interative computation, the last one
AES arithmetic element 104 does last time not loop iteration operation, can thus make multiple AES arithmetic elements 104 work simultaneously
Make, and then improves arithmetic speed, still, in the prior art, 10 AES arithmetic elements 104 increase the chip area occupied, from
And lead to the increase of cost, on the other hand, one section it is independent need the AES operation of plaintext encrypted to start when and at the end of,
It usually will appear the different degrees of idle situation of multiple AES arithmetic elements 104 in 10 AES arithmetic elements 104, to waste
Resource, AES arithmetic element more than 104, the resource wasted at this time are also more.
In embodiments of the present invention, it can be completed 2 times or more due to each AES arithmetic element 104 in a clock cycle
Recyclable interative computation therefore in the scene of above-mentioned 10 AES arithmetic elements 104 of needs, reach same effect
Fruit, the embodiment of the present invention only need 5 AES arithmetic elements 104, please refer to Fig. 8, and Fig. 8 is provided in an embodiment of the present invention multiple
The structural block diagram of AES arithmetic element 104, in Fig. 8, each AES arithmetic element 104 is individually electrically connected with microprocessor 101, micro- place
It manages device 101 and controls 5 progress pile line operations of AES arithmetic elements 104, on the one hand, reduce what AES arithmetic element 104 occupied
Chip area reduces costs, on the other hand, since the number of the AES arithmetic element 104 of needs is reduced, so that resource
Waste be also reduced.
In conclusion a kind of aes algorithm implementation method, device and solid state hard disk provided by the invention, which comprises
Initial key according to input carries out InvAddRoundKey to the plaintext of input and obtains initial ciphertext；According to initial ciphertext and initial key
It carries out the first encryption and obtains the first ciphertext and first key, wherein the first encryption has N number of clock cycle, each
Clock cycle corresponds to M recyclable interative computation, wherein N is the positive integer that the positive integer greater than 1, M are more than or equal to 2；
The second encryption is carried out according to the first ciphertext and first key to obtain and corresponding final ciphertext in plain text.With prior art phase
Than the embodiment of the present invention passes through the iteration twice completed at least AES encryption algorithm flow within a clock cycle, greatly
The clock cycle for reducing a complete AES encryption algorithm flow consumption, to increase substantially single AES arithmetic element
Arithmetic speed.
In several embodiments provided herein, it should be understood that disclosed device and method can also pass through
Other modes are realized.The apparatus embodiments described above are merely exemplary, for example, flow chart and block diagram in attached drawing
Show the device of multiple embodiments according to the present invention, the architectural framework in the cards of method and computer program product,
Function and operation.In this regard, each box in flowchart or block diagram can represent the one of a module, section or code
Part, a part of the module, section or code, which includes that one or more is for implementing the specified logical function, to be held
Row instruction.It should also be noted that function marked in the box can also be to be different from some implementations as replacement
The sequence marked in attached drawing occurs.For example, two continuous boxes can actually be basically executed in parallel, they are sometimes
It can execute in the opposite order, this depends on the function involved.It is also noted that every in block diagram and or flow chart
The combination of box in a box and block diagram and or flow chart can use the dedicated base for executing defined function or movement
It realizes, or can realize using a combination of dedicated hardware and computer instructions in the system of hardware.
In addition, each functional module in each embodiment of the present invention can integrate one independent portion of formation together
Point, it is also possible to modules individualism, an independent part can also be integrated to form with two or more modules.
It, can be with if the function is realized and when sold or used as an independent product in the form of software function module
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.It needs
Illustrate, herein, relational terms such as first and second and the like be used merely to by an entity or operation with
Another entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this realities
The relationship or sequence on border.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
Claims (10)
1. a kind of aes algorithm implementation method, which is characterized in that the described method includes:
Initial key according to input carries out InvAddRoundKey to the plaintext of input and obtains initial ciphertext；
It carries out round key according to the initial key to handle to obtain first key, wherein the round key processing has N number of clock
Period, each clock cycle correspond to M round key and generate operation, wherein the N is to be greater than 1 positive integer, the M
Positive integer more than or equal to 2；
The first encryption is carried out according to the initial ciphertext and obtains the first ciphertext, wherein first encryption has N number of
Clock cycle, each clock cycle correspond to M recyclable interative computation, wherein the N is greater than 1 positive integer, described
M is the positive integer more than or equal to 2；
It is obtained according to first ciphertext and the first key the second encryption of progress corresponding with the plaintext final close
Text.
2. aes algorithm implementation method as described in claim 1, which is characterized in that described to carry out the according to the initial ciphertext
The step of one encryption obtains the first ciphertext includes the first encryption sub-step and the first iteration sub-step, wherein
Described first, which encrypts sub-step, includes:
The recyclable interative computation in the nth clock period and n-th are carried out according to the initial ciphertext and the initial key
Round key in clock cycle generates operation, obtains the centre that the recyclable interative computation in the nth clock period obtains
Round key in ciphertext and the nth clock period generates the intermediate key that operation obtains；The n is less than or equal to N-1's
Positive integer；
First iteration sub-step includes:
The obtained intermediate ciphertext of interative computation will be recycled in the nth clock period as can in (n+1)th clock cycle
The initial ciphertext of loop iteration operation input；
The intermediate key for generating operation based on the round key in the nth clock period obtained in (n+1)th clock cycle
Round key generates the initial key of operation input, and round key based on (n+1)th clock cycle generates during operation obtains
Between key, the recyclable interative computation in (n+1)th clock cycle described in iteration；
Until the intermediate ciphertext for obtaining the recyclable interative computation in the n-th clock cycle is as institute when the number of iterations reaches N
The intermediate key stated the first ciphertext and obtain the round key generation operation in the n-th clock cycle is close as described first
Key.
3. aes algorithm implementation method as claimed in claim 2, which is characterized in that described according to the initial ciphertext and described
Initial key carries out the recyclable interative computation in the nth clock period and the round key in the nth clock period generates operation,
The wheel obtained in the intermediate ciphertext and the nth clock period that the recyclable interative computation in the nth clock period obtains is close
The step of intermediate key that key generation operation obtains includes that first key generates sub-step, the second encryption sub-step and secondary iteration
Sub-step, wherein
The first key generates sub-step
M next round cipher key calculation is carried out using round key generating algorithm according to the initial key, obtains M the first temporary keys,
Wherein, first temporary key is calculated in each round key；
Described second, which encrypts sub-step, includes:
According to the genesis sequence of first temporary key, m-th of first temporary keys are obtained from first temporary key；
The m is the positive integer less than or equal to M-1；
Recyclable interative computation carried out to the initial ciphertext according to m-th of first temporary keys obtain the m time to be recycled
The interim ciphertext of the first of interative computation；
The secondary iteration sub-step includes:
The first interim ciphertext that described the m times recyclable interative computation is obtained as the m+1 times recyclable interative computation just
Beginning ciphertext；
Until the number of iterations the first interim ciphertext that when reaching M, the M times recyclable interative computation is obtained is as intermediate ciphertext,
The first temporary key that M next round cipher key calculation is generated is as intermediate key.
4. aes algorithm implementation method as described in claim 1, which is characterized in that described according to first ciphertext and described
It is sub including the generation of the second key that first key carries out the step of the second encryption obtains final ciphertext corresponding with the plaintext
Step, third encrypt sub-step, third iteration sub-step and final ciphertext and generate sub-step, wherein
Second key generates sub-step
Total number of keys K needed for obtaining second encryption, wherein K=preset value-M*N；
It is calculated according to the first key using the round key that round key generating algorithm carries out K times, wherein each round key
Second temporary key is calculated；
The third encrypts sub-step
It is using second temporary key of k-th as the second key, first ciphertext is close as second when the K is 1
Text；
When the K is greater than 1, according to the genesis sequence of second temporary key, kth is obtained from second temporary key
A second temporary key；The k is the positive integer less than or equal to K-1；
The recyclable interative computation of kth time is carried out to first ciphertext according to k-th of second temporary keys and obtains kth time
Second interim ciphertext；
The third iteration sub-step includes:
Second interim ciphertext of the kth time is used as to+1 the first ciphertext of kth, kth+1 time recyclable iteration described in iteration is transported
It calculates；
Until the number of iterations reaches K-1 times, using described the K-1 times the second temporary key as the second key and by the K-
The interim ciphertext of the second of 1 time is as the second ciphertext；
The final ciphertext generates sub-step
Not loop iteration operation, which is carried out, according to the second ciphertext described in second key pair obtains final ciphertext.
5. a kind of aes algorithm realization device, which is characterized in that described device includes:
Initial encryption module carries out InvAddRoundKey for plaintext of the initial key according to input to input and obtains initial ciphertext；
First key generation module handles to obtain first key, wherein described for carrying out round key according to the initial key
Round key processing has N number of clock cycle, and each clock cycle correspond to the generation operation of M round key, wherein the N is
Greater than the positive integer that 1 positive integer, the M are more than or equal to 2；
First encrypting module obtains the first ciphertext for carrying out the first encryption according to the initial ciphertext, wherein described the
One encryption has N number of clock cycle, and each clock cycle corresponds to M recyclable interative computation, wherein the N is
Greater than the positive integer that 1 positive integer, the M are more than or equal to 2；
Second encrypting module, for according to first ciphertext and the first key carry out the second encryption obtain with it is described
Corresponding final ciphertext in plain text.
6. aes algorithm realization device as claimed in claim 5, which is characterized in that first encrypting module adds including first
Close unit and the first iteration unit, wherein
First encryption unit is used for:
The recyclable interative computation in the nth clock period and n-th are carried out according to the initial ciphertext and the initial key
Round key in clock cycle generates operation, obtains the intermediate ciphertext of the recyclable interative computation in the nth clock period
The intermediate key that fortune is calculated is generated with the round key in the nth clock period；The n is just whole less than or equal to N-1
Number；
First iteration unit is used for:
The intermediate ciphertext that interative computation is recycled in the nth clock period is recycled as in (n+1)th clock cycle
The initial ciphertext of interative computation input；
The intermediate key for generating operation based on the round key in the nth clock period obtained in (n+1)th clock cycle
Round key generates the initial key of operation, and it is close that the round key based on (n+1)th clock cycle generates the centre that operation obtains
Key, the recyclable interative computation in (n+1)th clock cycle described in iteration；
Until the number of iterations is when reaching N, n-th is recycled the intermediate ciphertext of interative computation as first ciphertext and by institute
It states n-th and is recycled the intermediate key of interative computation as the first key.
7. aes algorithm realization device as claimed in claim 6, which is characterized in that first encryption unit is specifically used for:
M next round cipher key calculation is carried out using round key generating algorithm according to the initial key, obtains M the first temporary keys,
Wherein, first temporary key is calculated in each round key；
According to the genesis sequence of first temporary key, m-th of first temporary keys are obtained from first temporary key；
The m is the positive integer less than or equal to M-1；
Recyclable interative computation carried out to the initial ciphertext according to m-th of first temporary keys obtain the m time to be recycled
The first interim ciphertext that interative computation obtains；
The first interim ciphertext that described the m times recyclable interative computation is obtained as the m+1 times recyclable interative computation just
Beginning ciphertext；
Until the number of iterations the first interim ciphertext that when reaching M, the M times recyclable interative computation is obtained is as intermediate ciphertext,
The first temporary key that M next round cipher key calculation is generated is as intermediate key.
8. aes algorithm realization device as claimed in claim 5, which is characterized in that second encrypting module further includes key
Generation unit, the second encryption unit, secondary iteration unit and final ciphertext generation unit, wherein
Key generating unit is used for:
Total number of keys K needed for obtaining second encryption, wherein K=preset value-M*N；
It is calculated according to the first key using the round key that round key generating algorithm carries out K times, wherein each round key
Second temporary key is calculated；
Second encryption unit is used for:
It is using second temporary key of k-th as the second key, first ciphertext is close as second when the K is 1
Text；
When the K is greater than 1, according to the genesis sequence of second temporary key, kth is obtained from second temporary key
A second temporary key；The k is the positive integer less than or equal to K-1；
The recyclable interative computation of kth time is carried out to first ciphertext according to k-th of second temporary keys and obtains kth time
Second interim ciphertext；
Secondary iteration unit is used for:
Second interim ciphertext of the kth time is used as to+1 the first ciphertext of kth, kth+1 time recyclable iteration described in iteration is transported
It calculates；
Until the number of iterations reaches K-1 times, using described the K-1 times the second temporary key as the second key and by the K-
The interim ciphertext of the second of 1 time is as the second ciphertext；
Finally ciphertext generation unit includes:
Not loop iteration operation, which is carried out, according to the second ciphertext described in second key pair obtains final ciphertext.
9. a kind of solid state hard disk, which is characterized in that the solid state hard disk includes microprocessor, memory, flash memory, AES operation list
Member, the microprocessor are electrically connected with the memory, the flash memory and the AES arithmetic element；
The memory is used for storing initial key；
The flash memory is for storing final ciphertext；
The microprocessor reads the initial key in memory and is input to the AES arithmetic element for receiving in plain text, with
It executes:
The AES arithmetic element progress InvAddRoundKey is controlled according to the initial key of input and the plaintext of input to obtain initially
Ciphertext；
It controls the AES arithmetic element progress round key according to the initial key to handle to obtain first key, wherein the wheel
Key handling has N number of clock cycle, and each clock cycle corresponds to M round key and generates operation, wherein the N is big
In 1 positive integer, the M be positive integer more than or equal to 2；
The first encryption of the AES arithmetic element progress is controlled according to the initial ciphertext and obtains the first ciphertext, wherein described
First encryption has N number of clock cycle, and each clock cycle corresponds to M recyclable interative computation, wherein the N
For the positive integer that the positive integer greater than 1, the M are more than or equal to 2；
According to first ciphertext and first key control the second encryption of the AES arithmetic element progress obtains and institute
State the corresponding final ciphertext of text clearly.
10. solid state hard disk as claimed in claim 9, which is characterized in that the AES arithmetic element is multiple, each AES
Arithmetic element is electrically connected with the microprocessor, the multiple AES arithmetic element under the controller of the microprocessor with
Pipeline system executes such as method of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565309.XA CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565309.XA CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109379180A true CN109379180A (en) | 2019-02-22 |
| CN109379180B CN109379180B (en) | 2022-04-19 |
Family
ID=65371042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811565309.XA Active CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109379180B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106935A (en) * | 2019-12-27 | 2020-05-05 | 天津芯海创科技有限公司 | Key management architecture supporting multi-terminal heterogeneous mode |
| CN112104450A (en) * | 2020-08-27 | 2020-12-18 | 广东技术师范大学天河学院 | Symmetric data encryption method and system and electronic equipment |
| CN112398641A (en) * | 2020-11-17 | 2021-02-23 | 上海桂垚信息科技有限公司 | Application method of AES encryption algorithm on encryption chip |
| CN114244510A (en) * | 2021-12-20 | 2022-03-25 | 深圳忆联信息系统有限公司 | Hardware acceleration apparatus, method, device, and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527531A (en) * | 2003-03-07 | 2004-09-08 | 华为技术有限公司 | Method of realizing data enciphering standard or double data enciphering standard |
| CN1677921A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Method for enciphering data through programmable device |
| US20120159186A1 (en) * | 2010-12-21 | 2012-06-21 | Apple Inc. | Securing the implementation of a cryptographic process using key expansion |
| US20120189119A1 (en) * | 2004-12-09 | 2012-07-26 | Brickell Ernie F | Method and Apparatus for Increasing the Speed of Cryptographic Processing |
| US20150086007A1 (en) * | 2013-09-24 | 2015-03-26 | Sanu Mathew | Compact, low power advanced encryption standard circuit |
| CN104639314A (en) * | 2014-12-31 | 2015-05-20 | 深圳先进技术研究院 | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method |
| US20150363332A1 (en) * | 2014-06-16 | 2015-12-17 | Texas Instruments Incorporated | Hardware protection of inline cryptographic processor |
| CN108718317A (en) * | 2018-06-12 | 2018-10-30 | 飞天诚信科技股份有限公司 | A kind of method and device of personal identification number protection |
-
2018
- 2018-12-20 CN CN201811565309.XA patent/CN109379180B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527531A (en) * | 2003-03-07 | 2004-09-08 | 华为技术有限公司 | Method of realizing data enciphering standard or double data enciphering standard |
| CN1677921A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Method for enciphering data through programmable device |
| US20120189119A1 (en) * | 2004-12-09 | 2012-07-26 | Brickell Ernie F | Method and Apparatus for Increasing the Speed of Cryptographic Processing |
| US20120159186A1 (en) * | 2010-12-21 | 2012-06-21 | Apple Inc. | Securing the implementation of a cryptographic process using key expansion |
| US20150086007A1 (en) * | 2013-09-24 | 2015-03-26 | Sanu Mathew | Compact, low power advanced encryption standard circuit |
| US20150363332A1 (en) * | 2014-06-16 | 2015-12-17 | Texas Instruments Incorporated | Hardware protection of inline cryptographic processor |
| CN104639314A (en) * | 2014-12-31 | 2015-05-20 | 深圳先进技术研究院 | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method |
| CN108718317A (en) * | 2018-06-12 | 2018-10-30 | 飞天诚信科技股份有限公司 | A kind of method and device of personal identification number protection |
Non-Patent Citations (3)
| Title |
|---|
| D. MCGREW; CISCO SYSTEMS等: "An Interface and Algorithms for Authenticated Encryption", 《IETF RFC5116》 * |
| 李冬冬等: "并行AES算法加密解密电路的高效实现", 《微电子学与计算机》 * |
| 龚向东等: "基于FPGA的AES算法硬件实现优化及IP核应用", 《电子设计工程》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106935A (en) * | 2019-12-27 | 2020-05-05 | 天津芯海创科技有限公司 | Key management architecture supporting multi-terminal heterogeneous mode |
| CN111106935B (en) * | 2019-12-27 | 2023-05-16 | 天津芯海创科技有限公司 | Key management architecture supporting multi-terminal heterogeneous mode |
| CN112104450A (en) * | 2020-08-27 | 2020-12-18 | 广东技术师范大学天河学院 | Symmetric data encryption method and system and electronic equipment |
| CN112398641A (en) * | 2020-11-17 | 2021-02-23 | 上海桂垚信息科技有限公司 | Application method of AES encryption algorithm on encryption chip |
| CN114244510A (en) * | 2021-12-20 | 2022-03-25 | 深圳忆联信息系统有限公司 | Hardware acceleration apparatus, method, device, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109379180B (en) | 2022-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109379180A (en) | Aes algorithm implementation method, device and solid state hard disk | |
| CN106850221B (en) | Information encryption and decryption method and device | |
| CN104639314A (en) | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method | |
| US8515059B2 (en) | Cryptographic processor with dynamic update of encryption state | |
| Fiskiran | Workload characterization of elliptic curve cryptography and other network security algorithms for constrained environments | |
| CN101467127B (en) | Method and device for generating a pseudorandom string | |
| Shantha et al. | SAT_Jo: An enhanced lightweight block cipher for the internet of things | |
| CN101958790B (en) | Encryption or decryption method of wireless communication network digital information | |
| CN107992283A (en) | A kind of method and apparatus that finite field multiplier is realized based on dimensionality reduction | |
| McMillan et al. | JBits™ implementations of the advanced encryption standard (Rijndael) | |
| CN106982116A (en) | A kind of local file encryption method of the AES based on reversible logic circuits | |
| Deshpande et al. | AES encryption engines of many core processor arrays on FPGA by using parallel, pipeline and sequential technique | |
| Ajmi et al. | Efficient and lightweight in-memory computing architecture for hardware security | |
| Gueron et al. | Hardware implementation of AES using area-optimal polynomials for composite-field representation GF (2^ 4)^ 2 of GF (2^ 8) | |
| Bajaj et al. | AES algorithm for encryption | |
| CN105577362B (en) | A kind of byte replacement method and system applied to aes algorithm | |
| CN104753662A (en) | Encryption key stream generating method based on AES (Advanced Encryption Standard) algorithm | |
| CN108134665A (en) | A kind of 8 bit A ES circuits applied towards IoT | |
| Atha | Design & Implementation of AES Algorithm Over FPGA Using VHDL | |
| Qin et al. | On the cryptanalysis of two cryptographic algorithms that utilize chaotic neural networks | |
| Harshitha et al. | High Performance Advanced Encryption Standard system using Secure Double Rate Registers | |
| Abed et al. | FPGA implementation of a modified advanced encryption standard algorithm | |
| RajaRaja et al. | Implementation of hardware efficient light weight encryption method | |
| Punia et al. | Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture | |
| Bu et al. | ’A Compact Implementation of SM4 Encryption and Decryption Circuit’ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |