CN109379084B - Decoding method for burst errors - Google Patents
Decoding method for burst errors Download PDFInfo
- Publication number
- CN109379084B CN109379084B CN201811047097.6A CN201811047097A CN109379084B CN 109379084 B CN109379084 B CN 109379084B CN 201811047097 A CN201811047097 A CN 201811047097A CN 109379084 B CN109379084 B CN 109379084B
- Authority
- CN
- China
- Prior art keywords
- unreliable
- check matrix
- parity check
- positions
- errors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Algebra (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Error Detection And Correction (AREA)
Abstract
The invention relates to a decoding method aiming at burst errors, which improves an RS code OSD soft-decision decoding algorithm. The method comprises the following steps: recording the position of the bit with large level change by setting a threshold value; locking positions where random errors are likely to occur through log-likelihood ratio calculation, and jointly determining unreliable positions where errors are likely to occur; a burst error pre-judgment module is added, and a parity check matrix which is a unit matrix at a corresponding position is generated according to the most unreliable position; calculating a syndrome by using the received code words and the generated parity check matrix, calculating the number of non-zero bits in the syndrome, comparing the number of non-zero bits with a set threshold value, and if the number of non-zero bits is less than the threshold value, judging that errors are concentrated on a selected unreliable position, otherwise, judging that errors occur on the reliable position; and finishing the decoding work.
Description
Technical Field
The invention belongs to the field of error control coding in channel coding, and relates to a decoding algorithm for continuous burst errors and individual random errors in a burst error channel.
Background
With the rapid development of society and the rapid progress of science and technology, information interaction among people is more and more frequent, and the information interaction is closely related to the development of communication technology. Especially, the digital communication mode has the advantages of long distance, high quality, convenience for encryption storage and integration, and the like, and becomes the core of the contemporary communication mode. However, the channel environment of modern transmission is more and more complex, and due to the influence of factors such as noise interference, defects caused by the nature of the channel, and the like, the signal is deviated in the channel, so that the received signal is erroneous, and the transmission result is influenced. Error control is a technique for correcting an erroneous signal occurring during signal transmission in digital communication using a digital information coding and decoding technique. The RS code is a linear block code with high error correction capability, has a simple structure, and is widely applied to the fields of data storage, digital video broadcasting, deep space exploration, wireless communication, wireless metropolitan area network and the like.
The current RS decoding algorithm is mainly divided intoHard-decision decoding algorithm (hard-decision decoding) and soft-decision decoding algorithm (soft-decision decoding). The hard decision Algorithm is an Algorithm for decoding according to a direct decision result of a transmission signal, and mainly includes a Berlekamp-Massey Algorithm (BMA) Algorithm, an Euclidean Algorithm, and a correlation of the Inverse-Free BM (RiBM) Algorithm. The soft decision algorithm is completed according to the channel level information of the digital signal after transmission, and because the channel information is considered, the soft decision algorithm has higher coding gain compared with the hard decision decoding algorithm, but has larger algorithm complexity, and the main algorithm has
(KV) algorithm, Low-Complexity Chase (LCC) algorithm, Adaptive Belief Propagation (ABP) algorithm, and Ordered Statistical Decoding (OSD) algorithm.
With the research on error control coding in wireless communication, the research direction is closer to the actual situation, and therefore, the research channel model advances from an ideal additive white gaussian noise channel to a channel model with continuous burst errors closer to the actual situation. In the channel model with continuous burst errors, due to the interference of pulses, the error probability of a certain section of code element in the channel code word is very high, even continuous errors occur, and meanwhile, random errors which often occur in the additive white gaussian noise channel model also occur in the channel model. Because the continuous error code word segment is longer and exceeds the decoding capability of the common RS code decoding Algorithm, the Algorithm is not applicable any more, Y.Wu et al propose a BCA (Burst-error Correcting Algorithm) Algorithm aiming at continuous Burst errors in 2012, Wang Lingyu carries out optimization and improvement on the basis of the BCA Algorithm in 2016, and propose a hard-decision-based fusion soft-decision decoding (BCHDD-LCC) Algorithm, so that the decoding effect under a mixed channel is further improved.
Disclosure of Invention
The invention aims to provide a decoding method with less hardware consumption for burst errors. The technical scheme is as follows:
a decoding method for burst errors improves an RS code OSD soft-decision decoding algorithm. Comprises the following steps:
(1) recording the position of the bit with large level change by setting a threshold value, and taking the position as a burst error position with possible errors; locking positions where random errors are likely to occur through log-likelihood ratio calculation, and jointly determining unreliable positions where errors are likely to occur;
(2) and a burst error pre-judging module is added, for RS (N, K) codes, code words to be decoded are input into the burst error pre-judging module, the positions of the burst errors possibly existing in the code words are pre-judged through the burst error pre-judging module, other unreliable positions are found out according to the log-likelihood ratio, and N-K least reliable positions are determined in total.
(3) Generating a parity check matrix which is an identity matrix at a corresponding position according to the least reliable position;
(4) calculating a syndrome by using the received code words and the generated parity check matrix, calculating the number of non-zero bits in the syndrome, comparing the number of non-zero bits with a set threshold value, and if the number of non-zero bits is less than the threshold value, judging that errors are concentrated on a selected unreliable position, otherwise, judging that errors occur on the reliable position;
(5) then, completing decoding work according to the result in the step (3), and if the error only appears at an unreliable position, turning over the unreliable bit corresponding to the non-zero position of the syndrome to complete decoding; and if errors occur at the reliable position, performing modular twofold addition on the syndrome and each column of the parity check matrix to select a column with the minimum number of non-zero bits, overturning the code word at the corresponding position, updating the syndrome simultaneously, and returning (4) the updated syndrome to decode again.
Preferably, the step (2) generates the parity check matrix which is the identity matrix at the corresponding position according to the least reliable position as the sparse parity check matrix, and the generating method is as follows: and obtaining a numerator calculation polynomial and a denominator calculation polynomial of each row and each column of the parity check matrix according to the known unreliable position, and dividing the numerator calculation polynomial and the denominator calculation polynomial to obtain values of each row and each column of the parity check matrix, thereby obtaining the sparse parity check matrix.
The invention is mainly designed aiming at the decoding process of the code words in the burst error channel, and applies the idea of a belief propagation algorithm to RS codes. In a burst error channel, a channel model can be simplified into two Gaussian channels with different variances, a random error channel corresponds to a small variance, a burst error channel corresponds to a large variance, and only the variances of a burst error state and a non-burst error state in the channel are different, which directly causes that the level fluctuation at a burst position is large, so that the burst error position can be pre-judged by using channel soft information, and meanwhile, the most unreliable position is determined by combining a log-likelihood ratio, and burst errors and individual random errors in the channel are decoded. In addition, the area of a hardware structure is effectively reduced through a new odd-even check matrix sparsification method, and the circuit efficiency is improved.
Drawings
FIG. 1 work flow of decoding algorithm
FIG. 2 hardware architecture of parity check matrix module
Detailed Description
For a burst error channel, when continuous burst errors occur in the channel, the range of variation in the magnitude of the modulation level at the burst error position is larger than that at other positions due to the larger interference of the received noise. Therefore, the threshold value is determined through a large number of experiments, and the bit occurrence position with large level change is recorded through setting of the threshold value as a burst error position with a possibility of error. Meanwhile, individual random errors may occur in the channel, and therefore, the positions where the random errors may occur are locked through log likelihood ratio calculation at the same time, and unreliable positions where the random errors may occur are determined together.
Performing sparsification of a parity check matrix according to the recorded unreliable positions, changing check matrix columns corresponding to the unreliable positions into unit arrays to reduce the influence of the unreliable positions on a decoding process, calculating syndromes by using the obtained sparse parity check matrix, performing threshold judgment on syndrome weights (the threshold is determined through a large number of experiments) according to the calculated syndrome bit weights, selecting different decoding schemes, and if the weights are less than the threshold, indicating that errors occur only at the unreliable positions, and turning the corresponding unreliable bit positions to complete decoding; if the error is larger than the threshold value, the error occurs at other reliable positions, secondary calculation is carried out on the syndrome and the parity check matrix to determine the position of the error reliable code word, the syndrome is turned over and adjusted, the syndrome is updated, and the threshold value is calculated again to carry out secondary decoding.
When a sparse parity check matrix is generated, the existing known method is Gaussian elimination, but the Gaussian elimination algorithm is complex in implementation process and high in hardware consumption. Aiming at the problem, the invention provides a novel algorithm, which obtains a numerator calculation polynomial and a denominator calculation polynomial of each row and each column of the parity check matrix according to the known unreliable position, and divides the numerator calculation polynomial and the denominator calculation polynomial to obtain the value of each row and column of the parity check matrix. The numerator calculation polynomial and the denominator calculation polynomial of the novel algorithm have the same structure and can be realized by the same hardware architecture pipeline, so that the structure on a hardware circuit is simple, and the hardware consumption is greatly reduced compared with a Gaussian elimination method.
The work flow of the whole algorithm is shown in fig. 1, and the following describes the flow of the algorithm in detail with reference to fig. 1:
(1) for RS (N, K) codes, firstly, a code word to be decoded is used as the input of an algorithm and enters a burst error pre-judging module in the algorithm, and the position of a burst error possibly existing in the code word can be pre-judged through the module. And in addition, other unreliable positions are found according to the log-likelihood ratio, and N-K least reliable positions are determined.
(2) The parity check matrix which is the unit matrix at the corresponding position is generated according to the most unreliable position, the process can be realized by recoding diagonalization or Gaussian elimination, and the algorithm provides a novel sparse check matrix generation algorithm, achieves the same effect and is more beneficial to hardware realization.
(3) And then, calculating a syndrome by using the received code word and the generated sparse parity check matrix, calculating the number of non-zero bits in the syndrome, comparing the number of the non-zero bits with a set threshold value, and if the number of the non-zero bits is less than the threshold value, indicating that errors are concentrated on the selected unreliable position, otherwise, indicating that errors occur on the reliable position.
(4) And (4) finishing decoding work according to the result in the step (3). And if the error only appears at the unreliable position, turning over the unreliable bit corresponding to the non-zero position of the syndrome to finish decoding.
(5) And if errors occur at the reliable position, performing modular twofold addition on the syndrome and each column of the parity check matrix to select a column with the minimum number of non-zero bits, overturning the code word at the corresponding position, updating the syndrome simultaneously, and returning (4) the updated syndrome to decode again.
The specific pseudo code of the Algorithm is shown in Algorithm: Decoding Algorithm.
In the invention, for the Algorithm pseudo code for generating the local sparse parity check matrix, as shown in Algorithm: matrix H, the following description is made in combination with the Algorithm pseudo code:
(1) for RS (N, K) codes, firstly, N-K least reliable positions are determined according to an upper layer module, and the least reliable positions are shifted, so that the first bit is an unreliable position. The unreliable position after displacement is recorded as gamma1，γ2，γ3，…，γN-KReliable position is denoted as ρ1，ρ2，ρ3，…，ρK。
(2) Calculating the constant F (alpha) ═ alpha-alpha2)(α-α3)…(α-αn) Wherein alpha is the primitive of Galois field, providing the basis for the subsequent calculation.
(3) Respectively calculating a first row numerator and a each row denominator of the parity check matrix according to the unreliable positions and the reliable positions after the shift, wherein the first row numerator calculation polynomial is
The denominator is calculated as a polynomial
On the basis of the first row of molecules, using the formula
And calculating numerators of other rows, finally dividing the numerator denominator corresponding to each column of each row to obtain a non-sparse part value of the parity check matrix, and finally filling the unit matrix in the column corresponding to the unreliable position to obtain the parity check matrix with local sparse characteristic.
As can be seen from a calculation formula in the algorithm, the calculation of the numerator of the first row and the denominator of each row of the parity check matrix has the same framework, can be realized by using the same hardware structure, and has low hardware resource consumption. The hardware architecture diagram is shown in fig. 2, where the B2P module is a conversion of a binary representation to an exponentiation representation of a galois field.
Claims (2)
1. A decoding method aiming at burst errors improves a soft decision decoding algorithm of an RS code Ordered Statistics Decoding (OSD) algorithm, and comprises the following steps:
(1) a burst error pre-judging module is added, for RS (N, K) codes, code words to be decoded are input into the burst error pre-judging module, burst error positions possibly existing in the code words are pre-judged, bit occurrence positions with large level changes are recorded through setting of a threshold value, the burst error positions are used as burst error positions possibly having errors, and m burst error positions are determined and used as first-class unreliable positions;
(2) determining N-K-m unreliable positions according to the log-likelihood ratio to serve as a second class of unreliable positions, and determining the N-K unreliable positions through the step (1) and the step (2);
(3) generating a parity check matrix which is an identity matrix at the corresponding position according to the N-K unreliable positions;
(4) calculating a syndrome by using the received code words and the generated parity check matrix, calculating the number of non-zero bits in the syndrome, comparing the number of non-zero bits with a set threshold value, and if the number of non-zero bits is less than the threshold value, judging that errors are concentrated on a selected unreliable position, otherwise, judging that errors occur on the reliable position;
(5) then, decoding is finished according to the result in the step (4), and if the error only appears at an unreliable position, the unreliable bit corresponding to the non-zero position of the syndrome is turned over to finish decoding; and (4) if errors occur at the reliable position, performing modular twofold addition on the syndrome and each column of the parity check matrix, selecting a column with the minimum number of non-zero bits, overturning the code word at the corresponding position, updating the syndrome simultaneously, and returning the updated syndrome to the step (4) for decoding again.
2. The decoding method according to claim 1, wherein the parity check matrix generated in step (3) is a sparse parity check matrix, and the generation method is: and obtaining a numerator calculation polynomial and a denominator calculation polynomial of each row and each column of the parity check matrix according to the known unreliable position, and dividing the numerator calculation polynomial and the denominator calculation polynomial to obtain values of each row and each column of the parity check matrix, thereby obtaining the sparse parity check matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811047097.6A CN109379084B (en) | 2018-09-08 | 2018-09-08 | Decoding method for burst errors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811047097.6A CN109379084B (en) | 2018-09-08 | 2018-09-08 | Decoding method for burst errors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109379084A CN109379084A (en) | 2019-02-22 |
| CN109379084B true CN109379084B (en) | 2021-09-17 |
Family
ID=65404669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811047097.6A Active CN109379084B (en) | 2018-09-08 | 2018-09-08 | Decoding method for burst errors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109379084B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110096384B (en) * | 2019-04-23 | 2021-06-25 | 西安电子科技大学 | High-reliability aerospace data and intermediate variable protection method |
| CN110339574B (en) * | 2019-08-13 | 2022-07-29 | 腾讯科技（深圳）有限公司 | Game hotspot card pause position determining method and device, server and storage medium |
| CN111917420B (en) * | 2020-08-25 | 2023-07-04 | 广东省新一代通信与网络创新研究院 | LDPC self-adaptive decoding method and LDPC self-adaptive decoder |
| CN114448559A (en) * | 2020-11-05 | 2022-05-06 | 华为技术有限公司 | Position detection method and device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997011530A1 (en) * | 1995-09-20 | 1997-03-27 | Hitachi, Ltd. | Method and device for decoding burst error of reed-solomon code |
| US5659557A (en) * | 1990-11-08 | 1997-08-19 | Cirrus Logic, Inc. | Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping |
| EP1387542A2 (en) * | 2002-07-29 | 2004-02-04 | Panasonic Communications Co., Ltd. | Symbol and hyperframe synchronisation in an ADSL modem |
| CN101621299A (en) * | 2008-07-04 | 2010-01-06 | 华为技术有限公司 | Burst correcting method, equipment and device |
| CN102122964A (en) * | 2011-03-31 | 2011-07-13 | 西安电子科技大学 | Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA) |
| CN102299758A (en) * | 2010-06-23 | 2011-12-28 | 中兴通讯股份有限公司 | Method and device for processing data burst error |
| CN106330205A (en) * | 2016-08-17 | 2017-01-11 | 天津大学 | Decoding algorithm for long burst errors |
| CN106341211A (en) * | 2016-08-17 | 2017-01-18 | 天津大学 | Self-adaptive decoding method for multiple channel environments |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8327240B2 (en) * | 2008-11-26 | 2012-12-04 | Broadcom Corporation | Handling burst error events with interleaved Reed-Solomon (RS) codes |
-
2018
- 2018-09-08 CN CN201811047097.6A patent/CN109379084B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659557A (en) * | 1990-11-08 | 1997-08-19 | Cirrus Logic, Inc. | Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping |
| WO1997011530A1 (en) * | 1995-09-20 | 1997-03-27 | Hitachi, Ltd. | Method and device for decoding burst error of reed-solomon code |
| EP1387542A2 (en) * | 2002-07-29 | 2004-02-04 | Panasonic Communications Co., Ltd. | Symbol and hyperframe synchronisation in an ADSL modem |
| CN101621299A (en) * | 2008-07-04 | 2010-01-06 | 华为技术有限公司 | Burst correcting method, equipment and device |
| CN102299758A (en) * | 2010-06-23 | 2011-12-28 | 中兴通讯股份有限公司 | Method and device for processing data burst error |
| CN102122964A (en) * | 2011-03-31 | 2011-07-13 | 西安电子科技大学 | Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA) |
| CN106330205A (en) * | 2016-08-17 | 2017-01-11 | 天津大学 | Decoding algorithm for long burst errors |
| CN106341211A (en) * | 2016-08-17 | 2017-01-18 | 天津大学 | Self-adaptive decoding method for multiple channel environments |
Non-Patent Citations (3)
| Title |
|---|
| Multiple channel error-correction algorithms for LCC decoding of Reed-Solomon codes and its high-speed architecture design;Lingyu Wang1;《IET Communications》;20170630;第1407-1415页 * |
| 王令宇.一种RS码突发错误译码算法的改进算法.《 南开大学学报(自然科学版)》.2018,第50-53页. * |
| 突发错误检测重数分配算法及其电路设计;胡岩;《西安交通大学学报》;20171206;第70-75页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109379084A (en) | 2019-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109379084B (en) | Decoding method for burst errors | |
| US7949927B2 (en) | Error correction method and apparatus for predetermined error patterns | |
| US9166623B1 (en) | Reed-solomon decoder | |
| US8677222B2 (en) | Method and device for decoding Reed-Solomon (RS) code | |
| US7712008B2 (en) | Systems and methods for error reduction associated with information transfer | |
| CN1132320C (en) | Optimal soft-output decoder for tail-biting trellis codes | |
| US8347178B2 (en) | Method, device and apparatus for correcting bursts | |
| CN110915141A (en) | TURBO product code based on polar code | |
| US7853854B2 (en) | Iterative decoding of a frame of data encoded using a block coding algorithm | |
| US20090193313A1 (en) | Method and apparatus for decoding concatenated code | |
| US20170288698A1 (en) | Power saving for bit flipping decoding algorithm in ldpc decoder | |
| US20070162821A1 (en) | Parity check matrix, method of generating parity check matrix, encoding method and error correction apparatus | |
| CN107370491B (en) | High-performance low-delay extended TPC decoding method | |
| JP5374156B2 (en) | Apparatus and method for decoding and encoding data | |
| US7814394B2 (en) | Post viterbi error correction apparatus and related methods | |
| US8019020B1 (en) | Binary decoding for correlated input information | |
| CN116760425A (en) | CRC auxiliary OSD decoding method of LDPC code | |
| JP6567238B1 (en) | Error correction decoding apparatus and error correction decoding method | |
| US20140013190A1 (en) | Iterative Decoding Device and Related Decoding Method | |
| CN113659994A (en) | Estimation method of low-complexity convolutional code random interleaving relation | |
| Cho et al. | Reduced complexity Chase-Pyndiah decoding algorithm for turbo product codes | |
| US8156412B2 (en) | Tree decoding method for decoding linear block codes | |
| CN106330205A (en) | Decoding algorithm for long burst errors | |
| CN111527705B (en) | Channel code construction for decoder reuse | |
| Liu et al. | A novel concatenation decoding of Reed-Solomon codes with SPC product codes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |