CN109360809A

CN109360809A - Stacked integrated circuit chip-packaging structure

Info

Publication number: CN109360809A
Application number: CN201810937368.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-07-17
Filing date: 2016-07-17
Publication date: 2019-02-19
Also published as: CN109360808B; CN106206458B; CN109360810A; CN106206458A; CN109360808A

Abstract

The present invention provides a kind of stacked integrated circuit chip-packaging structures, it is with multilayer encapsulation layer, the multilayer encapsulation layer is respectively provided with route except the bottom of other each layers of the bottom, IC chip electrical connection of the route in the layer corresponding to it, line layer between layer by layer is electrically isolated each other by encapsulated layer, there is dot matrix pad, line layer is electrically connected respectively at some or all of in the pad with leading-out terminal on the side surface of packaging body.Present invention decreases encapsulation volumes, enhance the flexibility of encapsulation.

Description

Stacked integrated circuit chip-packaging structure

Technical field

The present invention relates to integrated antenna package fields, and in particular to a kind of stacked integrated circuit chip-packaging structure.

Background technique

In integrated antenna package, routing or the mode of wiring is mostly used to be electrically connected drawing for each IC chip Foot, to reach set packaging body functional module, stacked chip package can reduce encapsulation volume, be current using wider Development pattern.But stack package be easy to cause between routing and intersects short circuit or wiring is too bad is not easy the problem of changing, to obtain in this way Packaging body often volume it is larger and encapsulation it is extremely not nimble, wiring arbitrarily can not be adjusted and be changed.

Summary of the invention

Based on solving the problems in above-mentioned encapsulation, the present invention provides a kind of stacked integrated circuit chip-packaging structure, With package substrate, it is provided with multiple pads on the package substrate, is provided with multilayer encapsulation layer, institute on the package substrate State multilayer encapsulation each layer of thickness be equal to every layer packaged by IC chip maximum gauge, the multilayer encapsulation Layer accommodates the groove of the IC chip except other each layers of the bottom all have, the ic core of upper layer encapsulated layer Piece is stacked in its lower layer's encapsulated layer ic core on piece respectively, the multilayer encapsulation layer except the bottom other each layers bottom Portion is respectively provided with route, IC chip electrical connection of the route in the layer corresponding to it, layer by layer between line Road floor is electrically isolated each other by encapsulated layer, on the side surface of packaging body have dot matrix pad, line layer respectively with the dot matrix It is electrically connected some or all of in formula pad with leading-out terminal.

Wherein, only packed layer covers half to the pad on package substrate.

Wherein, the level height of the route is identical with every layer of dot matrix pad of the height, is in corresponding relationship.

Wherein, the pad on package substrate and dot matrix pad are arranged to being aligned.

It wherein, further include redistribution line on side surface, the redistribution line needs and electric according to the function of encapsulating structure Different dot matrix pads is connected, and is coupled on the pad on corresponding package substrate.

Wherein, redistribution line crosses over different side surfaces.

Wherein, the IC chip of the multilayer encapsulation layer includes multiple, each layer of thickness root of multilayer encapsulation layer It is different and different according to the thickness of integrated chip packaged by every layer.

It wherein, may include multiple IC chips in each layer of the multilayer encapsulation layer, wherein every layer of relatively thin core On piece is equipped with rigid member.

Wherein, the thickness that the thickness of the rigid member is equal to most thick chip subtracts the thickness of corresponding relatively thin chip Degree.

Advantages of the present invention is as follows:

(1) stacked package is utilized, reduces encapsulation volume, enhances the flexibility of encapsulation；

(2) route redistribution is carried out using the dot matrix pad of encapsulation body side surface, increases the flexibility of wiring；

(3) use of rigid member prevents the bending warpage of stacked package.

Detailed description of the invention

Fig. 1 is the sectional view of integrated circuit package structure of the invention；

Fig. 2 is the top view of integrated circuit package structure of the invention；

Fig. 3 is a side surface electrical connection graph of integrated circuit package structure of the invention；

Fig. 4 is the perspective view of integrated circuit package structure of the invention.

Specific embodiment

Referring to Fig. 1, present invention firstly provides a kind of stacked integrated circuit encapsulating structure, encapsulating structure is a cuboid Packaging body is provided with multiple pads 2, is provided with multilayer encapsulation layer 7 on substrate 1 with package substrate 1 on package substrate 1, The thickness of thickness IC chip 3 according to packaged by every layer of each layer of the multilayer encapsulation layer 7 is different and different, often One layer of thickness be equal to every layer packaged by IC chip 3 maximum gauge, such as two in third layer encapsulated layer 7 The thickness of a IC chip is different, but the thickness of this layer is equal to the thickness of thicker IC chip, in this feelings Under condition, a rigid member 6, thickness etc. is arranged in the bending of upper integrated circuit chip in order to prevent above relatively thin chip 3 The thickness of relatively thin chip is subtracted in the thickness of thicker chip.

The multilayer encapsulation layer 7 all has receiving integrated circuit except other each layers (2-5 layers) of the bottom (the 1st layer) The groove 9 of chip 3, the stepped distribution of groove 9, the groove 9 can be potted with encapsulating material, and the encapsulating material is ring Oxygen resin or polyimides etc..3-5 layers of IC chip 3 is sequentially stacked on the IC chip 3 of its lower layer, can To be electrically isolated or can also be in electrical contact.The bottom of 2-5 layers of encapsulated layer 7 is respectively provided with route 4, the route 4 respectively at IC chip 3 in layer corresponding to it is electrically connected, layer by layer between line layer be electrically isolated each other by encapsulated layer 7, envelope Fill body side surface on have dot matrix pad 5, line layer respectively at be electrically connected some or all of in the pad with Leading-out terminal.In addition, only packed layer 7 covers half to pad 2, be conducive to the electrical connection of subsequent rewiring in this way.

Referring to fig. 2, top view only with two layers of encapsulated layer 7 is only schematically described, it can be seen that every layer of route 4 Level height it is identical with every layer of pad of height, be in corresponding relationship, and according to actual needs, route 4 can root in layers Different according to actual conditions realize redistribution.

Referring to Fig. 3, on a side surface of the mounting structure, dot matrix pad 5 be 4 × 3 matrix, pad 2 with Dot matrix pad 5 is arranged to alignment, is convenient to reroute, can be by different pads 5 by dividing again according to the needs being actually electrically connected 8 electrical connection of wiring, and be coupled on corresponding pad 2.

Referring to fig. 4, the three-dimensional electrical connection situation for illustrating side surface, redistribution line 8 can cross over different side tables Face is to be electrically connected the pads 5 of different surfaces.

Finally, it should be noted that obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description Other various forms of variations or variation out.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn The obvious changes or variations that Shen goes out are still in the protection scope of this invention.

Claims

1. a kind of stacked integrated circuit chip-packaging structure is provided with multiple welderings with package substrate on the package substrate Disk, is provided with multilayer encapsulation layer on the package substrate, and each layer of thickness of the multilayer encapsulation is equal to every layer and is sealed The maximum gauge of the IC chip of dress, the multilayer encapsulation layer accommodate the collection except other each layers of the bottom all have At the groove of circuit chip, the IC chip of upper layer encapsulated layer is stacked in its lower layer's encapsulated layer IC chip respectively On, the multilayer encapsulation layer is respectively provided with route except the bottom of other each layers of the bottom, and the route is right respectively at its institute In the layer answered IC chip electrical connection, layer by layer between line layer be electrically isolated each other by encapsulated layer, the side of packaging body On surface have dot matrix pad, line layer respectively be electrically connected some or all of in the dot matrix pad with draw Terminal；Only packed layer covers half to pad on package substrate；The level height of the route and the dot matrix pad Every layer of height is identical, is in corresponding relationship.