CN109359082B - USB data real-time monitoring system and method based on FPGA - Google Patents
USB data real-time monitoring system and method based on FPGA Download PDFInfo
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- CN109359082B CN109359082B CN201811082851.XA CN201811082851A CN109359082B CN 109359082 B CN109359082 B CN 109359082B CN 201811082851 A CN201811082851 A CN 201811082851A CN 109359082 B CN109359082 B CN 109359082B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
The invention relates to a USB data real-time monitoring system and method based on an FPGA, belonging to the technical field of electronics and communication. The invention comprises an FPGA chip, a USB transceiver module I, a USB transceiver module II and a DDR3SDRAM memory; the FPGA chip includes: the system comprises an ULPI data transceiver module I, an ULPI data transceiver module II, an ULPI control module I, an ULPI control module II, a data temporary storage module and an FPGA signal processing and coordinating module. The invention uses FPGA to transfer, and can unpack, store and forward the data on the USB bus without a PC machine after being connected into the USB transmission line, thereby realizing the non-invasive USB data real-time monitoring and acquisition in the data aspect.
Description
Technical Field
The invention relates to a USB data real-time monitoring system and method based on an FPGA, belonging to the technical field of electronics and communication.
Background
FPGA (Field-Programmable Gate Array) is called Field Programmable Gate Array. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The circuit design finished by hardware description language (Verilog or VHDL) can be quickly burned to the FPGA for testing through simple synthesis and layout, and is the mainstream of the existing IC verification technology. FPGAs can be quickly manufactured, can be modified to correct errors in the program, and are less expensive to manufacture. Meanwhile, the FPGA can realize a great number of logic functions, and due to the flexible and changeable internal structure, the logic units, the programmable internal connecting lines and the I/O units contained in the FPGA can be programmed by users in specific application, so that any logic function can be realized, and various design requirements can be met.
Usb (universal Serial bus), known as universal Serial bus, is a relatively new PC Serial communication protocol established by companies such as Microsoft, Compaq and IBM in 1995. The USB equipment is simple, convenient and interactive, has low price, and can be used as a serial port connection to realize multiple simultaneous use. USB interfaces have become standard interfaces for many digital devices (e.g., PCs, test and metrology instruments, cameras, mobile phones, and various embedded development boards).
But in the process of USB transmission, point-to-point transmission is adopted. Although portable mobile computers are available, they can be conveniently carried and used at any time, but considering some special working environments and working costs, if it is inconvenient or the real-time monitoring of data on the transmission line by a PC is not allowed, and the real-time monitored data is forwarded and preprocessed, other devices are needed to forward and preprocess the data. Therefore, the USB data real-time monitoring circuit based on the FPGA is provided.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the invention provides a USB data real-time monitoring system and method based on an FPGA (field programmable gate array), which are used for finishing real-time monitoring and acquisition of data on a USB bus by taking the FPGA as a core chip and assisting a USB processing chip.
The technical scheme of the invention is as follows: a USB data real-time monitoring system based on FPGA comprises an FPGA chip 1, a USB transceiver module I2, a USB transceiver module II 3 and a DDR3SDRAM memory 4;
the FPGA chip 1 includes: an ULPI data transceiver module I6, an ULPI data transceiver module II 7, an ULPI control module I8, an ULPI control module II 9, a data temporary storage module 10 and an FPGA signal processing and coordinating module 12;
the FPGA chip 1 is connected with a USB transceiver module I2, a USB transceiver module II 3 and a DDR3SDRAM memory 4; the USB transceiver module I2 and the USB transceiver module II 3 are connected to the FPGA chip 1 through different I/O ports, and the USB transceiver module I2 is connected with the FPGA signal processing and coordinating module 12 through an ULPI data transceiver module I6 and an ULPI control module I8; the FPGA signal processing and coordination module 12 is connected with the DDR3SDRAM memory 4 through the data temporary storage module 10, and the FPGA signal processing and coordination module 12 is connected with the USB transceiver module II 3 through the ULPI data transceiver module II 7 and the ULPI control module II 9.
The FPGA chip 1 further comprises a data forwarding module 11 and a back-end circuit 5; the data forwarding module 11 is connected to the back-end circuit 5, the FPGA signal processing and coordinating module 12 is connected to the data forwarding module 11 for sending the data read from the DDR3SDRAM memory 4 to the back-end circuit 5 through the data forwarding module 11, and the type of the communication protocol of the connection port are determined by the communication protocol or the interface of the back-end circuit 5.
The back-end circuit 5 employs a real-time image display circuit or a module capable of performing lucky algorithm processing on images.
After the USB transceiver module I2 receives data, the data signals are translated into data signals conforming to an ULPI protocol by a USB3320 chip, the data signals are transmitted to an FPGA signal processing and coordinating module 12 by cooperating with an ULPI control module I8 and an ULPI data transceiver module I6, the ULPI data transceiver module I6 restores the received signals into original signals, the original signals are copied and forwarded by the FPGA signal processing and coordinating module 12, one copy of the copied data is stored in a DDR3SDRAM memory 4 through a data temporary storage module 10, the other copy of the copied data is translated into ULPI signals through an ULPI data transceiver module II 7 and transmitted to a USB transceiver module II 3, and then the ULPI signals are transmitted to a PC.
The mode of the USB transceiver module I2 when connected with equipment at two ends is selectable through the ULPI control module I8; when the equipment connected with the USB transceiver module I2 is host equipment, the USB transceiver module I2 is set to work in a slave equipment mode through the ULPI control module I8; when the device connected with the USB transceiver module i 2 is a standard USB device, the USB transceiver module i 2 operates in the OTG mode, that is, the USB transceiver module i 2 serves as a host.
The data received by the USB transceiver module I2 is preferentially ensured to be transmitted to the USB transceiver module II 3 through the FPGA chip 1 and then transmitted to the PC machine through the FPGA signal processing and coordination module 12 in the FPGA chip 1 so as to restore a USB data transmission line; secondly, the monitored data is temporarily stored and forwarded; the flow judgment of the USB data, the real-time data monitoring and unloading and the establishment of the USB communication are all completed by the FPGA signal processing and coordinating module 12.
The core chip used by the FPGA chip 1 is an XC6SLX16-FTG256 chip of the Spartan6 series of Xilinx company; the DDR3SDRAM is a MT41J128M16HA-15E256MB DDR3 memory chip of the magnesium optical company; the USB transceiver module I2 and the USB transceiver module II 3 are identical in structure and respectively comprise a USB3320 chip and a USB interface.
A USB data real-time monitoring method based on FPGA, USB transceiver module I2 connects to the readable device, according to the type of the readable device, through ULPI control module I8 sets USB transceiver module I2 to different modes to realize the communication of both sides based on USB protocol;
according to the USB communication protocol, after the USB transceiver module I2 receives the transmitted data, the USB transceiver module I2 translates the data packet of the USB into a signal which accords with the ULPI protocol, and then the signal is sent to the FPGA signal processing and coordinating module 12 in the FPGA chip 1 through the ULPI protocol for temporary storage and forwarding; one copy of the copied data is stored in a DDR3SDRAM memory 4 through a data temporary storage module 10, the other copy of the copied data is translated into an ULPI signal through an ULPI data transceiver module II 7 and sent to a USB transceiver module II 3, then the ULPI signal is sent to a PC to restore a USB data transmission line, and the temporarily stored data is sent to a back-end circuit 5 through a data forwarding module 11.
The readable device comprises a USB flash disk or a PC; when the readable device is a USB flash disk, according to the USB communication protocol and the functions of the USB transceiver module I2, the USB transceiver module I2 is set to be in a host mode through the ULPI control module I8, the readable device USB flash disk works as a slave device, and communication on two sides is achieved based on the USB protocol;
when the readable device is a PC, according to the USB communication protocol and the functions of the USB transceiver module I2, the USB transceiver module I2 is set to be in a device mode through the ULPI control module I8, the readable device PC works as a host, and communication on two sides is achieved based on the USB protocol.
The working principle of the invention is as follows:
the USB transceiver module I2 and the USB transceiver module II 3 comprise a chip USB3320, a peripheral circuit and a USB interface. Because the power supply interface of the development board used in the invention is not matched with the power supply pins of the USB transceiver module I2 and the USB transceiver module II 3, the power supply pins are led out and then power is supplied by a voltage-stabilizing direct-current power supply. Crystal oscillator clock circuits on the USB transceiver module I2 and the USB transceiver module II 3 provide clock signals of 25MHz for the modules; the switch STMPS2151STR controls a VBUS power supply of +5V to be provided for the Micro B type USB interface. USB3320 is an ULPI transceiver chip, and converts data passing through the chip between differential signals and signals conforming to the ULPI communication protocol. Depending on the type of device connected, it may be selected to operate in different modes (host mode or USB device mode). Data transmission between the ULPI transmission chip USB3320 and the FPGA chip 1 is realized by data lines D0-D7 with 8-bit width;
the ULPI transmission chip USB3320 of the USB transceiver module I2 converts data into data with 8-bit width; then the data is sent to the FPGA chip 1 through D0-D7 of a USB3320 chip in the USB transceiver module I2; the USB3320 chip in the USB transceiver module II 3 receives the ULPI signal from the FPGA chip 1 through an 8-bit data bus from D0-D7, processes the ULPI signal into a differential signal and then sends the differential signal to connected equipment from a USB interface;
the ULPI transmission chip USB3320 of the USB transceiver module II 3 converts the data into data with 8-bit width; then the data is sent to the FPGA chip 1 through D0-D7 of a USB3320 chip in the USB transceiver module II 3; the USB3320 chip in the USB transceiver module I2 receives the ULPI signal from the FPGA chip 1 through an 8-bit data bus from D0-D7, processes the ULPI signal into a differential signal and then sends the differential signal to connected equipment from a USB interface;
in addition, the single USB transceiver module comprises two USB interfaces, an A-type female port and a Micro B-type interface, wherein the +5V VBUS driving power supply is only provided for the Micro B-type interface, so that the A-type female port is used for connecting other hosts in a slave mode, and the Micro B-type port is used for connecting other slave devices in a host mode. In the use of the invention, the fixed USB transceiver module II 3 is only connected to the host, i.e. the USB transceiver module II 3 only works in a slave Device (Device) mode; the USB transceiver module I2 can be selectively operated in a host mode or a slave mode according to different connected devices. Therefore, the invention fixes the effective data flow as: the connection between the PC and the FPGA chip 1 is completed by a USB transceiver module II 3. Such a design may reduce the complexity of the present invention.
The FPGA chip 1 is as follows: XC6SLX16-FTG256 which is produced by Xilinx company and is of low cost and low power consumption FPGA chip Spartan-6 series; the FPGA peripheral circuit is matched and comprises a power supply circuit and a clock circuit; the FPGA chip 1 is used as a core, and other accessories including a DDR3SDRAM memory 4, a key circuit and a water lamp circuit are further installed on the FPGA chip, wherein the key circuit comprises a key for resetting, and the water lamp circuit is used for prompting whether the circuit works normally or not. Two 2 x 32Pin pins of the FPGA chip are respectively connected to corresponding pins of Bank0 and Bank1 of the FPGA chip, the other end of the FPGA chip is respectively connected with a USB transceiver module I2 and a USB transceiver module II 3, and a DDR3SDRAM memory 4 is connected to corresponding pins of Bank3 of the FPGA chip 1; a clock circuit in the FPGA peripheral circuit provides a 50MHz clock signal for the FPGA chip 1 through a pin SYS _ CLK after being electrified, and a power supply circuit mainly provides required voltages of +5V, +3.3V and +1.5V for the FPGA chip 1 and the DDR3SDRAM 4. When the system is electrified and initialized, and after the USB transceiver module I2 receives a data request signal after connection, the requested data flows in from the USB transceiver module I2; when data passes through the FPGA chip 1, the data is restored into original data through the ULPI data transceiver module I6 and the ULPI control module I8 and flows into the FPGA signal processing and coordination module 12. In order to restore the USB bus transmission line, the FPGA signal processing and coordination module 12 preferentially sends the data from the USB transceiver module I2 to the ULPI data transceiver module II 7, and under the coordination of the ULPI control module II 9, the data are coded and then sent to the USB transceiver module II 3 according to the ULPI protocol, and then sent to the PC. The FPGA signal processing and coordination module 12 copies data flowing in from the USB transceiver module I2, sends the data to the data temporary storage module 10 and stores the data in the DDR3SDRAM memory 4, and invokes the data forwarding module 11 to send the monitored and collected data to the back-end circuit 5 when necessary.
The working process of the invention is as follows:
after power-on, the ULPI control module I8 and the ULPI control module II 9 respectively control the USB transceiver module I2 and the USB transceiver module II 3 to initialize, then the ULPI data transceiver module I6 and the ULPI data transceiver module II 7 respectively control the USB transceiver module I2 and the USB transceiver module II 3 to enumerate the device types or send the device type information of the USB transceiver module I2 and the USB transceiver module II 3 to the connected devices, and connection is established after handshaking; then the host connected with the USB transceiver module II 3 sends a data request command, and after receiving the command, the FPGA signal processing and coordinating module 12 controls the USB transceiver module I2 to send the data request command to the connected equipment; after the equipment connected with the USB transceiver module I2 returns data, the data is sent to a USB transceiver module II 3 in the FPGA signal processing and coordinating module 12 along the direction of returning to the PC; when the data is sent to the PC, a copy of data is temporarily stored in the DDR3SDRAM 4; finally, the FPGA signal processing and coordinating module 12 reads the data temporarily stored in the DDR3SDRAM memory 4, and sends the data to the back-end circuit 5 through the data forwarding module 11.
And the ULPI data transceiver module I6 and the ULPI data transceiver module II 7 realize corresponding functions through Verilog codes running on an FPGA chip. The module restores data signals with 8 bit wide transmitted by a USB transceiver module I2 and a USB transceiver module II 3 into an initial data type according to the ULPI transmission protocol of USB2.0, translates the data from the initial data into the data conforming to the ULPI protocol when the FPGA chip transmits the data to the USB transceiver module I2 and the USB transceiver module II 3, and then transmits the data.
The ULPI control module I8 and the ULPI control module II 9 are also realized by Verilog programs running on the FPGA chip 1. The module realizes the control of the USB3320 chip, controls the data transmission sequence on the bus and judges whether the bus is occupied or not through four signals of NTX, DIR, STP and CLK according to the ULPI transmission protocol of USB 2.0.
According to the ULPI protocol, an ULPI data transceiver module I6 and an ULPI control module I8 form a Link terminal I (also called a Link terminal 1), and an ULPI data transceiver module II 7 and an ULPI control module II 9 also form a Link terminal II (also called a Link terminal 2);
USB Transceiver module i 2 and USB Transceiver module ii 3 are collectively referred to as ULPI Transceiver end, also referred to as PHY end (ULPI Transceiver).
When the ULPI transceiver end sends data to the link end through a data bus, the signal DIR keeps high level, when no data exists, the signal DIR keeps low level, and whether the link end has data to send to the ULPI transceiver end is monitored; the signal CLK is a clock signal pin of the USB3320 chip, can output a clock signal of 60MHz, and can also be introduced into the chip for use, the invention synchronizes clock signals of the FPGA chip 1 and the USB3320 chip, and simultaneously uses a clock signal of 50MHz provided by an FPGA development board; after the data is received by the ULPI transceiver end, the driving signal NTX is at a high potential, which represents that the ULPI transceiver end has received the data, and the data to be sent next time is put on the data bus in the next clock period, and the data is sent when the next clock jump is waited; the STP signal represents the stop of communication, the STP transmits a stop signal once per clock cycle when there is no data transmission, and if there is data to be transmitted on the data bus, the signal STP holds the last bit of the data transmitted in the previous cycle in the next cycle after the data transmission is finished, and enters a cycle of being asserted once per clock cycle.
Therefore, data transmitted to the USB transceiver module I2 and the USB transceiver module II 3 by the FPGA chip 1 is controlled mainly by judging the signal NTX, the signal DIR and the signal STP. The principle of the cooperative work of each group of ULPI data transceiver modules and ULPI control modules (one group of ULPI data transceiver modules I6 and ULPI control modules I8, and one group of ULPI data transceiver modules II 7 and ULPI control modules II 9) is as follows: firstly, after the device is powered on, the device is initialized, the USB transceiver module I2 and the USB transceiver module II 3 respectively send handshake packets to the connected device (or host), enumerate the device types, and establish the connection. When data needs to be sent from the FPGA chip 1 to one of the USB transceiver module I2 or the USB transceiver module II 3, namely data is sent from the link end to the ULPI transceiver end, whether the STP signal keeps a signal of a previous period or not needs to be judged, and if yes, data transmission at the current time does not occur; the situation that the ULPI transceiver end transmits data to the link end does not exist when no data is transmitted, so that the DIR signal is driven to be in a high level; pulling up the NTX signal, starting to put data to be transmitted on a bus according to an ULPI protocol, and sending out the data in the next clock cycle till the data sending completion position; after the data transmission is completed, the STP holds the signal of the last bit data of the data transmitted in the previous cycle, and each signal is restored to the level when there is no data transmission. Similarly, when data needs to be sent from the ULPI transceiver end to the link end, after inquiring that the STP signal does not jump after lasting for two clock cycles, it is determined that no data transmission is in progress; keeping the signal DIR at low level, representing that the link end is to transmit data to the ULPI transceiver end; then the NTX signal is periodically pulled up, the data to be transmitted is put on a data bus, and the next clock period is waited for sending out; after the data transmission is finished, the signal STP maintains the level of the last bit signal of the data sent out in the last clock cycle, the signal DIR and the signal NTX are pulled down, and the data transmission is finished. The flow chart can refer to fig. 2.
The data temporary storage module 10 is responsible for coordinating the DDR3SDRAM 4 after receiving signals transmitted by the FPGA signal processing and coordinating module 12, and storing data to be stored in the DDR3SDRAM 4; and read out when needing to be forwarded, for the FPGA signal processing and coordinating module 12 to process and send to the data forwarding module 11. For controlling and configuring the DDR3SDRAM 4 chip, the MCB IP CORE of the DDR3SDRAM 4 can be generated by a Core Generator provided by Xilinx, and then part of the code parameters in the MCB IP CORE are modified.
The data forwarding module 11 is responsible for forwarding the original form of data to the back-end circuit 5 after receiving the signal from the FPGA signal processing and coordinating module 12 and under the condition that the back-end circuit 5 is ready to receive the data. Considering the difference of the interface of the back-end circuit 5 or the communication protocol, the common interface may be USB or gigabit ethernet, if the transmission speed is not required, a UART interface may be used, and the like.
The FPGA signal processing and coordinating module 12 is a Verilog program running on an FPGA chip, and is responsible for judging data flow direction, copying effective data, coordinating and controlling the work of other modules. In the present invention, the FPGA signal processing and coordinating module 12 is to implement the following detailed functions:
firstly, coordinating clocks, wherein the working clocks of a USB transceiver module I2 and a USB transceiver module II 3 are different from the working clock of the FPGA chip 1, and the working clock frequency of the FPGA signal processing and coordinating module 12 is at least 2 times of the working clock frequency of the USB transceiver module I2 and the USB transceiver module II 3 in consideration of the correctness of monitored and acquired data; in order to ensure that the working clock of the FPGA chip 1 and the working clocks of the USB transceiver module I2 and the USB transceiver module II 3 are synchronous, namely the working clock of the FPGA signal processing and coordinating module 12 jumps for 2 times, and the working clocks of the USB transceiver module I2 and the USB transceiver module II 3 jumps for 1 time; meanwhile, the working clocks of the FPGA chip 1 and the DDR3SDRAM 4 are also coordinated;
copying the sending data, copying the effective data in the data flowing in from the USB transceiver module I2 according to the direction and the judgment of the effective data, wherein one of the two data is sent to the USB transceiver module II 3 and completes the data sending to the PC, and the other data is sent to the DDR3SDRAM memory 4 for temporary storage;
judging the flow direction of the data, because the fixed USB transceiver module II 3 is connected with the PC, the copying of the data received by the USB transceiver module II 3 can be directly omitted from the aspect of judging the flow direction of the data, thereby reducing the copied data and lightening the working pressure of a chip;
judging valid data, wherein the data received by the USB transceiver module II 3 are not all useful, and in the data copying process of the invention, signals of handshaking, equipment enumeration and the like of a USB interface do not need to be copied, and the establishment of communication is realized, so that the signals for establishing communication can be removed according to the judgment of the type of the data;
after judging the valid data, the valid data is copied and sent to the USB transceiver module II 3, and simultaneously, the data is copied and sent to the DDR3SDRAM 4 for temporary storage;
on the premise that the back-end circuit is ready, the data of the DDR3SDRAM 4 is read out and sent to the data forwarding module 11, and the sending of the original data from the DDR3SDRAM 4 to the back-end circuit 5 is completed.
The back-end circuit 5 is a data processing circuit connected to the FPGA chip 1 and connected to the data forwarding module 11, and processes data monitored from the USB line. The processing mode and method are not fixed, and real-time processing is carried out according to actual data requirements. For example, for some image data to be displayed in real time, the back-end circuit may be designed as a real-time image display circuit; or to process the image data by using the lucky algorithm, a module capable of performing the lucky algorithm on the image is needed on the back-end circuit. Meanwhile, in order to expand the adaptation of the interface used by the back-end circuit, the communication protocol used by the back-end circuit is not explicitly required, and the communication protocol can be a network cable interface, a USB interface and the like, and the back-end circuit is matched according to the actual use condition.
The invention has the beneficial effects that:
1. under the condition that a PC or other signal analysis instruments are inconvenient to use, the scheme of the invention can be used when the data on a USB bus needs to be known specifically, and the data needs to be analyzed and temporarily stored for forwarding.
2. The invention uses FPGA to transfer, and can unpack, store and forward the data on the USB bus without using PC machine after accessing the USB transmission line, thereby realizing the non-invasive USB data real-time monitoring and collection from the data aspect;
3. the invention can send the temporarily stored data to other equipment for further analysis and use through the back-end circuit;
4. besides simple and easy-to-use equipment, the invention has much lower cost than equipment with similar functions such as a protocol analyzer and the like; after the device is designed into a mature device, the portability and the practicability can be increased;
5. the system has the advantages of portability, low cost, good universality and the like, and can play a better role than a PC (personal computer) under a proper condition.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a flow chart of data transfer between the ULPI transceiver side and the link side of the present invention; the data transmission is divided into two situations of transmission from a link end to an ULPI transceiver end and transmission from the ULPI transceiver end to the link end, and the states of the signal DIR are different according to different transmission directions.
The respective reference numerals in fig. 1: the device comprises a 1-FPGA chip, a 2-USB transceiver module I, a 3-USB transceiver module II, a 4-DDR3SDRAM memory, a 5-back-end circuit, a 6-ULPI data transceiver module I, a 7-ULPI data transceiver module II, an 8-ULPI control module I, a 9-ULPI control module II, a 10-data temporary storage module, an 11-data forwarding module and a 12-FPGA signal processing and coordinating module.
Detailed Description
The invention is further described with reference to the following figures and specific examples.
Example 1: as shown in fig. 1-2, a USB data real-time monitoring system based on FPGA includes an FPGA chip 1, a USB transceiver module i 2, a USB transceiver module ii 3, and a DDR3SDRAM memory 4;
the FPGA chip 1 includes: an ULPI data transceiver module I6, an ULPI data transceiver module II 7, an ULPI control module I8, an ULPI control module II 9, a data temporary storage module 10 and an FPGA signal processing and coordinating module 12;
the FPGA chip 1 is connected with a USB transceiver module I2, a USB transceiver module II 3 and a DDR3SDRAM memory 4; the USB transceiver module I2 and the USB transceiver module II 3 are connected to the FPGA chip 1 through different I/O ports, and the USB transceiver module I2 is connected with the FPGA signal processing and coordinating module 12 through an ULPI data transceiver module I6 and an ULPI control module I8; the FPGA signal processing and coordination module 12 is connected with the DDR3SDRAM memory 4 through the data temporary storage module 10, and the FPGA signal processing and coordination module 12 is connected with the USB transceiver module II 3 through the ULPI data transceiver module II 7 and the ULPI control module II 9.
The FPGA chip 1 further comprises a data forwarding module 11 and a back-end circuit 5; the data forwarding module 11 is connected to the back-end circuit 5, the FPGA signal processing and coordinating module 12 is connected to the data forwarding module 11 for sending the data read from the DDR3SDRAM memory 4 to the back-end circuit 5 through the data forwarding module 11, and the type of the communication protocol of the connection port are determined by the communication protocol or the interface of the back-end circuit 5.
The back-end circuit 5 employs a real-time image display circuit or a module capable of performing lucky algorithm processing on images.
After the USB transceiver module I2 receives data, the data signals are translated into data signals conforming to an ULPI protocol by a USB3320 chip, the data signals are transmitted to an FPGA signal processing and coordinating module 12 by cooperating with an ULPI control module I8 and an ULPI data transceiver module I6, the ULPI data transceiver module I6 restores the received signals into original signals, the original signals are copied and forwarded by the FPGA signal processing and coordinating module 12, one copy of the copied data is stored in a DDR3SDRAM memory 4 through a data temporary storage module 10, the other copy of the copied data is translated into ULPI signals through an ULPI data transceiver module II 7 and transmitted to a USB transceiver module II 3, and then the ULPI signals are transmitted to a PC.
The mode of the USB transceiver module I2 when connected with equipment at two ends is selectable through the ULPI control module I8; when the equipment connected with the USB transceiver module I2 is host equipment, the USB transceiver module I2 is set to work in a slave equipment mode through the ULPI control module I8; when the device connected with the USB transceiver module i 2 is a standard USB device, the USB transceiver module i 2 operates in the OTG mode, that is, the USB transceiver module i 2 serves as a host.
The data received by the USB transceiver module I2 is preferentially ensured to be transmitted to the USB transceiver module II 3 through the FPGA chip 1 and then transmitted to the PC machine through the FPGA signal processing and coordination module 12 in the FPGA chip 1 so as to restore a USB data transmission line; secondly, the monitored data is temporarily stored and forwarded; the flow judgment of the USB data, the real-time data monitoring and unloading and the establishment of the USB communication are all completed by the FPGA signal processing and coordinating module 12.
The core chip used by the FPGA chip 1 is an XC6SLX16-FTG256 chip of the Spartan6 series of Xilinx company; the DDR3SDRAM is a MT41J128M16HA-15E256MB DDR3 memory chip of the magnesium optical company; the USB transceiver module I2 and the USB transceiver module II 3 are identical in structure and respectively comprise a USB3320 chip and a USB interface.
A USB data real-time monitoring method based on FPGA, USB transceiver module I2 connects to the readable device, according to the type of the readable device, through ULPI control module I8 sets USB transceiver module I2 to different modes to realize the communication of both sides based on USB protocol;
according to the USB communication protocol, after the USB transceiver module I2 receives the transmitted data, the USB transceiver module I2 translates the data packet of the USB into a signal which accords with the ULPI protocol, and then the signal is sent to the FPGA signal processing and coordinating module 12 in the FPGA chip 1 through the ULPI protocol for temporary storage and forwarding; one copy of the copied data is stored in a DDR3SDRAM memory 4 through a data temporary storage module 10, the other copy of the copied data is translated into an ULPI signal through an ULPI data transceiver module II 7 and sent to a USB transceiver module II 3, then the ULPI signal is sent to a PC to restore a USB data transmission line, and the temporarily stored data is sent to a back-end circuit 5 through a data forwarding module 11.
The readable device comprises a USB flash disk or a PC; when the readable device is a USB flash disk, according to the USB communication protocol and the functions of the USB transceiver module I2, the USB transceiver module I2 is set to be in a host mode through the ULPI control module I8, the readable device USB flash disk works as a slave device, and communication on two sides is achieved based on the USB protocol;
when the readable device is a PC, according to the USB communication protocol and the functions of the USB transceiver module I2, the USB transceiver module I2 is set to be in a device mode through the ULPI control module I8, the readable device PC works as a host, and communication on two sides is achieved based on the USB protocol.
Further, in this example, the circuitry and peripherals are connected as follows: the back-end circuit 5 is a real-time processing display circuit, the USB transceiver module I2 is connected to a USB flash disk, and the USB transceiver module II 3 is connected to a PC. The realized functions are as follows: after the USB flash disk is connected to the USB transceiver module I2, the PC connected to the USB transceiver module II 3 can read image data on the USB flash disk, and meanwhile, the real-time processing display circuit at the rear end can display a result image after image processing in transmission is finished after the real-time processing of the image is finished.
USB transceiver module II 3 does from equipment connection to PC, works under the slave unit mode, and USB transceiver module I2 connects the USB flash disk, works under the host computer mode, and USB transceiver module II 3 uses the A type interface of USB transceiver module to be connected with PC, and USB transceiver module I2 uses the Micro B type interface of USB transceiver module to be connected with the USB flash disk. Because the interface that the USB flash disk plug corresponds is the A type interface, so need the adapter to accomplish this work.
According to the communication protocol of USB2.0, the USB transceiver module I2 establishes communication connection with the USB flash disk, the USB transceiver module II 3 establishes communication connection with the PC, and device enumeration and transmission speed determination are completed. And starting data transmission, wherein data request data of the PC flows into the FPGA signal processing and coordinating module 12 from the USB transceiver module II 3 through the ULPI data transceiver module II 7, the FPGA signal processing and coordinating module 12 directly forwards a command of the request data to the USB transceiver module I2, and the USB transceiver module I2 transmits the command to the USB flash disk, and the USB flash disk responds to the data request and starts to send image data in the USB flash disk to the FPGA chip 1. The returned data firstly reach the USB transceiver module I2 and then reach the FPGA chip 1. After the FPGA signal processing and coordination module 12 judges that the image data is effective data flowing from the USB transceiver module I2, the data is copied, meanwhile, the original data is sent to the USB transceiver module II 3, and then the USB transceiver module II 3 sends the data to the PC, so that the data transmission work of the original USB bus is completed. The copied data is sent to the DDR3SDRAM memory 4 and the temporary storage is completed.
After the back-end real-time processing display circuit is accessed, according to the data request of the back-end circuit 5, the FPGA signal processing and coordinating module 12 calls the original image data temporarily stored in the DDR3SDRAM 4, and sends the original image data to the back-end real-time processing display circuit from the data forwarding module 11, and the real-time processing and display are completed.
In the invention, the principle of data transmission of image data between the ULPI transceiver end and the FPGA chip 1 is as follows:
for the USB transceiver module I2 and the USB transceiver module II 3 both belong to the ULPI transceiver end, the ULPI data transceiver module I6 and the ULPI control module I8 also belong to the link end I, and the ULPI data transceiver module II 7 and the ULPI control module II 9 belong to the link end II.
After the communication connection is established, the USB flash disk receives the data request, starts to send data to the USB transceiver module I2, and then converts the data into data of the ULPI protocol to send to the FPGA chip 1 under the work of the USB 3320. Firstly, the STP signals of the USB transceiver module I2 and the ULPI control module I8 are inquired to be kept in an original state for more than two cycles, no data is transmitted on a bus, and data transmission is started. ULPI control module I8 detects that data is sent from ULPI transceiver end USB transceiver module I2 to link end I, pulls up DIR signals, and ULPI data transceiver module I6 restores data transmitted from 8-bit data lines back to original image data according to a protocol. After the data transmission is finished, the STP keeps the level of the last bit of the image data, and the transmission from the USB flash disk to the FPGA chip 1 is finished. And after the data is detected to be transmitted from the FPGA chip 1 to the PC, the USB transceiver module II 3 is transmitted from the link end II to the ULPI transceiver end, the DIR signal is firstly pulled down or kept at a low level after the inquiry bus is not occupied, the original image data is put on an 8-bit data bus, and the original image data is transmitted to the USB3320 chip according to the clock period and the NXT signal. And the USB3320 chip translates ULPI protocol data into USB protocol score checking data and sends the USB protocol score checking data to the PC. And finishing the signal judgment of the whole data transmission flow.
Example 2: as shown in fig. 1-2, a system and a method for real-time monitoring USB data based on FPGA includes the same embodiment as embodiment 1, wherein further:
in this example, the back-end circuit 5 is an FPGA-based astronomical real-time lucky imaging system, with the USB transceiver module i 2 connected to a CCD camera. The function of realization is, can make the PC who connects on USB transceiver module II 3 can receive the astronomical image that the CCD camera was shot, and the real-time processing circuit of rear end can be real-time to the image processing with the lucky imaging algorithm of transmitting past, obtains the result at last.
The USB transceiver module II 3 is connected to the PC through slave equipment and works in a slave equipment mode, namely the USB transceiver module II 3 is connected with the PC through an A-type interface; the USB transceiver module I2 is connected with the CCD camera, works in a host mode, and is connected with a Micro B type interface of the USB transceiver module I2.
Data request data of the PC flows into the FPGA chip 1 from the USB transceiver module II 3, and then is transmitted to the CCD camera through the USB transceiver module I2, and returned data firstly reach the USB transceiver module I2. The data are sent to an ULPI data transceiver module I6 from a USB3320 chip in a USB transceiver module I2, and after the data are packed and unpacked, the FPGA chip 1 temporarily stores the astronomical image data into a DDR3SDRAM memory 4 through a data temporary storage module 10 after receiving the astronomical image data; meanwhile, the image data is sent back to the PC through the USB transceiver module II 3. The embodiment can comprehensively realize real-time lucky imaging algorithm processing on the astronomical image on the premise of not generating interference on original data transmission, and can display the high-resolution image of the astronomical target in real time. An ULPI control module I8, an ULPI data transceiver module I6, an ULPI control module II 9 and an ULPI data transceiver module II 7 respectively coordinate and control data transceiving of a USB transceiver module I2 and a USB transceiver module II 3; the FPGA signal processing and coordination module 12 handles data replication and forwarding.
After the astronomical real-time lucky imaging system based on the FPGA at the back end is accessed, according to a data request of a back end circuit, the FPGA signal processing and coordinating module 12 calls original image data temporarily stored in the DDR3SDRAM 4, the original image data is sent to the astronomical real-time lucky imaging system based on the FPGA at the back end from the data forwarding circuit 11, and after the system finishes real-time processing on a high-resolution image of an astronomical target, display is finished through a display device.
In the invention, the principle of data transmission of the astronomical high-resolution image between the ULPI transceiver end and the FPGA chip 1 is as follows:
for the USB transceiver module I2 and the USB transceiver module II 3 both belong to the ULPI transceiver end, the ULPI data transceiver module I6 and the ULPI control module I8 also belong to the link end I, and the ULPI data transceiver module II 7 and the ULPI control module II 9 belong to the link end II.
After the communication connection is established, the CCD camera receives the data request, starts to transmit data to the USB transceiver module i 2, and then converts the data into data of the ULPI protocol to transmit to the FPGA chip 1 under the operation of the USB3320 in the USB transceiver module i 2. Firstly, the STP signals of the USB transceiver module I2 and the ULPI control module I8 are inquired to be kept in an original state for more than two cycles, no data is transmitted on a bus, and data transmission is started. ULPI control module I8 detects that data is sent from ULPI transceiver end USB transceiver module I2 to link end I, pulls up DIR signals, and ULPI data transceiver module I6 restores the data transmitted from the 8-bit data line back to the original astronomical high-resolution image according to the protocol. After the data transmission is finished, the STP keeps the level of the last bit of the image data, and the transmission from the CCD camera to the FPGA chip 1 is finished. And (3) data transmission from the FPGA chip 1 to the PC detects that data is transmitted from the link end II to the USB transceiver module II 3 of the ULPI transceiver end, after the inquiry bus is not occupied, firstly pulls down or keeps the DIR signal at a low level, puts astronomical high-resolution image data on an 8-bit data bus, and transmits the astronomical high-resolution image data to the USB3320 chip of the USB transceiver module II 3 according to a clock period and the NXT signal. And the USB3320 chip is used for translating ULPI protocol data into differential data of a USB protocol and transmitting the differential data to the PC. And finishing the signal judgment of the whole data transmission flow.
While the present invention has been described in detail with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, and various changes and modifications can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.
Claims (8)
1. The utility model provides a USB data real-time monitoring system based on FPGA which characterized in that: the device comprises an FPGA chip (1), a USB transceiver module I (2), a USB transceiver module II (3) and a DDR3SDRAM memory (4);
the FPGA chip (1) comprises: the system comprises an ULPI data transceiver module I (6), an ULPI data transceiver module II (7), an ULPI control module I (8), an ULPI control module II (9), a data temporary storage module (10) and an FPGA signal processing and coordinating module (12);
the FPGA chip (1) is connected with a USB transceiver module I (2), a USB transceiver module II (3) and a DDR3SDRAM memory (4); the USB transceiver module I (2) and the USB transceiver module II (3) are connected to the FPGA chip (1) through different I/O ports, and the USB transceiver module I (2) is connected with the FPGA signal processing and coordinating module (12) through the ULPI data transceiver module I (6) and the ULPI control module I (8); the FPGA signal processing and coordinating module (12) is connected with a DDR3SDRAM memory (4) through a data temporary storage module (10), and the FPGA signal processing and coordinating module (12) is connected with a USB transceiver module II (3) through an ULPI data transceiver module II (7) and an ULPI control module II (9);
after the USB transceiver module I (2) receives data, the data is translated into data signals conforming to an ULPI protocol by a USB3320 chip, the data signals are transmitted to an FPGA signal processing and coordinating module (12) in cooperation with an ULPI control module I (8) and an ULPI data transceiver module I (6), the ULPI data transceiver module I (6) restores the received signals into original signals, the original signals are copied and forwarded by the FPGA signal processing and coordinating module (12), one copy of the copied data is stored in a DDR3SDRAM memory (4) through a data temporary storage module (10), the other copy of the copied data is translated into ULPI signals through an ULPI data transceiver module II (7) and transmitted to a USB transceiver module II (3), and then the ULPI signals are transmitted to a PC.
2. The FPGA-based USB data real-time monitoring system according to claim 1, wherein: the FPGA chip (1) further comprises a data forwarding module (11) and a back-end circuit (5); the data forwarding module (11) is connected with the back-end circuit (5), the FPGA signal processing and coordination module (12) is connected with the data forwarding module (11) and used for sending data read from the DDR3SDRAM memory (4) to the back-end circuit (5) through the data forwarding module (11), and the type of a connection port are determined by a communication protocol or an interface of the back-end circuit (5).
3. The FPGA-based USB data real-time monitoring system of claim 2, wherein: the back-end circuit (5) adopts a real-time image display circuit or a module capable of carrying out lucky algorithm processing on images.
4. The FPGA-based USB data real-time monitoring system according to claim 1, wherein: the mode of the USB transceiver module I (2) is selectable through the ULPI control module I (8) when the USB transceiver module I (2) is connected with equipment at two ends; when the equipment connected with the USB transceiver module I (2) is host equipment, the USB transceiver module I (2) is set to work in a slave equipment mode through the ULPI control module I (8); when the device connected with the USB transceiver module I (2) is a standard USB device, the USB transceiver module I (2) works in an OTG mode, namely the USB transceiver module I (2) is used as a host.
5. The FPGA-based USB data real-time monitoring system according to claim 1, wherein: the data received by the USB transceiver module I (2) is preferentially ensured to be transmitted to the USB transceiver module II (3) through the FPGA chip (1) and then transmitted to the PC machine through the FPGA signal processing and coordination module (12) in the FPGA chip (1) so as to restore a USB data transmission line; secondly, the monitored data is temporarily stored and forwarded; the flow judgment of the USB data, the real-time data monitoring and unloading and the establishment of the USB communication are all completed by an FPGA signal processing and coordinating module (12).
6. The FPGA-based USB data real-time monitoring system according to claim 1, wherein: the core chip used by the FPGA chip (1) is an XC6SLX16-FTG256 chip of the Spartan6 series of Xilinx company; the DDR3SDRAM is a MT41J128M16HA-15E256MB DDR3 memory chip of magnesium optical company; the USB transceiver module I (2) and the USB transceiver module II (3) are identical in structure and respectively comprise a USB3320 chip and a USB interface.
7. A USB data real-time monitoring method based on FPGA is characterized in that: the USB transceiver module I (2) is connected to the readable device, and the USB transceiver module I (2) is set to be in different modes through the ULPI control module I (8) according to the type of the readable device, so that communication between two sides is achieved based on a USB protocol;
according to a USB communication protocol, after the USB transceiver module I (2) receives transmitted data, the USB transceiver module I (2) translates a USB data packet into a signal conforming to an ULPI protocol, and then the signal is sent to an FPGA signal processing and coordinating module (12) in the FPGA chip (1) through the ULPI protocol for temporary storage and forwarding; one copy of the copied data is stored in a DDR3SDRAM memory (4) through a data temporary storage module (10), the other copy of the copied data is translated into an ULPI signal through an ULPI data transceiver module II (7) and is sent to a USB transceiver module II (3), then the ULPI signal is sent to a PC to restore a USB data transmission line, and the temporarily stored data is sent to a back-end circuit (5) through a data forwarding module (11).
8. The FPGA-based USB data real-time monitoring method according to claim 7, wherein: the readable device comprises a USB flash disk or a PC; when the readable device is a USB flash disk, according to the USB communication protocol and the functions of the USB transceiver module I (2), the USB transceiver module I (2) is set to be in a host mode through the ULPI control module I (8), the readable device USB flash disk works as a slave device, and communication on two sides is achieved based on the USB protocol;
when the readable device is a PC, according to the USB communication protocol and the function of the USB transceiver module I (2), the USB transceiver module I (2) is set to be in a device mode through the ULPI control module I (8), and the readable device PC works as a host to realize communication on two sides based on the USB protocol.
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