CN109347614B - Different fractional order hyperchaotic system circuit - Google Patents
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Abstract
The invention relates to a fractional order hyperchaotic system and a signal generating circuit thereof, which are required in chaotic traffic flow control and chaotic secret communication. The four-dimensional different fractional order hyperchaotic system mathematical model is as follows:
where x, y, z and w are four state variables and a, m, b, c, d and r are system parameters. The system has the advantages that the Lyapunov exponent is positive, negative and zero, the system is a typical hyperchaotic system, more complex chaotic dynamics behaviors are realized, the system has different orders, is more in line with an actual physical model, a circuit is simple to realize, integration is convenient, and the system has high application value in secret communication and traffic flow control.
Description
Technical Field
The invention relates to a four-dimensional hyper-chaotic system with different fractional orders and a realization circuit, belonging to the technical field of chaotic signal generator circuit design.
Background
The differential-fraction order hyperchaotic system can more accurately describe the actual chaotic dynamic system, has more complex dynamic characteristics and better pseudo-randomness, can enhance the safety of chaotic secret communication, and is more suitable for the chaotic control of complex road traffic flow.
The chaotic signal generator circuit is a basic condition for applying chaotic science to the technical field of engineering, the existing fractional order signal generators are chaotic systems of the same order, and rarely relate to different fractional order chaotic systems and hyperchaotic fractional order systems, and the simple analog device is used for realizing the different fractional order hyperchaotic signal generator to lay a foundation for chaotic engineering application, so that the chaotic signal generator circuit has good application value.
Disclosure of Invention
The invention aims to provide a different-fractional order hyperchaotic system and a realization circuit, the system is more in line with the actual physical structure, the circuit parameters are easy to allocate, and the generated hyperchaotic signals have stronger pseudo-randomness.
The technical scheme adopted by the invention is as follows:
1. the four-dimensional different fractional order hyperchaotic system (i) is characterized in that:
in the formula (i), x, y, z and w are four state variables, a, m, b, c, d and r are parameters, a is 27, m is 20, b is 3, c is 25, d is 7, and r is 0.1.
The system (i) is a fractional order hyperchaotic system with Lyapunov exponent of positive, negative and zero.
Carrying out variable substitution on state variables x, y, z and w of the system (i), and enabling x to be 10uc1,y ＝10uc2,z＝10uc3,w＝10uc4, the following steps are included:
performing a time transformation
Comprises the following steps:
the system (iii) is:
designing the circuit implementation equation of system (i) by (iv):
in order to match the corresponding parameters of system (v) and system (iv), in system (v), R ═ R4＝R9＝R13＝R16，Rf2＝R3＝R4＝R8＝R9＝R12＝R13＝R14＝R15＝R16＝10kΩ， Rf1＝5kΩ，R1＝2.9kΩ，R5＝14.3kΩ,R6＝4kΩ,R7＝R10＝1kΩ,R11＝ 33.3kΩ，C0＝C＝10nF。
2. A circuit of the heterogeneous fractional order hyper-chaotic system signal generation circuit is realized by four channel circuits, wherein the first channel circuit consists of an operational amplifier A1, an operational amplifier A2, a 0.8-order link fractional order inverse integrator A3, a resistor R1, a resistor Rf1, a resistor R3, a resistor R2, a resistor Rf2 and a resistor R4, the second channel circuit consists of a multiplier AD1, an operational amplifier A4, a 0.9-order tree fractional order inverse integrator A5, a resistor R5, a resistor R6 and a resistor R7, the circuit comprises a resistor R8 and a resistor R9, a third channel circuit comprises a multiplier AD2, an operational amplifier A6, a 0.9-order tree-type fractional order inverse integrator A7, an inverter A8, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R17 and a resistor R18, and a fourth channel circuit comprises a multiplier AD3, an inverter A9, a 0.9-order tree-type fractional order inverse integrator A10, a resistor R14, a resistor R15 and a resistor R16.
An output signal uc1 of the first channel circuit is connected to a resistor R2, acts as an input signal of the first channel on the non-inverting input terminal of the operational amplifier a2 in the first channel circuit, the output signal uc1 is connected to a resistor R5 as an input signal of the second channel, acts on the inverting input terminal of the operational amplifier a4 in the second channel circuit, the output signal is connected to a multiplier AD1 and a resistor R7 as an input signal of the second channel, acts on the inverting input terminal of the operational amplifier a4 in the second channel circuit, the output signal is connected to an AD multiplier 2 and a resistor R10 as an input signal of the third channel, acts on the inverting input terminal of the operational amplifier A6 in the third channel circuit, and the output signal is connected to an AD multiplier AD3 and a resistor R14 as an input signal of the fourth channel, and acts on the inverting input terminal of the operational amplifier a9 in the fourth channel.
The output signal uc2 of the second channel circuit is connected with the resistor R1 as the input signal of the first channel, acts on the non-inverting input end of the operational amplifier A1 in the first channel circuit, the output signal is connected with the resistor R6 as the input signal of the second channel, acts on the inverting input end of the operational amplifier A4 in the second channel circuit, the output signal is connected with the multiplier AD2 and the resistor R10 as the input signal of the third channel, and acts on the inverting input end of the operational amplifier A6 in the third channel circuit.
An output signal uc3 of the third channel circuit is connected with a multiplier AD3 and a resistor R14 to serve as an input signal of a fourth channel and acts on an inverting input end of an operational amplifier A9 in the fourth channel circuit, the output signal is connected with an inverter A8 and then becomes a-uc 3 signal, a uc3 signal is connected with the multiplier AD1 and the resistor R7 to serve as an input signal of a second channel and acts on an inverting input end of an operational amplifier A4, and a uc3 signal is connected with a resistor R11 to serve as an input signal of a third channel and acts on an inverting input end of the operational amplifier A6.
The fourth channel output signal is uc 4.
Except A1 and A2, the same phase ends of all the operational amplifiers in the four channels are grounded, the negative port of the power supply of all the operational amplifiers is connected with-12V voltage, and the positive port of the power supply of the operational amplifiers is connected with 12V voltage.
The addition and subtraction operation of the uc1 signal and the uc2 signal is realized by a two-stage operational amplifier, a uc1 signal connection resistor R2 in a first channel is connected to the non-inverting input end of an operational amplifier A2, and a uc2 signal connection resistor R1 is connected to the non-inverting input end of an operational amplifier A1.
The resistor R41 is connected with the capacitor C1 in parallel, the resistor R42 is connected with the capacitor C2 in parallel, the resistor R43 is connected with the capacitor C3 in parallel, the resistor R44 is connected with the capacitor C4 in parallel, the resistor R45 is connected with the capacitor C5 in parallel, and the five circuits are sequentially connected in series to form a 0.8-order link type fractional order unit and are respectively connected to the inverting input end of the operational amplifier A3 and the output end uc1 of the first channel.
The resistor R47 and the capacitor C7 are connected in parallel and then connected in series with the resistor R46, the resistor R48 and the capacitor C8 are connected in parallel and then connected in series with the capacitor C6, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit which is connected to the inverting input end of the operational amplifier A5 and the two ends of the second output signal uc 2.
The resistor R50 and the capacitor C10 are connected in parallel and then connected in series with the resistor R49, the resistor R51 and the capacitor C11 are connected in parallel and then connected in series with the capacitor C9, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit which is connected to the inverting input end of the operational amplifier A7 and two ends of the third output signal uc 3.
The resistor R53 and the capacitor C13 are connected in parallel and then connected in series with the resistor R52, the resistor R54 and the capacitor C14 are connected in parallel and then connected in series with the capacitor C12, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit which is connected to the inverting input end of the operational amplifier A10 and the two ends of the fourth output signal uc 4.
The invention has the beneficial effects that: the four-dimensional different fractional order hyper-chaotic system and the implementation circuit thereof are provided, the type of the chaotic system is increased, and a foundation is laid for the application of the chaotic system.
Compared with an integer order chaotic system, the fractional order hyperchaotic system has more complex dynamic characteristics and stronger signal pseudo-randomness, and the orders of the system are different, namely 0.8 order and 0.9 order, so that the fractional order hyperchaotic system is more in line with an actual physical system model.
The invention has the advantages that: the input signal of the first channel is composed of two-stage operational amplifiers, compared with the resistance of a single operational amplifier, the selection and adjustment are convenient, meanwhile, for two input signals uc1 and uc2, the input resistance is large, the current required for the signals is small, and the generation of chaotic signals is facilitated.
Drawings
Fig. 1 is a circuit diagram of a heterofractional order hyper-chaotic signal generator of the present invention.
FIG. 2 is a diagram of the system bifurcation and the corresponding maximum Lyapunov exponent as a function of the parameter b for the system (i) of the present invention.
FIG. 3 is a diagram of the system bifurcation and the corresponding maximum Lyapunov exponent as a function of the parameter m for the system (i) of the present invention.
FIG. 4 is a Lyapunov exponent diagram for system (i) of the present invention.
FIG. 5 is a two-dimensional simulated phase diagram of system (i) of the present invention. Wherein FIG. 5(a) is an x-z plane phase diagram and FIG. 5(b) is a y-z plane phase diagram.
FIG. 6 is a circuit diagram of the system of the present invention (v). Wherein FIG. 6(a) is a plan phase diagram of uc1-uc3, and FIG. 6(b) is a plan phase diagram of uc2-uc 3.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The invention adopts the following technical means to realize the purpose of the invention:
1. constructing a new four-dimensional different fractional order hyperchaotic system:
in the formula, x, y, z and w are four state variables, a, m, b, c, d and r are parameters, a is 27, m is 20, b is 3, c is 25, d is 7, and r is 0.1.
From the two-dimensional simulation of the system (i) shown in fig. 4, the variable range is beyond the linear region of the operational amplifier, so that the state variables x, y, z and w of the system (i) are replaced by the variables, and x is 10uc1,y＝10uc2,z＝10uc3,w＝10uc4, the following steps are included:
for the convenience of circuit realization, the time is compressed and changed, and the order is changed
Comprises the following steps:
the system (iii) is:
designing the circuit implementation equation of system (i) by (iv):
in order to match the corresponding parameters of system (v) and system (iv), in system (v), R ═ R4＝R9＝R13＝R16，Rf2＝R3＝R4＝R8＝R9＝R12＝R13＝R14＝R15＝R16＝10kΩ， Rf1＝5kΩ，R1＝2.9kΩ，R5＝14.3kΩ,R6＝4kΩ,R7＝R10＝1kΩ,R1133.3k Ω. Wherein C is0Is a parameter unit, C0＝C＝10nF。
2. Fig. 1 shows a differential-fractional order hyperchaotic signal generator circuit, the circuit experiment is carried out on Multisim 14.0, the circuit is composed of four channel circuits, and the first, second, third and fourth channel circuits respectively realize four functions of uc1, uc2, uc3 and uc4 of system ii.
The first channel circuit consists of an operational amplifier A1, a 0.8-order link type fractional order inverse integrator A1, a resistor R1, a resistor Rf1, a resistor R1, a resistor Rf1 and a resistor R1, the second channel circuit consists of a multiplier AD1, an operational amplifier A1, a 0.9-order tree type fractional order inverse integrator A1, a resistor R1 and a resistor R1, the third channel circuit consists of a multiplier AD1, an amplifier A1, a 0.9-order tree type fractional order inverse integrator A1, an inverter A1, a resistor R1 and a resistor R1, and a fourth channel circuit consists of a multiplier AD1, an inverter A1, a 0.9-order fractional order inverse integrator A1, a resistor R1 and a resistor R1; an output signal uc1 of the first channel circuit is connected with a resistor R2, acts on a non-inverting input terminal of an operational amplifier A2 in the first channel circuit as an input signal of the first channel, is connected with a resistor R5 as an input signal of the second channel, acts on an inverting input terminal of an operational amplifier A4 in the second channel circuit, is connected with a multiplier AD1 and a resistor R7 as an input signal of the second channel, acts on an inverting input terminal of an operational amplifier A4 in the second channel circuit, is connected with the multiplier AD2 and a resistor R10 as an input signal of the third channel, acts on an inverting input terminal of the operational amplifier A6 in the third channel circuit, and is connected with the multiplier AD3 and the resistor R14 as an input signal of the fourth channel, and acts on an inverting input terminal of the operational amplifier A9 of the fourth channel; an output signal uc2 of the second channel circuit is connected with a resistor R1 as an input signal of the first channel and acts on a non-inverting input end of an operational amplifier A1 in the first channel circuit, the output signal is connected with a resistor R6 as an input signal of the second channel and acts on an inverting input end of an operational amplifier A4 in the second channel circuit, the output signal is connected with a multiplier AD2 and a resistor R10 as an input signal of a third channel and acts on an inverting input end of an operational amplifier A6 in the third channel circuit; an output signal uc3 of the third channel circuit is connected with a multiplier AD3 and a resistor R14 to serve as an input signal of a fourth channel and acts on an inverting input end of an operational amplifier A9 in the fourth channel circuit, the output signal is connected with an inverter A8 and then becomes a-uc 3 signal, a uc3 signal is connected with the multiplier AD1 and the resistor R7 to serve as an input signal of a second channel and acts on an inverting input end of an operational amplifier A4, and a uc3 signal is connected with a resistor R11 to serve as an input signal of the third channel and acts on an inverting input end of the operational amplifier A6; the fourth channel output signal is uc 4.
In the differential-fractional order hyperchaotic circuit, an operational amplifier adopts TL082, a multiplier adopts AD633 with the gain of 0.1, and a linear resistor and a capacitor are selected.
Except A1 and A2, the same phase ends of all the operational amplifiers in the four channels are grounded, the negative port of the power supply of all the operational amplifiers is connected with-12V voltage, and the positive port of the power supply of the operational amplifiers is connected with 12V voltage.
As shown in fig. 1, a 0.8-order fractional order circuit unit resistor R41 is connected in parallel with a capacitor C1, a resistor R42 is connected in parallel with a capacitor C2, a resistor R43 is connected in parallel with a capacitor C3, a resistor R44 is connected in parallel with a capacitor C4, and a resistor R45 is connected in parallel with a capacitor C5, and these five groups of circuits are connected in series in sequence to form a 0.8-order link-type fractional order unit, which is respectively connected to the inverting input terminal of the operational amplifier A3 and the output terminal uc1 of the first path.
The R41 ═ 37.85M Ω, R42 ═ 1.754M Ω, R43 ═ 0.17M Ω, R44 ═ 0.017M Ω, R45 ═ 0.0018M Ω, C1 ═ 1.98 μ F, C2 ═ 2.4 μ F, C3 ═ 1.39 μ F, C4 ═ 780nF, and C5 ═ 420 nF.
As shown in fig. 1, the resistor R47 and the capacitor C7 are connected in parallel and then connected in series with the resistor R46, the resistor R48 and the capacitor C8 are connected in parallel and then connected in series with the capacitor C6, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit, which is connected to the inverting input terminal of the operational amplifier a5 and the two ends of the second output signal uc 2.
The resistor R50 and the capacitor C10 are connected in parallel and then connected in series with the resistor R49, the resistor R51 and the capacitor C11 are connected in parallel and then connected in series with the capacitor C9, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit which is connected to the inverting input end of the operational amplifier A7 and two ends of the third output signal uc 3.
The resistor R53 and the capacitor C13 are connected in parallel and then connected in series with the resistor R52, the resistor R54 and the capacitor C14 are connected in parallel and then connected in series with the capacitor C12, and then the two branches are connected in parallel to form a 0.9-order tree-type fractional order unit which is connected to the inverting input end of the operational amplifier A10 and the two ends of the fourth output signal uc 4.
R46 ═ R49 ═ R52 ═ 1.55M Ω, C6 ═ C9 ═ C12 ═ 0.73 μ F, R47 ═ R50 ═ R53 ═ 61.54M Ω, C7 ═ C10 ═ C13 ═ 0.52 μ F, R48 ═ R51 ═ R54 ═ 2.5k Ω, C8 ═ C11 ═ C14 ═ 1.1 μ F.
Fig. 2 shows a bifurcation diagram of the proposed super-system (i) along with the variation of the parameter b and a corresponding maximum lyapunov exponent diagram, and it can be seen from the diagram that when the parameter b is less than 4.5, the system is in a chaotic state, and at this time, the maximum lyapunov exponent of the system is a positive number, and the chaotic state is also satisfied.
Fig. 3 shows a bifurcation diagram of the proposed super-system (i) varying with the parameter m and a corresponding maximum lyapunov exponent diagram, and it can be seen from the diagram that when the parameter m is greater than 17.2, the system enters a chaotic state from a periodic state, and at this time, the maximum lyapunov exponent corresponding to the system is a positive number and also satisfies the chaotic state.
Figure 4 shows a representation of the lyapunov exponent corresponding to system (i) of the invention. As can be seen from the figure, the system has two positive Lyapunov indexes, one zero and one negative Lyapunov index, and the sum of the Lyapunov indexes is less than zero, which proves that the invented system (i) is a hyperchaotic system.
Figure 5 shows a corresponding numerical simulation phase diagram for system (i) of the present invention. As can be seen from the two-dimensional phase diagram, the two attractors swim around in the phase space, the two attractors are used as centers to form the double-vortex chaotic attractor, and the system is in a chaotic state.
Fig. 6 is a Multisim 14.0 circuit experimental phase diagram of the system (v) of the present invention, and the experimental result shows that the designed chaotic signal generator circuit is consistent with the constructed new chaotic system (i), and the circuit design of the differential fractional order hyper-chaotic system is completed by using a simple analog circuit.
The present invention is not limited to the above embodiments, and the variations, modifications, additions and substitutions within the spirit and scope of the invention may be made by those skilled in the art.
Claims (4)
1. A different fractional order hyperchaotic system circuit is characterized by comprising the following steps:
(1) the four-dimensional different fractional order hyperchaotic system comprises:
in the formula (i), x, y, z and w are four state variables, a, m, b, c, d and r are parameters, a is 27, m is 20, b is 3, c is 25, d is 7, r is 0.1, and the system (i) is a fractional order hyper-chaotic system with the Lyapunov index of positive, negative and zero;
(2) in system (i), the state variables x, y, z and w are replaced by variables, wherein x is 10uc1, y is 10uc2, z is 10uc3, and w is 10uc 4:
(3) performing a time transformation
Comprises the following steps:
(4) the system (iii) is:
(5) designing a circuit equation from (iv)
In system (v), C ═ 10nF, R ═ R4＝R9＝R13＝R16，Rf2＝R3＝R4＝R8＝R9＝R12＝R13＝R14＝R15＝R16＝10kΩ，Rf1＝5kΩ，R1＝2.9kΩ，R5＝14.3kΩ，R6＝4kΩ，R7＝R10＝1kΩ，R11＝33.3kΩ；
(6) The heterofractional order hyperchaotic system constructed by the system (v) consists of four channel circuits, wherein the first channel circuit consists of an operational amplifier A1, an operational amplifier A2, a 0.8-order link-type fractional order inverse integrator A3, a resistor R1, a resistor Rf1, a resistor R3, a resistor R2, a resistor Rf2 and a resistor R4, the second channel circuit consists of a multiplier AD1, an operational amplifier A4, a 0.9-order tree-type fractional order inverse integrator A5, a resistor R5, a resistor R6 and a resistor R7, the third channel circuit consists of a multiplier AD2, an amplifier A6, a 0.9-order tree-type fractional order inverse integrator A7, an inverter A8, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R17 and a resistor R18, and the fourth channel circuit consists of a multiplier AD3, an inverter A9, a 0.9-order tree-type fractional order inverse integrator A10, a resistor R14, a resistor R15 and a resistor R16;
an output signal uc1 of the first channel circuit is connected with a resistor R2, acts on a non-inverting input terminal of an operational amplifier A2 in the first channel circuit as an input signal of the first channel, is connected with a resistor R5 as an input signal of the second channel, acts on an inverting input terminal of an operational amplifier A4 in the second channel circuit, is connected with a multiplier AD1 and a resistor R7 as an input signal of the second channel, acts on an inverting input terminal of an operational amplifier A4 in the second channel circuit, is connected with the multiplier AD2 and a resistor R10 as an input signal of the third channel, acts on an inverting input terminal of the operational amplifier A6 in the third channel circuit, and is connected with the multiplier AD3 and the resistor R14 as an input signal of the fourth channel, and acts on an inverting input terminal of the operational amplifier A9 of the fourth channel;
an output signal uc2 of the second channel circuit is connected with a resistor R1 as an input signal of the first channel and acts on a non-inverting input end of an operational amplifier A1 in the first channel circuit, the output signal uc2 is connected with a resistor R6 as an input signal of the second channel and acts on an inverting input end of an operational amplifier A4 in the second channel circuit, the output signal is connected with a multiplier AD2 and a resistor R10 as an input signal of a third channel and acts on an inverting input end of the operational amplifier A6 in the third channel circuit;
an output signal uc3 of the third channel circuit is connected with a multiplier AD3 and a resistor R14 to serve as an input signal of a fourth channel and acts on an inverting input end of an operational amplifier A9 in the fourth channel circuit, the output signal is connected with an inverter A8 and then becomes a-uc 3 signal, a uc3 signal is connected with the multiplier AD1 and the resistor R7 to serve as an input signal of a second channel and acts on an inverting input end of an operational amplifier A4, and a uc3 signal is connected with a resistor R11 to serve as an input signal of the third channel and acts on an inverting input end of the operational amplifier A6;
the fourth channel output signal is uc 4;
except A1 and A2, the same phase ends of all the operational amplifiers in the four channels are grounded, the negative port of the power supply of all the operational amplifiers is connected with-12V voltage, and the positive port of the power supply of the operational amplifiers is connected with 12V voltage.
2. The heterofractional order hyperchaotic system circuit of claim 1, wherein: the uc1 signal connection resistor R2 in the first channel is connected to the non-inverting input terminal of the operational amplifier A2, and the uc2 signal connection resistor R1 is connected to the non-inverting input terminal of the operational amplifier A1.
3. The heterofractional order hyperchaotic system circuit of claim 2, wherein: the resistance value of R1 is 2.9 K.OMEGA., the resistance value of Rf1 is 5 K.OMEGA., the resistance value of R2 is 10 K.OMEGA., the resistance value of R3 is 10 K.OMEGA., and the resistance value of Rf1 is 10 K.OMEGA.
4. The heterofractional order hyperchaotic system circuit of claim 1, wherein: the 0.8-order link type fractional order inverse integrator A3 comprises a 0.8-order link type fractional order unit and an operational amplifier A3, and the 0.9-order tree type fractional order inverse integrator A5 comprises a 0.9-order tree type fractional order unit and an operational amplifier A5.
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