CN109343905B

CN109343905B - PCIE resource configuration system and method

Info

Publication number: CN109343905B
Application number: CN201811167118.8A
Authority: CN
Inventors: 李纪伟; 李岩
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-10-08
Filing date: 2018-10-08
Publication date: 2021-07-06
Anticipated expiration: 2038-10-08
Also published as: CN109343905A

Abstract

The invention discloses a PCIE resource allocation system, which comprises: the system comprises a south bridge chip, an I/O Expander chip, a single-pole double-throw Switch chip and a PCIE Switch chip, wherein the south bridge chip is connected with the I/O Expander chip, the I/O Expander chip is connected with the single-pole double-throw Switch chip, the single-pole double-throw Switch chip is connected with the PCIE Switch chip, a nonvolatile memory is arranged in the I/O Expander chip, user configuration information is stored in the nonvolatile memory, the south bridge chip configures the level of an I/O port of the I/O Expander chip, which is connected with the single-pole double-throw Switch chip, according to the user configuration information, and controls the output of the single-pole double-throw Switch chip to the PCIE Switch chip, so that PCIE resources are configured through the PCIE Switch chip. The PCIE resource configuration system adopts the I/O Expander chip to replace the traditional Jumper and PCA9555 chips, can store the user configuration information in the nonvolatile memory thereof, and can keep the user configuration information from being lost after the power failure, thereby facilitating the operation of the user and reducing the design cost.

Description

PCIE resource configuration system and method

Technical Field

The present invention relates to the field of system design, and in particular, to a PCIE resource configuration system and method.

Background

In a server based on an Intel platform, each CPU supports 48 channels (Lane) at maximum, and 48 channels are sufficient for a traditional server, but with the rapid increase of the scale of the internet of things, a centralized data storage and processing mode faces bottlenecks and pressures, data processing capability and service are provided near the network edge where data is generated, and traditional PCIE allocation resources cannot meet the requirements; such a server platform has special requirements on PCIE resources, and PCIE Switch (switching) is developed to deal with the limitation of the number of channels. When the server system is configured with a plurality of chips, a user can switch the interconnection topological relation among the chips according to the actual application scene so as to meet the performance requirement.

In the prior art, to implement switching of system topologies, current server designs usually adopt a design scheme of reserving Jumper (Jumper) or PCA9555 chips. The concrete design is as follows: and leading out related Strap pins signals of the PCIE Switch chip and respectively connecting the Strap pins signals to a GPIO port of a 3-pin Jumper or a PCA9555 chip of the connector. When a user needs to change the system topology, the user can manually adjust the Jumper position to lock the default state; or the PCA9555 internal register is changed through I2C, and the Strap pin signal voltage is changed to configure the port link bandwidth of the PCIE Switch.

However, the prior art scheme using Jumper or PCA9555 chip has the following disadvantages: the existing Jumper is used for changing the topology, the Jumper falling risk exists in the falling and oscillation tests, and meanwhile, the case needs to be opened by manually adjusting the Jumper, so that the Jumper is not beneficial to the operation of customers, and is not suitable for mass production products; in addition, because the register information is lost after the power failure of the PCA9555 chip, the configuration information of a client cannot be stored, and the method is not suitable for mass production.

In view of the above drawbacks of the prior art, there is a need in the art for an alternative solution suitable for mass production, which is convenient for users to operate and reduces the design cost, instead of using the conventional Jumper or PCA9555 chip.

Disclosure of Invention

In view of this, an embodiment of the present invention provides a PCIE resource configuration system and method, which can solve the problems that in the prior art, the Jumper design is not favorable for client operations, and the register configuration information is lost due to power failure of a PCA9555 chip.

Based on the above object, an aspect of the embodiments of the present invention provides a PCIE resource allocation system, including: a south bridge chip, an I/O Expander chip (I/O expansion chip), a single-pole double-throw Switch chip and a PCIE Switch chip (PCIE switching chip), wherein the south bridge chip is connected with the I/O Expander chip, the I/O Expander chip is connected with the single-pole double-throw Switch chip, the single-pole double-throw Switch chip is connected with the PCIE Switch chip,

the I/O expansion chip is internally provided with a nonvolatile memory, user configuration information is stored in the nonvolatile memory, the south bridge chip configures the level of an I/O port connected with the I/O Expander chip and the single-pole double-throw Switch chip according to the user configuration information, and the output of the single-pole double-throw Switch chip to the PCIE Switch chip is controlled, so that PCIE resources are configured through the PCIE Switch chip.

In some embodiments, configuring PCIE resources through the PCIE Switch chip includes: and adjusting the port link bandwidth of the PCIE Switch chip.

In some embodiments, the I/O port of the I/O Expander chip is connected to the selection input pin of the single-pole double-throw Switch chip, and the output pin of the single-pole double-throw Switch chip is connected to the control pin of the PCIE Switch chip.

In some embodiments, a single pole double throw switch chip includes a first input pin and a second input pin; when the level output by the I/O port of the I/O Expander chip is high level, the output pin of the single-pole double-throw Switch chip is communicated with the first input pin, and the port link bandwidth of the PCIE Switch chip connected with the single-pole double-throw Switch chip is configured as a first bandwidth; when the level output by the I/O port of the I/O Expander chip is low level, the output pin of the single-pole double-throw Switch chip is communicated with the second input pin, and the port link bandwidth of the PCIE Switch chip connected with the single-pole double-throw Switch chip is configured to be the second bandwidth.

In some embodiments, the south bridge chip is connected to the I/O Expander chip via an I2C bus.

In some embodiments, the non-volatile memory includes at least one of: ROM, PROM, EPROM, EEPROM, or Flash.

In some embodiments, the PCIE Switch chips include at least one first-stage PCIE Switch chip and at least one second-stage PCIE Switch chip, the first-stage PCIE Switch chip is connected to the CPU, the second-stage PCIE Switch chip is connected to the first-stage PCIE Switch chip, and each second-stage PCIE Switch chip is connected to a corresponding single-pole double-throw Switch chip.

In some embodiments, each second-level PCIE Switch chip includes at least one control pin, each control pin corresponding to a port.

In some embodiments, configuring PCIE resources through the PCIE Switch chip includes: and adjusting the link bandwidth of the port of the second-stage PCIE Switch chip.

In another aspect of the embodiments of the present invention, a PCIE resource allocation method is further provided, where the method includes: and the PCIE resources are configured by utilizing the PCIE resource configuration system.

The invention has the following beneficial technical effects: the PCIE resource configuration system and the method provided by the embodiment of the invention adopt the I/O Expander chip to replace the traditional Jumper and PCA9555 chips, can store the user configuration information in the nonvolatile memory thereof, and can still keep the user configuration information from losing after the power failure, thereby facilitating the user operation, reducing the design cost and being suitable for the requirement of mass production products.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a PCIE resource allocation system architecture according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the interconnection of a south bridge chip and an I/O Expander chip of the system of FIG. 1;

FIG. 3 is a schematic diagram of the interconnection of an I/O Expander chip and a single-pole, double-throw switch chip of the system of FIG. 1;

FIG. 4 is a schematic diagram of an interconnection of a single-pole double-throw Switch chip and a PCIE Switch chip of the system shown in FIG. 1;

fig. 5 is a schematic block diagram of an embodiment of configuring PCIE resources using a PCIE resource configuration system of the present invention;

fig. 6 is a schematic block diagram of another embodiment of configuring PCIE resources using the PCIE resource configuration system of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions of "first", "second", and the like in the embodiments of the present invention are used for distinguishing two or more entities with the same name but different names or different parameters, and it is understood that "first", "second", and the like are only for convenience of description and should not be construed as limiting the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted.

Based on the foregoing objective, a first aspect of the present invention provides an embodiment of a PCIE resource configuration system. Fig. 1 is a schematic diagram illustrating an architecture of the PCIE resource allocation system.

As shown in fig. 1, the PCIE resource configuration system may include: the south bridge chip 101, the I/O Expander chip 102 with the nonvolatile memory inside, the single-pole double-throw Switch chip 103 and the PCIE Switch chip 104, wherein the south bridge chip 101 is connected with the I/O Expander chip 102, the I/O Expander chip 102 is connected with the single-pole double-throw Switch chip 103, and the single-pole double-throw Switch chip 103 is connected with the PCIE Switch chip 104. The non-volatile memory stores user configuration information, and the south bridge chip 101 may configure the level of an I/O port of the I/O Expander chip 102, which is connected to the single-pole double-throw Switch chip 103, according to the user configuration information to control the output of the single-pole double-throw Switch chip 103 to the PCIE Switch chip 104, so as to configure PCIE resources through the PCIE Switch chip 104.

The PCIE resource configuration system of the embodiment of the invention adopts the I/O Expander chip 102 with the nonvolatile memory inside to replace the traditional Jumper and PCA9555 chip, and stores the user configuration information in the nonvolatile memory, so that the user configuration information can still be kept from being lost after the power failure. On one hand, when a user changes the PCIE topology, the physical connection relation in the system does not need to be changed manually, and only the register information of the I/O Expander chip 102 needs to be changed; on the other hand, the user configuration information can still be stored after power failure, so that the user configuration information does not need to be manually reconfigured after power is powered on again. Therefore, compared with the prior art, the PCIE resource allocation system is convenient for the user to operate and can reduce the design cost.

In a preferred embodiment, configuring PCIE resources through the PCIE Switch chip includes: port Link bandwidth (Link Width) of the PCIE Switch chip is adjusted, for example, X1, X2, X4, X8, X16, and the like.

In a preferred embodiment, the non-volatile memory is a memory in which the stored data does not disappear after the current is cut off, and such a memory may include at least ROM, PROM, EPROM, EEPROM or Flash. More preferably, a serial EEPROM is selected, which can support 28KB of memory space for the user. The user configuration information is stored in the user-specific area of the EEPROM, and after the chip is powered on, all the information will be redistributed to the registers corresponding to the ports of the I/O Expander chip 102.

FIG. 2 is a schematic diagram of the interconnection between the south bridge chip 101 and the I/O Expander chip 102 of the system shown in FIG. 1. In a preferred embodiment, the south bridge chip 101 may be a PCH chip (platform controller hub) of Intel corporation, the I/O Expander chip 102 may be a CY8C9520A chip, and the CY8C9520A chip is a chip applied to GPIO (general input output) resource extension for I2C, and serves as an I2C slave device for a master device to access all ports (ports) thereof through registers. As shown in FIG. 2, south bridge chip 101 is interconnected with I/O Expander chip 102 via an I2C bus. The south bridge chip 101 configures all data pins (pins) of the I/O Expander chip 102 independently through an I2C interface, wherein the data pins comprise input/output/quasi-bidirectional input/output or PWM outputs; meanwhile, the data pin may be configured to an OD (open drain output)/OC (open collector output)/PU (pull-up)/PD (pull-down)/HI (high impedance) state, and is configured to an internal pull-up by default. The WD (write inhibit) pin of the I/O Expander chip 102 is used to control read/write operations to its internal non-volatile memory. After the system is powered on, the south bridge chip 101 may read and write the registers of the I/O Expander chip 102 through the I2C bus according to the user's needs, so as to configure the high/low state of the I/O port level.

FIG. 3 is a schematic diagram of the interconnection of the I/O Expander chip 102 and the single-pole double-throw switch chip 103 of the system shown in FIG. 1. In a preferred embodiment, the single pole double throw switch chip 103 may be an SN74LVC1G3157 chip, which is capable of handling both analog and digital signals. The VCC range of the SN74LVC1G3157 chip is 1.65V-5.5V, which is convenient for users to design, and the chip is mainly used for signal gating, chopping, modulation, demodulation and digital-to-analog/analog-to-digital conversion signal systems. As shown in FIG. 3, the select input pin of the single-pole double-throw switch chip 103 is directly interconnected with the GPIO port of the I/O Expander chip 102. The single pole double throw switch chip 103 includes a first input pin B1 and a second input pin B0. When the level of the I/O port output of the I/O Expander chip 102 to the S pin of the single-pole double-throw Switch chip 103 is high, the output pin of the single-pole double-throw Switch chip 103 is communicated with the first input pin B1, and the port link bandwidth of the PCIE Switch chip 104 connected to the single-pole double-throw Switch chip 103 is configured to be the first bandwidth (e.g., PCIE X16). When the level of the I/O port output of the I/O Expander chip 102 to the S pin of the single-pole double-throw Switch chip 103 is low, the output pin of the single-pole double-throw Switch chip 103 is communicated with the second input pin B0, and the port link bandwidth of the PCIE Switch chip 104 connected to the single-pole double-throw Switch chip 103 is configured to be the second bandwidth (e.g., PCIE X8).

Fig. 4 is a schematic diagram of the interconnection between the single-pole double-throw Switch chip 103 and the PCIE Switch chip 104 of the system shown in fig. 1. In a preferred embodiment, the PCIE Switch chip 104 may be a PEX8780 chip. As shown in fig. 4, the output pin of the single-pole double-throw Switch chip 103 is connected to the control pin of the PCIE Switch chip 104 (since the VCC voltages of the SN74LVC1G3157 and the PCIE Switch are different, the SN74LVC1G3157 plays a role in level isolation). The control pin (Strap pin) is a pin for controlling selection of output of another pin by the level of a certain pin. The PCIE Switch chip 104 may include a plurality of control pins, each control pin corresponding to a port.

In the following, different embodiments of configuring PCIE resources by using the PCIE resource configuration system of the present invention are illustrated, so that those skilled in the art will more deeply understand the technical solutions and the beneficial effects brought by the present invention.

Fig. 5 is a schematic block diagram of an embodiment of configuring PCIE resources using a PCIE resource configuration system of the present invention. As shown in fig. 5, the PCIE Switch chips may include a first-stage PCIE Switch chip (PCIE Switch 0) and four second-stage PCIE Switch chips (PCIE Switch a, PCIE Switch B, PCIE Switch C, PCIE Switch D), the first-stage PCIE Switch chip is connected to the CPU through PCIE X16, the second-stage PCIE Switch chip is connected to the first-stage PCIE Switch chip through PCIE X16, and each second-stage PCIE Switch chip is connected to a corresponding single-pole double-throw Switch chip. Each second-level PCIE Switch chip may include at least one control pin (not shown), each control pin corresponding to one port, and it is shown in fig. 5 that each second-level PCIE Switch chip includes four ports (e.g., state 0, state 1, state 3, state 4 of PCIE Switch a, state 0, state 1, state 3, state 4 of PCIE Switch B, state 1, state 2, state 3, state 4 of PCIE Switch C, state 0, state 1, state 3, state 4 of PCIE Switch D) that can configure bandwidth through the control pins.

In a preferred embodiment, configuring PCIE resources through the PCIE Switch chip includes: and adjusting the link bandwidth of the configurable port of the second-stage PCIE Switch chip. For example, in the embodiment of fig. 5, after the system is powered on, the south bridge chip configures the register of the I/O Expander chip through the I2C bus according to the user configuration information stored in the nonvolatile memory of the I/O Expander chip to output a high level, after the selection of the single-pole double-throw Switch chip, the lap pin of the second stage PCIE Switch is pulled high, and all of the four groups of downstream states of the second stage PCIE Switch are configured as PCIE X16, for example, for connecting PCIE devices (e.g., NVIDIA GPU configured line cards) plugged into PCIE X16 slots.

A user may change a PCIE configuration using the PCIE resource configuration system of the present invention, for example, fig. 6 shows another embodiment of PCIE resource configuration. The embodiment of fig. 6 is different from the embodiment shown in fig. 5 only in that the link bandwidths of the configurable ports of the second-stage PCIE Switch chip are different, and other features are the same, so that details are not described herein. As shown in fig. 6, when the PCIE configuration is changed, the south bridge chip configures the register of the I/O Expander chip through the I2C bus according to the user configuration information stored in the nonvolatile memory of the I/O Expander chip to output a low level, pulls down the lap pin of the second level PCIE Switch after being selected by the single-pole double-throw Switch chip, and configures four sets of downstream states of the second level PCIE Switch into two sets of PCIE X8, for example, PCIE devices (e.g., line cards configured by Xilinx FPGA) plugged in the PCIE X8 slot.

It should be appreciated that the present invention is not limited by the embodiments of fig. 5 and fig. 6, that is, a person skilled in the art may make appropriate modifications to the embodiments of fig. 5 and fig. 6 under the teaching of the present invention, for example, the number of configurable ports, the number of PCIE switches at each stage, etc. may be selected according to practical situations, and the PCIE resource configuration system using the present invention may Switch between PCIE X1, PCIE X2, PCIE X4, PCIE X8, PCIE X16 at will.

Based on the foregoing objective, a second aspect of the present invention provides an embodiment of a PCIE resource allocation method. The method comprises the following steps: and the PCIE resources are configured by utilizing the PCIE resource configuration system.

Based on the Purely platform, after the I/O Expander chip is read and written by the south bridge chip, the lap pin of the PCIE Switch is configured through the single-pole double-throw Switch chip so as to configure the port link bandwidth of the Switch chip. Compared with the prior art, the embodiment of the invention has the following beneficial effects: in the prior art, a Strap pin signal is connected to a 3-pin Jumper, and in practical application, a user needs to enter a field to open a chassis and manually adjust the Jumper position to realize the switching of a PCIE topological structure; or the PCA9555 chip controls the Strap pin, but the register is restored to the default state after power failure, the configuration information of the user cannot be stored, and manual configuration needs to be carried out again after power on again. However, the invention uses an I/O Expander chip with a nonvolatile memory inside, and the PCIE Switch port configuration is adjusted to Switch the system topology by changing the Strap pin voltage. The user only needs to change the register of the I/O Expander chip through the I2C interface of the south bridge chip, and reconfigures the Strap pin voltage of the PCIE Switch after the selection of the single-pole double-throw Switch chip, thereby realizing the adjustment of the downstream PCIE bandwidth. In addition, the invention can be applied to other principle designs which need to change the configuration by using a Jumper/PCA9555 device and the like. Therefore, the invention can facilitate the operation of users, reduce the design cost and is suitable for mass production products.

It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by a computer program that can be stored in a computer-readable storage medium and that, when executed, can include the processes of the above embodiments of the methods. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The computer program may achieve the same or similar effects as the corresponding previous method embodiments.

Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.

Further, the above-described method steps may also be implemented using a controller and a computer-readable storage medium for storing a computer program that causes the controller to implement the functions of the above-described steps.

Further, it should be understood that the computer-readable storage medium (e.g., memory) employed to implement the methods of the present invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The above is an exemplary embodiment of the present disclosure, and the order of disclosure of the above embodiment of the present disclosure is only for description and does not represent the merits of the embodiment. It should be noted that the discussion of any embodiment above is exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to those examples, and that various changes and modifications may be made without departing from the scope, as defined in the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. A PCIE resource allocation system, comprising: the system comprises a south bridge chip, an I/O expansion chip, a single-pole double-throw switch chip and a PCIE switching chip, wherein the south bridge chip is connected with the I/O expansion chip, the I/O expansion chip is connected with the single-pole double-throw switch chip, the single-pole double-throw switch chip is connected with the PCIE switching chip,

the I/O expansion chip is internally provided with a nonvolatile memory, user configuration information is stored in the nonvolatile memory, the south bridge chip configures the level of an I/O port connected with the I/O expansion chip and the single-pole double-throw switch chip according to the user configuration information, and controls the output of the single-pole double-throw switch chip to the PCIE switching chip so as to configure PCIE resources through the PCIE switching chip.

2. The PCIE resource configuration system of claim 1, wherein the configuring the PCIE resources through the PCIE switch chip comprises: and adjusting the port link bandwidth of the PCIE switching chip.

3. The PCIE resource configuration system of claim 1, wherein the I/O port of the I/O expansion chip is connected to a selection input pin of the single-pole double-throw switch chip, and an output pin of the single-pole double-throw switch chip is connected to a control pin of the PCIE switch chip.

4. The PCIE resource configuration system of claim 3, wherein the single-pole double-throw switch chip comprises a first input pin and a second input pin; when the level output by the I/O port of the I/O expansion chip is a high level, the output pin of the single-pole double-throw switch chip is communicated with the first input pin, and a port link bandwidth of the PCIE switch chip connected to the single-pole double-throw switch chip is configured as a first bandwidth; when the level output by the I/O port of the I/O expansion chip is a low level, the output pin of the single-pole double-throw switch chip is communicated with the second input pin, and the port link bandwidth of the PCIE switch chip connected to the single-pole double-throw switch chip is configured as a second bandwidth.

5. The PCIE resource allocation system of claim 1, wherein the south bridge chip is connected to the I/O expansion chip through an I2C bus.

6. The PCIE resource configuration system of claim 1, wherein the non-volatile memory comprises at least one of: ROM, PROM, EPROM, EEPROM, or Flash.

7. The PCIE resource configuration system of claim 1, wherein the PCIE switch chips comprise at least one first level PCIE switch chip and at least one second level PCIE switch chip, the first level PCIE switch chip is connected to a CPU, the second level PCIE switch chip is connected to the first level PCIE switch chip, and each second level PCIE switch chip is connected to a corresponding single-pole double-throw switch chip.

8. The PCIE resource configuration system of claim 7, wherein each of the second-level PCIE switch chips comprises at least one control pin, and each control pin corresponds to one port.

9. The PCIE resource configuration system of claim 8, wherein configuring PCIE resources through the PCIE switch chip comprises: and adjusting the link bandwidth of the port of the second-stage PCIE switching chip.

10. A PCIE resource configuration method is characterized in that the method comprises the following steps: the PCIE resource configuration system of any one of claims 1 to 9 is utilized to configure PCIE resources.