CN109327205B

CN109327205B - Boost clock generating circuit

Info

Publication number: CN109327205B
Application number: CN201810966055.6A
Authority: CN
Inventors: 王永寿; 吴建刚
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2018-08-23
Filing date: 2018-08-23
Publication date: 2022-08-05
Anticipated expiration: 2038-08-23
Also published as: CN109327205A

Abstract

The invention discloses a boost clock generating circuit which is characterized by being formed by interconnecting a charge-discharge unit, a level conversion unit and a digital modulation unit, wherein the level conversion unit and the digital modulation unit which are mainly formed by connecting common MOS (metal oxide semiconductor) tubes work in a high voltage domain VDDL-VDDH, a low-voltage clock signal is connected into the charge-discharge unit and is boosted by the level conversion unit and the digital modulation unit, and output ends PH1 and PH1B of the digital modulation unit are used as high-voltage clock signals obtained by conversion and are output. The boost clock generating circuit can realize the function of converting a low-voltage clock into a high-voltage clock, avoids the influence of a high-voltage MOS tube and a parasitic capacitor thereof on the switching efficiency, simultaneously eliminates the consumption of extra static current and optimizes the overall energy consumption of the circuit.

Description

Boost clock generating circuit

Technical Field

The invention relates to a signal conversion circuit, in particular to a clock signal generation circuit suitable for converting low voltage into high voltage of a common mode power supply of an application system.

Background

With the increasing development of electronic application technologies, the technology is developed as a hardware base, and the microelectronics also continuously breaks through and develops in the technical problem. In the microelectronic design of many application systems, although most of the circuit designs use low voltage timing signals, the conventional signal swing is below 5V. However, as the functions of the application system are diversified, the clock signal with a low voltage pulse cannot meet the signal requirement of part of high voltage driving, and therefore, a clock signal generating circuit for boosting the voltage is required to be introduced into the circuit design of such a functional system.

Some related circuit designs are actually proposed by some designers in the prior art, but high-voltage MOS transistors or LDMOS transistors are inevitably used to meet the requirements of high voltage resistance, power control and the like. Through deep analysis and research, the clock generation circuit with the design mode also has a plurality of defects and shortcomings: firstly, due to the existence of parasitic capacitance of a high-voltage MOS tube, the conversion efficiency is greatly limited in the charging and discharging process, and the whole process has strong sensitivity and great difficulty; further, the circuit is complicated, so that the actual power consumption is always kept at a high level, and it is difficult to reduce the power consumption.

Disclosure of Invention

In view of the above-mentioned deficiencies of the prior art in boosting a clock signal, the present invention provides a boosted clock generating circuit to meet the adaptation requirement of the clock signal.

The technical solution of the present invention for achieving the above object is a boost clock generation circuit, characterized in that: the circuit is formed by interconnection of a charge and discharge unit, a level conversion unit and a digital modulation unit, wherein the level conversion unit and the digital modulation unit work in a high voltage domain VDDL-VDDH, a low-voltage clock signal is connected into the charge and discharge unit, and output ends PH1 and PH1B of the digital modulation unit are used as high-voltage clock signals obtained through conversion and output.

Further, the level shift unit is composed of PMOS tubes PM0, PM1, PM2, PM3, NMOS tubes NM1, NM2 and a bias current I _bias The common source of PM2, PM1, PM0 and the common drain of NM1, NM2 are connected to VDDH, the drain of PM2, the source of PM3 are connected to the common gate of PM2, PM1, PM0, bias current I _bias The drain of PM3 is connected with the common gate of PM3, NM1 and NM2, and the bias current I _bias The negative end of NM1 is grounded, the source of NM1 and the drain of PM1 are connected to node A, the node A is respectively connected to one path of each of the charge and discharge unit and the digital modulation unit, the source of NM2 and the drain of PM0 are connected to node B, and the node B is respectively connected to the other path of each of the charge and discharge unit and the digital modulation unit.

Furthermore, the charge and discharge unit is composed of two capacitors C1 and C2, wherein one end of the capacitor C1 is connected to the CK1 end of the charge and discharge unit receiving the low-voltage clock signal, the other end of the capacitor C1 is connected to the node a, one end of the capacitor C2 is connected to the CK2 end of the charge and discharge unit receiving the low-voltage clock signal, and the other end of the capacitor C2 is connected to the node B.

Furthermore, the digital modulation unit is formed by connecting a first and gate, a second and gate and four not gates, wherein a first input end of the first and gate is connected to a node B, a second input end of the first and gate is connected to an output end of the second and gate, an output end of the first and gate is connected in series with the two not gates to form an output end PH1, a first input end of the second and gate is connected to a node a, a second input end of the second and gate is connected to an output end of the first and gate, and an output end of the second and gate is connected in series with the two not gates to form an output end PH 1B.

Furthermore, the low-voltage clock signal has a swing of 0-aV, a ranges from 1 to 5, the high-voltage clock signal has a swing of b-cV, and c-b = a, b ranges from 60 to 110.

The boost clock generating circuit has the prominent substantive characteristics and the remarkable progress: the newly-constructed circuit can realize the function of converting a low-voltage clock into a high-voltage clock, avoids the influence of using a high-voltage MOS tube and a parasitic capacitor thereof on the switching efficiency, simultaneously eliminates the consumption of extra quiescent current, and optimizes the overall energy consumption of the circuit.

Drawings

FIG. 1 is a schematic diagram of a boost clock generation circuit according to the present invention.

Detailed Description

The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.

The designer of the invention aims at the defects of the prior art in the aspect of clock signal boosting, integrates the experience of the industry for many years, and aims to provide a breakthrough of technical improvement on the boosting clock generating circuit so as to meet the adaptation requirement of the clock signal.

The boost clock generation circuit is mainly formed by interconnection of a charge-discharge unit, a level conversion unit and a digital modulation unit, wherein the level conversion unit is formed by connecting a common MOS (metal oxide semiconductor) tube and a bias current, the digital modulation unit is formed by a plurality of gate circuit devices, the two units work in a high voltage domain VDDL-VDDH, a low voltage clock signal is connected into the charge-discharge unit, and output ends PH1 and PH1B of the digital modulation unit are used as high voltage clock signals obtained by conversion and output.

For a more detailed understanding, the schematic diagram of the boost clock generation circuit of the present invention as shown in FIG. 1 can be seen. Among the three-part component units, the first flat conversion unit is composed of PMOS tubes PM0, PM1, PM2, PM3, NMOS tubes NM1, NM2 and bias current I _bias The formed edge-triggered level conversion circuit. From the connection relationship of the devices: wherein PM2, PM1,The common source of PM0 and the common drain of NM1 and NM2 are connected to VDDH, the drain of PM2 and the source of PM3 are connected with the common gates of PM2, PM1 and PM0, and the bias current I is _bias The drain of PM3 is connected with the common gate of PM3, NM1 and NM2, and the bias current I _bias The negative end of NM1 is grounded, the source of NM1 and the drain of PM1 are connected to node A, the node A is respectively connected to one path of each of the charge and discharge unit and the digital modulation unit, the source of NM2 and the drain of PM0 are connected to node B, and the node B is respectively connected to the other path of each of the charge and discharge unit and the digital modulation unit. In the unit, the circuit does not need any high-voltage MOS tube or LDMOS tube, thereby avoiding the charge and discharge effect of parasitic capacitance of the high-voltage MOS tube, greatly improving the conversion efficiency, reducing the process sensitivity and facilitating the transplantation to various application designs. Moreover, the unit belongs to edge triggered level conversion, can realize the requirement of low power consumption,

on the other hand, the charge/discharge unit is composed of only two capacitors C1 and C2 to realize charge/discharge functions, wherein one end of the capacitor C1 is connected to the terminal CK1 of the charge/discharge unit receiving the low-voltage clock signal, the other end of the capacitor C1 is connected to the node a, one end of the capacitor C2 is connected to the terminal CK2 of the charge/discharge unit receiving the low-voltage clock signal, and the other end of the capacitor C2 is connected to the node B. The footprint of the overall generating circuit will thereby be effectively limited.

In another aspect, the digital modulation unit is formed by connecting a first and gate 1, a second and gate 2, and four not gates, wherein a first input terminal of the first and gate 1 is connected to a node B, a second input terminal of the first and gate is connected to an output terminal of the second and gate 2, an output terminal of the first and gate 1 is connected in series with two not gates to form an output terminal PH1, a first input terminal of the second and gate 2 is connected to a node a, a second input terminal of the second and gate 2 is connected to an output terminal of the first and gate 1, and an output terminal of the second and gate 2 is connected in series with two not gates to form an output terminal PH 1B. Thus, the high-voltage clock signal after being converted and boosted can be output through the output terminals PH1 and PH1B of the digital modulation unit.

The operation principle of the boosting circuit is understood from the conversion process of the boosting clock generation circuit: assuming that the high level of the low-voltage clock is V1, the low level is 0, CK1 and CK2 are differential clock signals, and the initial clock signal is CK1 is 0, CK2 is V1; in a stable state, because the capacitor branch has no current, the voltage of points A and B is VDDH, the static power consumption is zero at the moment, and the voltages of two polar plates of the capacitor C1 are VDDH and 0 respectively; the voltages of two polar plates of the capacitor C2 are VDDH and V1 respectively; when the low voltage clock state changes, i.e. CK1 changes from 0 to V1, CK2 changes from V1 to 0.

Since the voltage of the capacitor cannot be suddenly changed, according to the principle of conservation of charge, for the capacitor C1, at the moment of jump, the voltage of one plate, namely the point a, jumps to VDDH + V1, the voltage of the other plate is V1, and after the jump is finished, the point a discharges the power supply VDDH through the body diode of the NOMS tube NM1 until the voltage of the point a is stabilized to VDDH.

Similarly, for the capacitor C2, according to the principle of conservation of charge, at the moment of jump, the voltage of one plate, namely the point B jumps to VDDH-V1, and the voltage of the other plate is 0; after the transition is over, the voltage at point B drops, and the NMOS transistor NM2 turns on the strong pull-up point B to VDDH.

According to the above process, it can be seen that, during the transition of the low-voltage clock from the high level V1 to the low level 0, or a glitch signal is generated from VDDH down to VDDH-V1, as long as the value of VDDH-V1 is smaller than the trigger threshold of the RS flip-flop, the signal is responded by the RS flip-flop in the high-voltage domain, so as to generate the clock signal in the high-voltage domain; therefore, clock signals of the low-voltage clocks 0-V1 are raised to any high-voltage domain supported by the VDDL-VDDH process.

Generally, the low voltage clock signal has a swing of 0-aV, a ranges from 1 to 5, the high voltage clock signal has a swing of b-cV, and b ranges from 60 to 110. For example, in the microelectronic design of conventional application systems, most of the low voltage timing signals are usually 0-5V pulses, and the high voltage timing signals converted by the boost timing generation circuit of the present invention can reach a moderate swing pulse at a common mode voltage of 80V.

The boost clock generating circuit has the prominent substantive characteristics and remarkable progress: the newly-constructed circuit can realize the function of converting a low-voltage clock into a high-voltage clock, avoids the influence of using a high-voltage MOS tube and a parasitic capacitor thereof on the switching efficiency, simultaneously eliminates the consumption of extra quiescent current, and optimizes the overall energy consumption of the circuit.

Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and modifications and equivalents within the scope of the claims may be made by those skilled in the art and are included in the scope of the present invention.

Claims

1. A boost clock generation circuit, characterized by: the circuit is formed by interconnecting a charging and discharging unit, a level conversion unit and a digital modulation unit, wherein the level conversion unit and the digital modulation unit work in a high voltage domain VDDL-VDDH, the level conversion unit is an edge triggered level conversion circuit formed by PMOS tubes PM0, PM1, PM2, PM3, NMOS tubes NM1, NM2 and bias current Ibias, wherein common sources of PM2, PM1 and PM0 and common drains of NM1 and NM2 are connected to VDDH, drains of PM2 and PM3 are connected with common gates of PM2, PM1 and PM0, positive ends of bias currents Ibias and PM3 and drains of PM3, NM1 and NM2 are connected with common gates, negative ends of bias currents Ibias are grounded, sources of NM1 and drains of PM1 are connected with a node A, the node A is respectively connected with one path of each of the charge and discharge unit and the digital modulation unit, the source of the NM2 and the drain of the PM0 are connected with the node B, and the node B is respectively connected with the other path of each of the charge and discharge unit and the digital modulation unit; the charge and discharge unit is composed of two capacitors C1 and C2, wherein one end of the capacitor C1 is connected with the CK1 end of the charge and discharge unit for receiving the low-voltage clock signal, the other end of the capacitor C1 is connected to the node A, one end of the capacitor C2 is connected with the CK2 end of the charge and discharge unit for receiving the low-voltage clock signal, and the other end of the capacitor C2 is connected to the node B; the digital modulation unit is formed by connecting a first AND gate, a second AND gate and four NOT gates, wherein the first input end of the first AND gate is connected with a node B, the second input end of the first AND gate is connected with the output end of the second AND gate, the output end of the first AND gate is connected with two NOT gates in series to form an output end PH1, the first input end of the second AND gate is connected with a node A, the second input end of the second AND gate is connected with the output end of the first AND gate, and the output end of the second AND gate is connected with two NOT gates in series to form an output end PH 1B; the low-voltage clock signal is connected to a charge and discharge unit, the charge and discharge unit is combined with the level conversion unit to generate a trigger signal containing a burr signal according to the low-voltage clock signal and the high voltage domain high voltage VDDH and provide the trigger signal to the digital modulation unit so as to trigger an RS trigger in the digital modulation unit to generate a high-voltage clock signal based on the high voltage domain VDDL-VDDH.

2. The boost clock generation circuit of claim 1, wherein: the low-voltage clock signal has a swing of 0-aV, the value of a ranges from 1 to 5, the high-voltage clock signal has a swing of b-cV, and the value of c-b = a, b ranges from 60 to 110.