CN109324991B

CN109324991B - Hot plug device, method, medium and system of PCIE (peripheral component interface express) equipment

Info

Publication number: CN109324991B
Application number: CN201811109611.4A
Authority: CN
Inventors: 赵帅; 孙昊; 亓浩
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-09-21
Filing date: 2018-09-21
Publication date: 2021-12-03
Anticipated expiration: 2038-09-21
Also published as: CN109324991A

Abstract

The invention discloses a hot plug device, a method, a medium and a system of PCIE equipment, wherein the method comprises the following steps: in the BIOS starting process, acquiring and occupying target memory resources distributed by a host by using the identity of PCIE equipment; after the BIOS is started, when the PCIE interface is detected to be accessed into a new PCIE device, establishing a communication relation between a host and the new PCIE device, and providing target memory resources for the new PCIE device; when the PCIE interface is detected to be disconnected with the existing PCIE equipment, the IO access initiated by the host to the existing PCIE equipment is received by utilizing the target memory resource. The method ensures the overall working stability of the system formed by the PCIE equipment and the host. In addition, the invention also provides a hot plug device for realizing the PCIE equipment, a computer readable storage medium and a hot plug system for the PCIE equipment, and the beneficial effects are the same as the above.

Description

Hot plug device, method, medium and system of PCIE (peripheral component interface express) equipment

Technical Field

The present invention relates to the field of data communications, and in particular, to a hot-plug apparatus, method, medium, and system for PCIE devices.

Background

In the technical background of big data and cloud computing, the importance of read-write performance to data processing is increasingly prominent. Taking a solid state disk as an example, with the rapid development of an SSD (solid state disk) technology, the performance of the SSD is increasing dramatically, the bandwidth of a flash memory in a bottom layer of the SSD is increasing, and the delay when accessing a flash memory medium is decreasing, for the greatly increased data read-write performance of the SSD, an AHCI bus protocol or an SATA bus protocol commonly used at an interface of the SSD cannot meet the requirements of the current SSD on high performance and low delay, because a channel of a PCIE bus protocol has characteristics of low delay and parallel communication, the current SSD is usually connected to a host by using an interface based on a PCIE bus protocol, that is, the SSD is connected to the host as a PCIE device, so as to increase the read-write performance of the host on data in the SSD.

When a host connected with a PCIE device performs BIOS startup, memory resources corresponding to each logic unit of the PCIE device are first allocated in the host, and then the host can perform IO (input/output) operation on the PCIE device based on the pre-allocated memory resources. However, since the memory resources of the host may be completely allocated to the current PCIE device in the BIOS startup process, when the BIOS is started up and the host is in a working state, a new PCIE device is inserted, and the host may not allocate new memory resources to the PCIE device any more, so that the new PCIE device cannot be normally used at the host, and further generate abnormal information at the host; in addition, when the PCIE device and the host are in an IO process, disconnecting the PCIE device from the host may release a memory resource allocated to the PCIE device in the host, and since the host cannot access the memory resource, the host cannot continue to send the IO access to the memory resource, and finally, the host generates abnormal information. In the above, when the host is in a working state, it is difficult to ensure the overall stability of a system formed by the PCIE device and the host for the hot plug operation of the PCIE device.

Therefore, it is obvious that providing a hot-plug apparatus and method for PCIE devices to relatively ensure the overall stability of a system formed by the PCIE devices and a host is a problem to be solved urgently by those skilled in the art.

Disclosure of Invention

The invention aims to provide a hot-plug device, a method, a medium and a system of PCIE equipment, so as to relatively ensure the overall stability of a system formed by the PCIE equipment and a host.

In order to solve the above technical problem, the present invention provides a hot plug device for PCIE devices, including:

the FPGA device is connected with the host and is used for occupying target memory resources allocated by the host by the identity of the PCIE device and providing the target memory resources for the PCIE device or the host when the PCIE device is inserted or pulled out;

and the Peripheral Component Interface Express (PCIE) interface is connected with the FPGA equipment and used for inserting or pulling out the PCIE interface of the PCIE equipment.

In addition, the present invention further provides a hot plug method for a PCIE device, which is applied to the hot plug apparatus for a PCIE device disclosed above, and includes:

in the BIOS starting process, the FPGA equipment acquires and occupies target memory resources distributed by the host machine according to the identity of the PCIE equipment;

after the BIOS is started, when the PCIE interface is detected to be accessed into a new PCIE device, establishing a communication relation between a host and the new PCIE device, and providing target memory resources for the new PCIE device;

when the PCIE interface is detected to be disconnected with the existing PCIE equipment, the IO access initiated by the host to the existing PCIE equipment is received by utilizing the target memory resource.

Preferably, after the BIOS is started, when it is detected that the PCIE interface accesses the new PCIE device, establishing a communication relationship between the host and the new PCIE device, and providing the target memory resource to the new PCIE device specifically includes:

after the BIOS is started, when an in-place signal of the new PCIE equipment is detected, establishing a communication relation between the host and the new PCIE equipment;

initiating an interrupt processing application for rescanning the PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the new PCIE equipment so as to identify and use the new PCIE equipment through the host.

Preferably, when it is detected that the PCIE interface is disconnected from the existing PCIE device, receiving, by using the target memory resource, an IO access initiated by the host to the existing PCIE device specifically includes:

when detecting that an in-place signal of the existing PCIE equipment is disconnected, initiating an interrupt processing application for changing the memory resource corresponding to the existing PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the existing PCIE equipment;

and receiving IO access initiated by the host to the existing PCIE equipment by utilizing the target memory resource.

Preferably, the PCIE device is specifically a PCIE SSD.

Preferably, the PCIE SSD is specifically an NVME SSD.

Preferably, the target memory resource specifically includes a BUS resource, a DEVICE resource, a FUNCTION ID resource, and an MMIO space resource.

Preferably, the PCIE interface is specifically an U.2 standard interface.

In addition, the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when executed by a processor, the computer program implements the steps of the hot plug method for a PCIE device as described above.

In addition, the invention also provides a hot plug system of the PCIE equipment, which comprises a hot plug device of the PCIE equipment.

The hot plug device of the PCIE equipment comprises an FPGA equipment which is connected with a host and used for occupying target memory resources distributed by the host by the identity of the PCIE equipment and providing the target memory resources for the PCIE equipment or the host when the PCIE equipment is inserted or pulled out, and a PCIE interface which is connected with the FPGA equipment and used for inserting or pulling out the PCIE equipment. On the basis of the topological structure of the hot plug device of the PCIE equipment, the hot plug method of the PCIE equipment provided by the invention is characterized in that in the starting process of a BIOS (basic input/output system) of a host, an FPGA (field programmable gate array) device is used as the PCIE equipment to acquire and occupy target memory resources distributed by the host, and then when a PCIE interface of the FPGA equipment is connected into new PCIE equipment, the target memory resources occupied in advance are provided for the new PCIE equipment to be used; when a PCIE interface of the FPGA device is disconnected with the existing PCIE device, namely the original memory resource of the existing PCIE device is released, IO access initiated by a host to the existing PCIE device is received through the target memory resource. According to the method, the target memory resources allocated by the host are acquired and occupied in advance by the FPGA equipment in the identity of the PCIE equipment, so that when a hot plug condition occurs in the working process of the host, the target memory resources occupied by the FPGA equipment can be used as standby resources to support the normal operation of various operations of the host after the hot plug, the normal operation of the host is further ensured, and the overall working stability of a system formed by the PCIE equipment and the host is ensured. In addition, the invention provides a computer readable storage medium for realizing hot plug of the PCIE equipment and a hot plug system of the PCIE equipment, and the beneficial effects are the same as the above.

Drawings

In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive effort.

Fig. 1 is a structural diagram of a hot plug device of a PCIE device according to an embodiment of the present invention;

fig. 2 is a flowchart of a hot plug method of a PCIE device according to an embodiment of the present invention;

fig. 3 is a flowchart of another hot plug method for a PCIE device according to an embodiment of the present invention;

fig. 4 is a flowchart of another hot plug method for a PCIE device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

The core of the invention is to provide a hot-plugging device and a hot-plugging method for PCIE equipment, so as to relatively ensure the overall stability of a system formed by the PCIE equipment and a host. In addition, another core of the present invention is to provide a computer readable storage medium for implementing hot plug of a PCIE device and a hot plug system of a PCIE device.

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Example one

Fig. 1 is a structural diagram of a hot plug device of a PCIE device according to an embodiment of the present invention. The hot plug device 10 of PCIE device provided in the embodiment of the present invention includes:

the FPGA device 12 is connected with the host 11 and used for occupying target memory resources allocated by the host with the identity of the PCIE device and providing the target memory resources for the PCIE device or the host 11 when the PCIE device is inserted or pulled out;

and the PCIE interface 13 is connected to the FPGA device 12 and used for inserting or pulling out the PCIE device.

The host in the present apparatus refers to a main body part of a computer excluding IO (input/output) devices, and generally includes a CPU, a memory, a hard disk, an optical drive, a power supply, and other input/output controllers and interfaces. Because the FPGA device occupies the target memory resource allocated by the host with the identity of the PCIE device, the host and the FPGA device are connected by the PCIE standard. The host in the device mainly scans the accessed PCIE equipment through the processing logic of the CPU, and then allocates corresponding memory resources to each PCIE equipment obtained through scanning, wherein the memory resources are a general name of a series of logic spaces required by the PCIE equipment and the host when in normal IO interaction, and the logic spaces specifically contained in the memory resources are not specifically limited due to certain differences among different PCIE equipment.

In addition, the FPGA device is provided with the PCIE interfaces for connecting the PCIE devices, and the FPGA device has good expandability, so that the number of the PCIE interfaces is not limited to 1, and can be set according to actual conditions.

The FPGA equipment in the device is a connection relation established between the identity of the PCIE equipment and the host, and the FPGA equipment has higher programming flexibility and controls the working state of the FPGA equipment by a program stored in the RAM, so that a user can compile a corresponding program according to the logic function of the FPGA equipment, the FPGA equipment can simulate the working logic of the PCIE equipment and can be used as the PCIE equipment to communicate with the host.

In addition, a specific implementation manner in which the FPGA device simulates the working logic of the PCIE device and communicates with the host using the identity of the PCIE device is to create a logic module in the FPGA device, which is the same as the PCIE device, and write fixed content in a configuration space (i.e., a standard register) of each logic module.

The hot plug device of the PCIE equipment comprises an FPGA equipment which is connected with a host and used for occupying target memory resources distributed by the host by the identity of the PCIE equipment and providing the target memory resources for the PCIE equipment or the host when the PCIE equipment is inserted or pulled out, and a PCIE interface which is connected with the FPGA equipment and used for inserting or pulling out the PCIE equipment.

Fig. 2 is a flowchart of a hot plug method of a PCIE device according to an embodiment of the present invention, and is applied to the hot plug apparatus of the PCIE device. Referring to fig. 2, the hot-plug method of the PCIE device includes the specific steps of:

step S10: and in the BIOS starting process, acquiring and occupying target memory resources distributed by the host by using the identity of the PCIE equipment.

It should be noted that BIOS (Basic Input Output System) is a set of programs that are solidified on a ROM chip on a main board in a computer, and stores the most important Basic Input and Output programs of the computer, a self-test program after power-on, and a System self-start program, and its main function is to provide the bottom layer and most direct hardware setting and control for the computer. In order to ensure that PCIE devices connected to the host can be used normally after the initialization of the host is completed, in the BIOS starting process, memory resources corresponding to each PCIE device need to be allocated in the host. In this step, the purpose of simulating the FPGA device as the PCIE device is only to acquire and occupy the target memory resource allocated by the host, and besides, the FPGA device does not perform IO operation with the host using the identity of the PCIE device, so the target memory resource is substantially an idle memory resource.

Step S11: after the BIOS is started, when the PCIE interface is detected to be accessed into the new PCIE equipment, the communication relation between the host and the new PCIE equipment is established, and target memory resources are provided for the new PCIE equipment.

It should be noted that the main execution body of this step should be an FPGA device, and the FPGA device executes the operation content of this step and the subsequent steps through a program written in advance and stored in the RAM. After the BIOS is started, namely after the initialization process of the host is finished and normal work is started, when the PCIE interface is detected to be connected with the new PCIE equipment, the communication relation between the new PCIE equipment and the host in logic is established, so that the basis of IO interaction between the host and the new PCIE equipment is established, and then target memory resources pre-occupied by the FPGA equipment are used as memory resources used when IO is performed between the new PCIE equipment and the host, so that the situation that an error is reported because the host does not have the memory resources to perform IO interaction with the new PCIE equipment is prevented.

Step S12: when the PCIE interface is detected to be disconnected with the existing PCIE equipment, the IO access initiated by the host to the existing PCIE equipment is received by utilizing the target memory resource.

In this step, when the PCIE interface is detected to be disconnected from the existing PCIE device, that is, the operation content performed when the existing PCIE device is pulled out from the PCIE interface is detected, because the memory resource of the existing PCIE device in the host is released when the existing PCIE device is pulled out from the PCIE interface, in order to avoid a situation that the host initiates an IO access to the existing PCIE device but cannot find the memory resource of the existing PCIE device after the memory resource is released, the target memory resource is used in this step to receive the IO access initiated by the host to the existing PCIE device, so as to prevent an error report of the host from occurring.

On the basis of the topological structure of the hot plug device of the PCIE equipment, the hot plug method of the PCIE equipment provided by the invention is characterized in that in the starting process of a BIOS (basic input/output system) of a host, an FPGA (field programmable gate array) device is used as the PCIE equipment to acquire and occupy target memory resources distributed by the host, and then when a PCIE interface of the FPGA equipment is connected into new PCIE equipment, the target memory resources occupied in advance are provided for the new PCIE equipment to be used; when a PCIE interface of the FPGA device is disconnected with the existing PCIE device, namely the original memory resource of the existing PCIE device is released, IO access initiated by a host to the existing PCIE device is received through the target memory resource. According to the method, the target memory resources allocated by the host are acquired and occupied in advance by the FPGA equipment in the identity of the PCIE equipment, so that when a hot plug condition occurs in the working process of the host, the target memory resources occupied by the FPGA equipment can be used as standby resources to support the normal operation of various operations of the host after the hot plug, the normal operation of the host is further ensured, and the overall working stability of a system formed by the PCIE equipment and the host is ensured.

Example two

On the basis of the above examples, the present invention also provides a series of preferred embodiments as follows.

Fig. 3 is a flowchart of another hot plug method for a PCIE device according to an embodiment of the present invention. Step S10 and step S12 in fig. 3 are the same as those in fig. 2, and are not repeated here.

As shown in fig. 3, as a preferred embodiment, after the BIOS is started, when it is detected that a PCIE interface accesses a new PCIE device, establishing a communication relationship between a host and the new PCIE device, and providing a target memory resource to the new PCIE device specifically includes:

step S20: after the BIOS is started, when an in-place signal of the new PCIE equipment is detected, the communication relation between the host and the new PCIE equipment is established.

It can be understood that, when the new PCIE device is connected to the PCIE interface, a circuit at the PCIE interface is turned on, so that a level signal, that is, an in-place signal in this step is generated, and then when the in-place signal is detected, a communication relationship between the host and the new PCIE device is established. Since the PCIE device capable of working normally inevitably generates a level signal when accessing the PCIE interface, whether a new PCIE device is accessed is determined by detecting whether an in-place signal exists in this step, which has higher accuracy.

Step S21: initiating an interrupt processing application for rescanning the PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the new PCIE equipment so as to identify and use the new PCIE equipment through the host.

It should be noted that, after initiating an interrupt processing application to the host in this step, the host can be informed that the current PCIE device changes in the first time, so as to temporarily interrupt IO access of the host to the PCIE device, and rescan the PCIE device to find a new PCIE device, and further establish a corresponding relationship, that is, a "dependency relationship", between the new PCIE device and a target memory resource, and when the host initiates IO access to the new PCIE device, the target memory resource receives and processes the IO access. In the step, the currently-performed service of the host is temporarily interrupted by initiating the interrupt processing application to the host, so that the host can be ensured to finish loading the new PCIE equipment in the first time, and the loading efficiency of the new PCIE equipment when the new PCIE equipment is inserted into the host in a hot state is improved.

Fig. 4 is a flowchart of another hot plug method for a PCIE device according to an embodiment of the present invention. Steps S10-S11 in FIG. 4 are the same as those in FIG. 2, and are not repeated herein.

As shown in fig. 4, as a preferred embodiment, when it is detected that a PCIE interface is disconnected from an existing PCIE device, receiving, by using a target memory resource, an IO access initiated by a host to the existing PCIE device specifically includes:

step S30: when detecting that the in-place signal of the existing PCIE equipment is disconnected, initiating an interrupt processing application for changing the memory resource corresponding to the existing PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the existing PCIE equipment.

Step S31: and receiving IO access initiated by the host to the existing PCIE equipment by utilizing the target memory resource.

It can be understood that, when the existing PCIE device is pulled out from the PCIE interface, a path between the existing PCIE device and the PCIE interface is blocked, which may cause the level signal to disappear, that is, the on-site signal is disconnected. When an existing PCIE device is disconnected from a PCIE interface in a state where a host works, a situation that the host initiates an IO access to the existing PCIE device may still occur, but under the current situation, a memory resource belonging to the existing PCIE device is already released, and the IO access initiated by the host cannot be normally received and responded. In order to avoid the situation that the host is unstable due to the situation, in this step, when it is detected that the in-place signal of the existing PCIE device is disconnected, an interrupt processing application is initiated to the host, so as to set the memory resource corresponding to the existing PCIE device as a target memory resource, thereby achieving the purpose of establishing a subordinate relationship between the target memory resource and the existing PCIE device. In the step, the currently-performed service of the host is temporarily interrupted by initiating an interrupt processing application to the host, so that the host can be ensured to set the memory resource corresponding to the existing PCIE equipment as the target memory resource in the first time, and the stability of the host is ensured to the greatest extent.

In addition, as a preferred embodiment, the PCIE device is specifically a PCIE SSD.

It should be noted that the hard disk is an important device for providing data storage support and data reading support when the current big data and cloud computing processing is performed, and the read-write performance of the hard disk determines the overall efficiency of the big data and cloud computing processing. Due to the rapid development of the SSD (solid state disk) technology, the performance of the SSD is increasing dramatically, the bandwidth of the flash memory in the SSD bottom layer is higher and higher, and the delay when accessing the flash memory medium is lower and lower, so that the SSD has higher data read-write performance. According to the embodiment, the PCIE equipment is limited to the PCIE SSD so as to realize the hot plug operation of the PCIE SSD, a user can flexibly replace the PCIE SSD according to actual requirements, the expandability and the flexibility of system data storage can be further increased on the basis of high data read-write performance, and the flexibility of data read-write during big data and cloud computing processing is improved.

In addition, on the basis of the above embodiments, as a preferred embodiment, the PCIE SSD is specifically an NVME SSD.

The NVME SSD is a high-performance solid state disk in the PCIE SSD type, and has lower latency, lower power consumption, and higher data read/write efficiency, so that the read/write performance of data can be further improved on the basis of the above embodiment.

In addition, as a preferred embodiment, the target memory resource specifically includes a BUS resource, a DEVICE resource, a FUNCTION ID resource, and an MMIO space resource.

It should be noted that, the BUS resource is a public communication trunk line for transmitting information between various functional components of the computer, and it is a transmission line bundle composed of wires, according to the information type transmitted by the computer, the BUS of the computer can be divided into a data BUS, an address BUS and a control BUS, which are used to transmit data, data address and control signal respectively; DEVICE resources refer to space resources required when a PCIE DEVICE is loaded; the FUNCTION ID resource is a space resource required for loading each FUNCTION of the PCIE device; MMIO (Memory mapping I/O) space resources, i.e. Memory mapped I/O, I/O devices are placed in the Memory space, thus requiring certain space resources. The resource content specifically included in the target resource relates to the resource content that is generally required to be used by the PCIE device when operating, so that the operating reliability of the PCIE device can be relatively ensured.

In addition, as a preferred embodiment, the PCIE interface is specifically an U.2 standard interface.

It should be noted that the interface specification is derived from the solid state disk Form Work organization (SSD Form Factor Work Group). U.2 can support PCIE specifications, is compatible with SAS, SATA and other specifications, has higher compatibility for the accessed devices, has faster data read-write speed at the U.2 interface, and can relatively ensure the overall efficiency of data interaction between the PCIE interface of the FPGA device and the PCIE device.

EXAMPLE III

The invention further provides a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program implements the steps of the hot plug method for PCIE devices as described above.

The computer-readable storage medium provided by the invention is characterized in that in the starting process of a host BIOS, an FPGA device is used as a PCIE device to acquire and occupy target memory resources distributed by the host, and further when a PCIE interface of the FPGA device is accessed to a new PCIE device, the target memory resources occupied in advance are provided for the new PCIE device to use; when a PCIE interface of the FPGA device is disconnected with the existing PCIE device, namely the original memory resource of the existing PCIE device is released, IO access initiated by a host to the existing PCIE device is received through the target memory resource. The computer readable storage medium acquires and occupies the target memory resource allocated by the host in advance through the FPGA device by using the identity of the PCIE device, so that when a hot plug condition occurs in the working process of the host, the target memory resource occupied by the FPGA device can be used as a standby resource to support the normal operation of various operations of the host after the hot plug, the normal operation of the host is further ensured, and the overall working stability of a system formed by the PCIE device and the host is ensured.

In addition, the invention also provides a hot plug system of the PCIE equipment, which comprises the hot plug device of the PCIE equipment.

The hot plug system of the PCIE equipment provided by the invention takes the FPGA equipment as the PCIE equipment in the starting process of the BIOS of the host, acquires and occupies the target memory resource distributed by the host, and then provides the pre-occupied target memory resource for the new PCIE equipment to use when the PCIE interface of the FPGA equipment is accessed into the new PCIE equipment; when a PCIE interface of the FPGA device is disconnected with the existing PCIE device, namely the original memory resource of the existing PCIE device is released, IO access initiated by a host to the existing PCIE device is received through the target memory resource. Because the system acquires and occupies the target memory resource allocated by the host in advance through the FPGA device by using the PCIE device, when a hot plug condition occurs in the working process of the host, the target memory resource occupied by the FPGA device can be used as a standby resource to support the normal operation of each item of work of the host after the hot plug, so that the normal operation of the host is ensured, and the integral working stability of the system formed by the PCIE device and the host is ensured.

The hot plug device, the method, the medium and the system for the PCIE device provided in the present invention are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the media and the system disclosed by the embodiment, the description is simple because the media and the system correspond to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A hot plug device of PCIE equipment is characterized by comprising:

the FPGA equipment is connected with the host and used for occupying target memory resources allocated by the host by the identity of the PCIE equipment and providing the target memory resources for the PCIE equipment or the host when the PCIE equipment is inserted; when the PCIE equipment is pulled out, initiating an interrupt processing application for changing the memory resource corresponding to the existing PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the existing PCIE equipment; receiving IO access initiated by the host to the existing PCIE equipment by utilizing the target memory resource;

and the PCIE interface is connected with the FPGA equipment and used for inserting or pulling out the PCIE interface of the PCIE equipment.

2. A hot plug method for a PCIE device, which is applied to the hot plug apparatus of a PCIE device of claim 1, and the method includes:

in the BIOS starting process, acquiring and occupying target memory resources allocated by the host by using the identity of the PCIE equipment;

after the BIOS is started, when the PCIE interface is detected to be accessed into a new PCIE device, establishing a communication relation between the host and the new PCIE device, and providing the target memory resource for the new PCIE device;

when the PCIE interface is detected to be disconnected with the existing PCIE equipment, receiving IO access initiated by the host to the existing PCIE equipment by using the target memory resource;

when it is detected that the PCIE interface is disconnected from the existing PCIE device, receiving, by using the target memory resource, an IO access initiated by the host to the existing PCIE device specifically includes:

when detecting that the in-place signal of the existing PCIE equipment is disconnected, initiating an interrupt processing application for changing the memory resource corresponding to the existing PCIE equipment to the host, and establishing the subordinate relation between the target memory resource and the existing PCIE equipment;

3. The method of claim 2, wherein, after the BIOS is started, when it is detected that the PCIE interface accesses a new PCIE device, establishing a communication relationship between the host and the new PCIE device, and providing the target memory resource to the new PCIE device specifically includes:

initiating an interrupt processing application for rescanning the PCIE equipment to the host, and establishing the subordinate relationship between the target memory resource and the new PCIE equipment so as to identify and use the new PCIE equipment through the host.

4. The method of claim 2, wherein the PCIE device is specifically a PCIE SSD.

5. The method of claim 4, wherein the PCIE SSD is specifically an NVME SSD.

6. The method of claim 2, wherein the target memory resources specifically comprise BUS resources, DEVICE resources, FUNCTION ID resources, and MMIO space resources.

7. The method according to any of claims 2 to 6, wherein the PCIE interface is specifically an U.2 standard interface.

8. A computer-readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the hot plug method for a PCIE device as recited in any one of claims 2 to 7.

9. A hot plug system of a PCIE device, comprising the hot plug apparatus of a PCIE device according to claim 1.