CN109308282A - A kind of parallel architecture method and device being used in MR mixed reality equipment - Google Patents
A kind of parallel architecture method and device being used in MR mixed reality equipment Download PDFInfo
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- CN109308282A CN109308282A CN201710628203.9A CN201710628203A CN109308282A CN 109308282 A CN109308282 A CN 109308282A CN 201710628203 A CN201710628203 A CN 201710628203A CN 109308282 A CN109308282 A CN 109308282A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of parallel architecture method and device being used in MR mixed reality equipment, receives processing real-time stream by reconfigurable processor, is analyzed as instruction and image data and be sent to respective processor.Graphics image processor carries out real-time rendering to graphic image data, while the idsplay order for receiving central processing unit sending shows image.It is an advantage of the invention that the isomerism parallel form combined using central processing unit, graphics image processor, reconfigurable processor, the high speed processing to data flow is realized using the high concurrent of reconfigurable processor, low-power consumption, restructural feature.Graphics image processor and reconfigurable processor are parallel handled data stream according to director data, improve the speed of processing data, solve the problems, such as that MR device data is handled slow in the prior art, reduce the time overhead for handling this generic task, power consumption.The picture that MR equipment is shown more in real time, promotes user experience.
Description
Technical field
The present invention relates to mixed reality data processing field more particularly to it is a kind of being used in MR mixed reality equipment and
Row framework method and device.
Background technique
The data flow generated in the operation of MR (Mixed Reality, mixed reality) equipment is generally adopted in the prior art
With CPU (Central Processing Unit, central processing unit) and GPU (Graphics Processing Unit, figure
Processor) cooperate with the processing mode handled.In processing data flow procedure, CPU is specifically used to handle complex logic and raising refers to
The execution efficiency of order can handle computation complexity height, but calculated performance is general so causing to calculate versatile.GPU is main
For doing image procossing calculating.
CPU is that data are handled by way of serial process, it lines up received data, one one progress
Processing, processing issue process instruction and data packet, GPU reception to GPU to when needing the GPU cooperation to carry out the task of image procossing
Respective image is handled after to both, is shown after processing.
Since data transmission procedure is also limited by Semiconductor Physics process, the raising of microprocessor arithmetic speed is
Tend to slowly, the parallel computing based on multi-core processor or cluster computer has been increasingly becoming raising Computing
The main means of performance.Include multi-microprocessor in parallel computation equipment, multi-group data can be handled simultaneously, thus
The data-handling capacity of raising system.Supercomputer based on cluster computer has become the large-scale science of solution and engineering is asked
The tool of topic.However, CPU again can line up data in this data flow since the data flow that MR equipment obtains is huge,
Again since CPU is serial process data task, when data are huge exceeds its load, CPU cannot be sent out to GPU in time
Image processing commands are sent, to the slow problem of data processing occur, MR equipment picture is further caused and Caton occurs, very
It crashes to may cause equipment.
Summary of the invention
The present invention provides a kind of parallel architecture method and device being used in MR mixed reality equipment, existing to solve
The slow problem of data processing in MR equipment in technology.
To achieve the goals above, technical solution of the present invention provide it is a kind of be used in it is parallel in MR mixed reality equipment
Framework method, which comprises reconfigurable processor, which receives data flow and carries out data processing to it, obtains data acquisition system, institute
Stating data acquisition system includes director data, graphic image data and remaining data;During director data is sent to by reconfigurable processor
Central processor, graphic image data are sent to graphics image processor;Graphics image processor is to the received graph image
After data are rendered, rendering graphical images are shown according to the idsplay order that the central processing unit received issues
Show;Wherein, the data flow is acquired by data acquisition device, and the reconfigurable processor also sends out the remaining data
It send to the central processing unit and is handled.
As a preferred embodiment of the above technical solution, the method also includes: reconfigurable processors to number in the data acquisition system
It is extracted according to feature.Data with instruction features are director data, and the data with graph image feature are graph image
Data are both remaining data without instruction features or without the data of graph image feature.
As a preferred embodiment of the above technical solution, which comprises central processing unit receives director data;Central processing unit
Director data sends instruction render instruction to the graphics image processor based on the received.
As a preferred embodiment of the above technical solution, the method also includes: graphics image processors to receive instruction idsplay order
And the graphic image data received is rendered according to idsplay order, rendering graphical images are obtained, later, to center
Processor sends rendering and finishes signal;Central processing unit is received after rendering finishes signal and is shown to graphics image processor transmission
Instruction;Graphics image processor shows the rendering graphical images.
As a preferred embodiment of the above technical solution, the method also includes: graphics image processor is respectively to central processing unit
Display, which is sent, with reconfigurable processor finishes signal;After central processing unit receives this signal, phase is also sent to reconfigurable processor
Signal is finished with display;Reconfigurable processor is respectively received the display that central processing unit and graphics image processor are sent
Finish after signal that then the Data Stream Processing finishes.
Technical solution of the present invention additionally provides a kind of parallel architecture device being used in MR mixed reality equipment, the dress
Setting includes: reconfigurable processor receiving unit, receives data flow for reconfigurable processor;Reconfigurable processor data processing list
Member carries out data processing for the reconfigurable processor data flow received to reconfigurable processor receiving unit and obtains data
Set, the data acquisition system includes director data, graphic image data and remaining data;Reconfigurable processor transmission unit is used
In the reconfigurable processor data processing unit is sent to central processing unit by the director data that data processing obtains, scheme
Shape image data is sent to graphics image processor;Rendering unit is sent out for graphics image processor from reconfigurable processor
The graphic image data for sending unit to send is rendered;Graphics image processor receiving unit, for receiving central processing
The idsplay order that device issues is also used to receive the graphic image data that the reconfigurable processor transmission unit is sent;Figure
Shape image processor display unit is used for according to the received idsplay order of graphics image processor receiving unit to rendering graphic diagram
As being shown;Wherein, the data flow is acquired by data acquisition device, the reconfigurable processor data processing list
The remaining data is also sent to the central processing unit and handled by member.
As a preferred embodiment of the above technical solution, in described device, reconfigurable processor data processing unit, comprising: can weigh
Structure processor data processing module obtains institute for carrying out data processing to the received data flow of reconfigurable processor receiving unit
State data acquisition system;Reconfigurable processor data extract categorization module, are used for by reconfigurable processor data processing module number
The feature of data extracts in the data acquisition system obtained according to processing, and is classified according to data characteristics to it, is specifically divided into
Director data, graphic image data and remaining data.Wherein, the data with instruction features are director data, have graphic diagram
It is both described surplus without the data of instruction features or the graph image feature useless as the data of feature are graphic image data
Remainder evidence.
As a preferred embodiment of the above technical solution, described device, after reconfigurable processor transmission unit, further includes: center
Processor receiving unit, for receiving the director data of reconfigurable processor transmission unit transmission;Central processing unit transmission unit,
For sending instruction render instruction to graphics image processor according to the received director data of central processing unit receiving unit;Center
Processor data processing unit, for carrying out data processing to the received remaining data of central processing unit receiving unit;Graphic diagram
As processor receiving unit, the instruction render instruction that central processing unit transmission unit is sent is received for graphics image processor.
As a preferred embodiment of the above technical solution, described device, rendering unit are specifically used for graphics image processor according to figure
The received render instruction of shape image processor receiving unit renders the graphic image data, obtains rendering graphic diagram
Picture.
As a preferred embodiment of the above technical solution, described device, after rendering unit, comprising: graphics image processor is sent
Unit sends rendering to central processing unit after finishing for rendering unit rendering and finishes signal;Central processing unit receiving unit is used
Signal is finished in receiving rendering, later central processing unit transmission unit, sends idsplay order to graphics image processor;Graphic diagram
As processor receiving unit, for receiving the idsplay order of central processing unit transmission unit transmission, later, graphics image processor
The rendering graphical images are shown according to central processing unit idsplay order;Graphics image processor transmission unit, is used for
After the rendering image is shown, shown to central processing unit receiving unit and the transmission of reconfigurable processor receiving unit
Finish signal;Central processing unit receiving unit, the display for receiving the transmission of graphics image processor transmission unit finish signal;In
Central processor transmission unit sends identical display to reconfigurable processor receiving unit for receiving after display finishes signal
Finish signal;Reconfigurable processor receiving unit, for receiving respectively from central processing unit transmission unit and graph and image processing
The display that device transmission unit is sent finishes signal.
Technical solution of the present invention provides a kind of parallel architecture method being used in MR mixed reality equipment, comprising: can
Reconfigurable processor, which receives data flow and carries out data processing to it, obtains data acquisition system.Data acquisition system includes director data, figure
Image data and remaining data.Director data is sent to central processing unit by reconfigurable processor, and graphic image data is sent to
Graphics image processor.Graphics image processor renders graphic image data, according to connecing the aobvious of central processing unit sending
Show that instruction shows graph image.Technical solution of the present invention additionally provide it is a kind of being used in MR mixed reality equipment and
Row architecture device, comprising: reconfigurable processor receiving unit receives data flow for programmable logic reconfigurable processor.It can
Reconfigurable processor data processing unit carries out data processing for received data flow and obtains data acquisition system.Data acquisition system includes
Director data, graphic image data and remaining data.Reconfigurable processor transmission unit, for director data to be sent to center
Processor, graphic image data are sent to graphics image processor.Rendering unit, for graphics image processor to graph image
Data are rendered.Graphics image processor receiving unit is also used to receive graphic image data for receiving idsplay order.
Graphics image processor display unit shows the graph image after rendering for idsplay order.It is an advantage of the invention that
The isomeric form combined using central processing unit, graphics image processor, reconfigurable processor.Since reconfigurable processor has
High concurrent, low-power consumption, restructural feature.The present invention utilizes the characteristics of reconfigurable processor to realize to the high speed of data flow
Reason, central processing unit convey instruction by way of serial process, and graphics image processor and reconfigurable processor are according to center
The parallel instructions that processor is conveyed carry out data processing to data stream, to improve the speed of processing data flow, solve existing
There is in technology the slow problem of data processing in MR equipment.Also reduce the time overhead for handling this generic task in the prior art, function
Consumption.The picture that MR equipment is shown is more real-time, promotes user experience.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to make one simply to introduce, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of process for the parallel architecture method being used in MR mixed reality equipment provided in an embodiment of the present invention
Figure;
Fig. 2 is a kind of parallel architecture method being used in MR mixed reality equipment that further embodiment of this invention provides
Flow chart;
Fig. 3 is a kind of structure for the parallel architecture device being used in MR mixed reality equipment provided in an embodiment of the present invention
Schematic diagram one;
Fig. 4 is the structural schematic diagram of reconfigurable processor data processing unit 32 shown in Fig. 3;
Fig. 5 is a kind of structure for the parallel architecture device being used in MR mixed reality equipment provided in an embodiment of the present invention
Schematic diagram two;
Fig. 6 is a kind of structure for the parallel architecture device being used in MR mixed reality equipment provided in an embodiment of the present invention
Schematic diagram three.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is a kind of process for the parallel architecture method being used in MR mixed reality equipment provided in an embodiment of the present invention
Figure, as shown in Figure 1, comprising:
Step 101, reconfigurable processor, which receive data flow and carry out data processing to it, obtains data acquisition system.
Step 102, reconfigurable processor extract data characteristics in the data acquisition system, and extraction obtains instruction number
According to, graphic image data and remaining data.
Wherein, the data with instruction features are described instruction data, and the data with graph image feature are the figure
Shape image data is both the remaining data without described instruction feature or without the data of the graph image feature.
Director data and remaining data are sent to central processing unit by step 103, reconfigurable processor, by graph image number
According to being sent to graphics image processor.
Specifically, central processing unit handles received remaining data immediately.
Step 104, central processing unit receive director data and send instruction render instruction to graphics image processor.
Step 105: graphics image processor receives instruction render instruction, and carries out wash with watercolours to the graphic image data received
Dye, obtain rendering graphical images, it is rear to central processing unit send rendering finish signal.
Step 106, central processing unit receive rendering and finish signal graph image processor transmission idsplay order, graph image
Processor shows rendering graphical images.
Step 107, graphics image processor send display to central processing unit and reconfigurable processor respectively and finish signal.
After step 108, central processing unit reception display finish signal, identical display is sent to reconfigurable processor and finishes letter
Number.
It is complete that step 109, reconfigurable processor are respectively received the display that central processing unit and graphics image processor are sent
Finish signal.
Technical solution of the present invention provides a kind of parallel architecture method being used in MR mixed reality equipment, by that can weigh
Structure processor, which receives data flow and carries out data processing to it, obtains data acquisition system.Wherein, data acquisition system includes director data, figure
Shape image data and remaining data.Director data is sent to central processing unit by reconfigurable processor, and graphic image data is sent
To graphics image processor.Graphics image processor renders graphic image data, according to connect central processing unit sending
Idsplay order shows rendering graphical images, and display result is fed back to central processing unit and reconfigurable processor.Solution
The slow problem of data processing in MR equipment in the prior art of having determined.It also reduces and handles time of this generic task in the prior art and open
Pin, power consumption.The picture that MR equipment is shown is more real-time, and the user experience is improved.
A current specific embodiment describes technical solution of the present invention, in the present embodiment, specifically by taking image data stream as an example
It is illustrated.Not to limit data stream type.In the present embodiment, reconfigurable processor is with FPGA (Field-
Programmable Gate Array, field programmable gate array) for be illustrated, graphics image processor is by taking GPU as an example
It is illustrated, central processing unit is illustrated by taking CPU as an example, and the above citing in technical solution of the present invention not to being used
Processor type limited.
Fig. 2 is a kind of parallel architecture method being used in MR mixed reality equipment that further embodiment of this invention provides
Flow chart, as shown in Figure 2:
Step 201, FPGA receive the image data stream that image acquisition components obtain.
Logic gate carries out data processing to image data stream in step 202, FPGA, obtains data acquisition system, extracts data set
Data characteristics in conjunction.
Data characteristics includes: instruction features and characteristics of image.
Specifically, since each logic gate in FPGA in each clock cycle while carrying out logical operation, FPGA
Specifically to the real-time processing of image data and algorithm data in data flow.
Step 203, according to data characteristics to data sets classification, including director data, graphic image data and remainder
According to.
Data with instruction features are director data, and the data with characteristics of image are image data, both without described
The data of characteristics of image are not remaining data to instruction features yet.
Wherein, director data and remaining data are low speed data, and image data is high-speed data.Low speed data can also be
Temperature data, the small data of the data volumes such as humidity data;High-speed data can be, position data, audio data, video data,
The big data of the data volumes such as three-dimensional modeling data.
Director data and remaining data are sent to CPU by step 204, FPGA.
Step 205, CPU carry out data processing to remaining data.
Graphic image data is sent to GPU by step 206, FPGA.
Step 207, CPU send instruction render instruction to GPU.
Step 208, GPU render graphic image data, obtain rendering image.
GPU provides a large amount of computing unit (up to thousands of a computing units) and a large amount of high-speed internal memory, can be right simultaneously
More pixels carry out parallel processing.
Step 209, GPU send rendering to CPU and finish signal.
Step 210, CPU send idsplay order to GPU.
Step 211, GPU show rendering image.
Step 212, GPU send display to CPU and finish signal.
Step 213, GPU send display to FPGA and finish signal.
Step 214, CPU send display to FPGA and finish signal.
The another technical solution of the present invention provides a kind of parallel architecture method being used in MR mixed reality equipment, passes through
FPGA, which receives the data flow that MR equipment generates and carries out data processing to it, obtains the number being made of image data and algorithm data
According to set.FPGA classifies data acquisition system, and director data class is sent to CPU, and image data class is sent to GPU.GPU is to picture number
According to being rendered, and image is shown, display result is fed back into CPU and FPGA.CPU is merely responsible for referring in the present invention
Part is enabled, a large amount of data calculate by having the characteristics that high concurrent, low-power consumption, restructural FPGA are realized, prevented CPU and existed
The problem that defect when operation due to serial process causes data processing slow.It solves in MR equipment in the prior art at data
Manage slow problem.Also reduce the time overhead for handling this generic task in the prior art, power consumption.So that the picture that MR equipment is shown
Can be more real-time, the user experience is improved.
Fig. 3 is a kind of knot for parallel architecture device being used in MR mixed reality equipment that technical solution of the present invention provides
Structure schematic diagram one, specifically, as shown in Figure 3:
Reconfigurable processor receiving unit 31, specifically in MR mixed reality equipment image acquiring device capture figure
As after, reconfigurable processor is sent by the data flow of generation, then reconfigurable processor receives data flow.
Reconfigurable processor data processing unit 32 receives reconfigurable processor for reconfigurable processor in MR equipment
The received data flow of unit 31 carries out data processing, obtains data acquisition system.The data acquisition system includes director data, graph image
Data and remaining data.
Reconfigurable processor transmission unit 33 is specifically used for passing through reconfigurable processor data processing unit 32 at data
The director data and remaining data that reason obtains are sent to the central processing unit in MR equipment, and graphic image data is sent to MR equipment
In graphics image processor.
Rendering unit 34, for graphics image processor to the figure sent from the reconfigurable processor transmission unit 33
Image data is rendered.
Graphics image processor receiving unit 35 receives central processing unit hair for the graphics image processor in MR equipment
Idsplay order out is also used to graphics image processor and receives the graph image number that reconfigurable processor transmission unit 33 is sent
According to.
Graphics image processor display unit 36, for according to the received idsplay order of graphics image processor receiving unit
Rendering graphical images are shown in MR equipment.
As shown in figure 4, reconfigurable processor data processing unit 32, comprising:
Reconfigurable processor data processing module 41, for being flowed into the received data of reconfigurable processor receiving unit 31
Row data processing obtains data acquisition system.
Reconfigurable processor data extract categorization module 42, according to pass through 41 data of reconfigurable processor data processing module
It handles feature possessed by the data in obtained data acquisition system to extract, and it is divided according to the data characteristics
Class is specifically divided into director data, graphic image data and remaining data.
Data with instruction features are director data, and the data with graph image feature are graphic image data, both
Do not have instruction features also graph image feature useless data be remaining data.
Fig. 5 is a kind of structure for the parallel architecture device being used in MR mixed reality equipment provided in an embodiment of the present invention
Schematic diagram two, as shown in figure 5, after reconfigurable processor transmission unit 33, further includes:
Central processing unit receiving unit 51 receives reconfigurable processor transmission unit for the central processing unit in MR equipment
33 director datas and remaining data sent.
Central processing unit transmission unit 52, for being set according to the received director data of central processing unit receiving unit 51 to MR
Graphics image processor in standby sends instruction render instruction.
Central processing unit data processing unit 53, for being carried out to the received remaining data of central processing unit receiving unit 51
Data processing.
Graphics image processor receiving unit 35 receives central processing unit transmission unit 52 for graphics image processor and sends out
The instruction render instruction sent.
In the technical solution of the present invention, rendering unit 34, specifically for the graphics image processor in MR equipment according to figure
The received render instruction of shape image processor receiving unit 35 renders graphic image data, to obtain rendering graphic diagram
Picture.
Fig. 6 is a kind of structure for the parallel architecture device being used in MR mixed reality equipment provided in an embodiment of the present invention
Schematic diagram three, as shown in fig. 6, after 34 after rendering unit, comprising:
Graphics image processor transmission unit 61 renders the central processing after finished into MR equipment for rendering unit 34
Device sends rendering and finishes signal.
Central processing unit receiving unit 51 receives what graphics image processor transmission unit 61 was sent for central processing unit
Rendering finishes signal.
Central processing unit transmission unit 52, receives rendering and finishes and set after signal to MR in central processing unit receiving unit 51
Graphics image processor in standby sends idsplay order.
Graphics image processor receiving unit 35 receives central processing unit for graphics image processor in MR equipment and sends
The idsplay order that unit 52 is sent.
Graphics image processor display unit 36, for being existed according to the received idsplay order of central processing unit receiving unit 51
Rendering graphical images are shown on the display screen of MR equipment.
Graphics image processor transmission unit 61 is also used to after graphics image processor shows rendering image,
Display, which is sent, to central processing unit receiving unit 51 and reconfigurable processor receiving unit 31 finishes signal.
Central processing unit receiving unit 51 receives what graphics image processor transmission unit 61 was sent for central processing unit
Display finishes signal.
Central processing unit transmission unit 52, is used for, and the central processing unit receiving unit 51 in MR equipment receives graph image
After the display that processor is sent finishes signal, identical display is sent to reconfigurable processor receiving unit 31 and finishes signal.
Reconfigurable processor receiving unit 31 receives respectively from the central processing unit transmission unit 52 and figure in MR equipment
The display that image processor transmission unit 61 is sent finishes signal.
Technical solution of the present invention provides a kind of parallel architecture device being used in MR mixed reality equipment.Restructural place
Device receiving unit is managed, receives data flow for reconfigurable processor.Reconfigurable processor data processing unit is by received data
Stream carries out data processing and obtains data acquisition system, and data acquisition system includes director data and graphic image data.Reconfigurable processor hair
Send unit that director data is sent to central processing unit, graphic image data is sent to graphics image processor.Rendering unit pair
Graphic image data is rendered.Graphics image processor receiving unit receives idsplay order, also reception reconfigurable processor hair
The graphic image data for sending unit to send.Graphics image processor display unit shows described image according to idsplay order
Show.Central processing unit is merely responsible for operation part in the technical solution of the present invention, and a large amount of data are calculated by with high concurrent, low
Power consumption, restructural feature reconfigurable processor realized, prevented central processing unit at runtime due to serial process
The slow problem of data processing caused by defect.Solve the problems, such as that data processing is slow in MR equipment in the prior art.Also drop
The low time overhead for handling this generic task in the prior art, power consumption.The picture that MR equipment is shown is more real-time, is promoted
User experience.
It should be noted that graph image involved in technical solution of the present invention, can be face graph image, gesture figure
Shape image, object representation image etc., these images can be 2D graph image, be also possible to 3D graph image and it is other can
Other figures of data processing are carried out by central processing unit, graphics image processor, the reconfigurable processor in the technical program
Image.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations;To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement;And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of parallel architecture method being used in MR mixed reality equipment, which is characterized in that the method, comprising:
Reconfigurable processor, which receives data flow and carries out data processing to it, obtains data acquisition system, and the data acquisition system includes instruction
Data, graphic image data and remaining data;
Described instruction data are sent to central data processor by the reconfigurable processor, and the graphic image data is sent to
Graphics image processor;
After the graphics image processor renders the received graphic image data, according to the center received
The idsplay order that processor issues shows rendering graphical images;
Wherein, the data flow is acquired by data acquisition device, and the reconfigurable processor is also by the remaining data
The central processing unit is sent to be handled.
2. the method according to claim 1, wherein the reconfigurable processor receives data flow and carries out to it
Data processing obtains data acquisition system, and the data acquisition system includes director data, graphic image data and remaining data, comprising:
The reconfigurable processor extracts data characteristics in the data acquisition system;
Data with instruction features are described instruction data, and the data with graph image feature are the graph image number
According to, both without described instruction feature and also without the graph image feature data be the remaining data.
3. the method according to claim 1, wherein described instruction data are sent to by the reconfigurable processor
Central processing unit, the graphic image data are sent to graphics image processor, further includes:
The central processing unit receives described instruction data;
Central processing unit based on the received director data to the graphics image processor send instruction render instruction.
4. according to the method described in claim 3, it is characterized in that, the graphics image processor is to the received graphic diagram
After being rendered as data, rendering graphical images are shown according to the idsplay order that the central processing unit received issues
Show, comprising:
The graphics image processor receives the instruction idsplay order;
Graphics image processor renders the graphic image data received according to idsplay order, obtains rendering figure
Image sends rendering to central processing unit after finishing and finishes signal;
Central processing unit, which receives the rendering and finishes, sends idsplay order to graphics image processor after signal;
Graphics image processor shows the rendering graphical images.
5. according to the method described in claim 4, it is characterized in that, the graphics image processor carries out the rendering image
After display, comprising:
The graphics image processor sends display to the central processing unit and the reconfigurable processor respectively and finishes signal;
After the display that the central processing unit receives graphics image processor transmission finishes signal, to the reconfigurable processor
Also it sends identical display and finishes signal;
Reconfigurable processor is respectively received the display that central processing unit and graphics image processor are sent and finishes signal.
6. a kind of parallel architecture device being used in MR mixed reality equipment, which is characterized in that described device, comprising:
Reconfigurable processor receiving unit receives data flow for reconfigurable processor;
Reconfigurable processor data processing unit connects the reconfigurable processor receiving unit for the reconfigurable processor
The data flow received carries out data processing and obtains data acquisition system, and the data acquisition system includes director data, graphic image data
And remaining data;
Reconfigurable processor transmission unit, for obtain the reconfigurable processor data processing unit by data processing
Described instruction data are sent to central processing unit, and the graphic image data is sent to graphics image processor;
Rendering unit, for the graphics image processor to the figure sent from the reconfigurable processor transmission unit
Image data is rendered;
Graphics image processor receiving unit, the idsplay order issued for receiving the central processing unit, is also used to receive institute
State the graphic image data of reconfigurable processor transmission unit transmission;
Graphics image processor display unit, for according to the received idsplay order pair of graphics image processor receiving unit
Rendering graphical images are shown;
Wherein, the data flow is acquired by data acquisition device, and the reconfigurable processor data processing unit will also
The remaining data is sent to the central processing unit and is handled.
7. device according to claim 6, which is characterized in that the reconfigurable processor data processing unit, comprising:
Reconfigurable processor data processing module, for being carried out at data to the received data flow of reconfigurable processor receiving unit
Reason obtains the data acquisition system;
Reconfigurable processor data extract categorization module, for at by the reconfigurable processor data processing module data
The feature for managing data in the obtained data acquisition system extracts, and is classified according to the data characteristics to it, specifically
It is divided into director data, graphic image data and remaining data;
Wherein, the data with instruction features are described instruction data, and the data with graph image feature are the graphic diagram
It is both the remaining data without the data of described instruction feature or the graph image feature useless as data.
8. the apparatus according to claim 1, which is characterized in that after the reconfigurable processor transmission unit, further includes:
Central processing unit receiving unit, the described instruction data sent for receiving the reconfigurable processor transmission unit;
Central processing unit transmission unit, for according to the received described instruction data of the central processing unit receiving unit to figure
Image processor sends instruction render instruction;
Central processing unit data processing unit, for being carried out at data to the received remaining data of central processing unit receiving unit
Reason;
Graphics image processor receiving unit receives what the central processing unit transmission unit was sent for graphics image processor
The instruction render instruction.
9. device according to claim 8, which is characterized in that the rendering unit is specifically used at the graph image
Reason device renders the graphic image data according to the received render instruction of graphics image processor receiving unit, obtains
To the rendering graphical images.
10. device according to claim 9, which is characterized in that after the rendering unit, comprising:
Graphics image processor transmission unit sends rendering to central processing unit after finishing for rendering unit rendering and finishes
Signal;
Central processing unit receiving unit, the rendering for receiving the transmission of graphics image processor transmission unit finish signal;
Central processing unit transmission unit finishes after signal for receiving the rendering in central processing unit receiving unit to figure
Image processor sends idsplay order;
Graphics image processor receiving unit, for receiving the idsplay order of central processing unit transmission unit transmission;
Graphics image processor display unit is used for according to the received idsplay order of central processing unit receiving unit to the rendering
Graph image is shown;
Graphics image processor transmission unit, for being received to the central processing unit after the rendering image is shown
Unit and the reconfigurable processor receiving unit send display and finish signal;
Central processing unit receiving unit, the display for receiving the transmission of graphics image processor transmission unit finish signal;
Central processing unit transmission unit, for the central processing unit receiving unit receive it is described display finish signal after, to
The reconfigurable processor receiving unit sends identical display and finishes signal;
Reconfigurable processor receiving unit is sent from central processing unit transmission unit and graphics image processor respectively for receiving
The display that unit is sent finishes signal.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110138769A (en) * | 2019-05-09 | 2019-08-16 | 深圳市腾讯网域计算机网络有限公司 | A kind of method and relevant apparatus of image transmitting |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050122333A1 (en) * | 2003-12-05 | 2005-06-09 | Siemens Medical Solutions Usa, Inc. | Graphics processing unit for simulation or medical diagnostic imaging |
CN101216931A (en) * | 2007-12-29 | 2008-07-09 | 长城信息产业股份有限公司 | 3D graphical display superposition device based on OpenGL |
US7522167B1 (en) * | 2004-12-16 | 2009-04-21 | Nvidia Corporation | Coherence of displayed images for split-frame rendering in multi-processor graphics system |
US20100328327A1 (en) * | 2009-06-30 | 2010-12-30 | Arnaud Hervas | Multi-platform Optimization Techniques for Image-Processing Operations |
CN203250508U (en) * | 2013-04-24 | 2013-10-23 | 苏州创捷传媒展览股份有限公司 | Three-dimensional mixed reality display device |
CN104688273A (en) * | 2015-03-16 | 2015-06-10 | 哈尔滨工业大学 | Ultra high speed ultrasonic imaging device and method based on central processing unit (CPU) + graphic processing unit (GPU) isomeric framework |
CN104820207A (en) * | 2015-05-08 | 2015-08-05 | 中国科学院新疆天文台 | Real-time correlator based on FPGA, GPU and CPU mixed architecture |
CN105427236A (en) * | 2015-12-18 | 2016-03-23 | 魅族科技(中国)有限公司 | Method and device for image rendering |
CN106708777A (en) * | 2017-01-23 | 2017-05-24 | 张军 | Multi-core heterogeneous CPU - CPU - FPGA architecture |
-
2017
- 2017-07-28 CN CN201710628203.9A patent/CN109308282A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050122333A1 (en) * | 2003-12-05 | 2005-06-09 | Siemens Medical Solutions Usa, Inc. | Graphics processing unit for simulation or medical diagnostic imaging |
US7522167B1 (en) * | 2004-12-16 | 2009-04-21 | Nvidia Corporation | Coherence of displayed images for split-frame rendering in multi-processor graphics system |
CN101216931A (en) * | 2007-12-29 | 2008-07-09 | 长城信息产业股份有限公司 | 3D graphical display superposition device based on OpenGL |
US20100328327A1 (en) * | 2009-06-30 | 2010-12-30 | Arnaud Hervas | Multi-platform Optimization Techniques for Image-Processing Operations |
CN203250508U (en) * | 2013-04-24 | 2013-10-23 | 苏州创捷传媒展览股份有限公司 | Three-dimensional mixed reality display device |
CN104688273A (en) * | 2015-03-16 | 2015-06-10 | 哈尔滨工业大学 | Ultra high speed ultrasonic imaging device and method based on central processing unit (CPU) + graphic processing unit (GPU) isomeric framework |
CN104820207A (en) * | 2015-05-08 | 2015-08-05 | 中国科学院新疆天文台 | Real-time correlator based on FPGA, GPU and CPU mixed architecture |
CN105427236A (en) * | 2015-12-18 | 2016-03-23 | 魅族科技(中国)有限公司 | Method and device for image rendering |
CN106708777A (en) * | 2017-01-23 | 2017-05-24 | 张军 | Multi-core heterogeneous CPU - CPU - FPGA architecture |
Non-Patent Citations (1)
Title |
---|
裴鑫等: "基于混合架构的双通道实时相关器实现", 《计算机工程》 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110138769A (en) * | 2019-05-09 | 2019-08-16 | 深圳市腾讯网域计算机网络有限公司 | A kind of method and relevant apparatus of image transmitting |
CN110138769B (en) * | 2019-05-09 | 2021-06-15 | 深圳市腾讯网域计算机网络有限公司 | Image transmission method and related device |
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