CN109299030A - The method that cameralink based on ZYNQ turns PAL system - Google Patents
The method that cameralink based on ZYNQ turns PAL system Download PDFInfo
- Publication number
- CN109299030A CN109299030A CN201811050894.XA CN201811050894A CN109299030A CN 109299030 A CN109299030 A CN 109299030A CN 201811050894 A CN201811050894 A CN 201811050894A CN 109299030 A CN109299030 A CN 109299030A
- Authority
- CN
- China
- Prior art keywords
- data
- module
- cameralink
- pal
- fifo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Studio Devices (AREA)
Abstract
The invention discloses the method that the cameralink based on ZYNQ turns PAL system, realize that cameralink data flow inputs all the way, PAL system data flow and cameralink data flow export all the way.This method uses Read-write Catrol module of the VDMA as DDR3, VDMA is controlled by the part PS of ZYNQ chip and carries out reading and writing data, DDR3 is written into cameralink data flow line by line, data are read from DDR3 with time-division two-way, read out as cameralink output line by line all the way, another way interlacing reads out as PAL output.
Description
Technical field
The present invention relates to the methods that the cameralink based on ZYNQ turns PAL system.
Background technique
With the fast development of computer, multimedia and digital communication technology, video technique has obtained great promotion, so
And various cameras, display equipment and the interface inter-link problem acquired between equipment more protrude.Cameralink (data transmission association
View) it is a serial communication protocol standard released on the basis of channel-link (Data Transport Protocol), it is a kind of special
For the communication protocol of field of machine vision, Low Voltage Differential Signal LVDS (Low-Voltage Different Signal is used
Low Voltage Differential Signal) it is transmitted.PAL system (PAL system Phase Alteration Line swings to system line by line) is a kind of TV
Standard, using interleaved method output data.Cameralink (Data Transport Protocol) and PAL (PAL system Phase
Alteration Line swings to system line by line) it is two kinds of entirely different data-transmission modes, the two is incompatible, if therefore regarding
Frequency acquisition uses cameralink (Data Transport Protocol) camera, and rear end is shown using PAL (PAL system Phase Alteration
Line swings to system line by line) display, it must format therebetween.Most common method is using PAL (PAL system
Phase Alteration Line swings to system line by line) codec chip processed carries out data flow generation, such as CH7024 (chip-shaped
Number).However this method needs to increase the number of chips and circuit board volume of whole plate, is unfavorable for the miniaturization and low-power consumption of product
Design.
Summary of the invention
The purpose of the method for the present invention is that provides a kind of real based on ZYNQ (chip series that match company of Sentos releases) platform
It is aobvious that existing cameralink (Data Transport Protocol) turns PAL (PAL system Phase Alteration Line swings to system line by line) system
Show method, inputs as cameralink all the way (Data Transport Protocol) data flow, export as PAL (PAL system Phase
Alteration Line swings to system line by line) data flow processed and cameralink (Data Transport Protocol) data flow, this method will
Cameralink (Data Transport Protocol) stream compression changes AXI4-Stream (bus protocol) data flow into, by VDMA core
(the direct accessor of Video Direct Memory Access video) controls a kind of DDR3 (computer storage specification) memory will
A kind of DDR3 (computer storage specification) memory is written in data line by line, then by VDMA (Video Direct Memory Access
The direct accessor of video) data are divided two-way to read by a kind of control DDR3 (computer storage specification) memory, and interlacing is read all the way,
It makes and exports for PAL (PAL system Phase Alteration Line swings to system line by line), read, be used for line by line all the way
Cameralink (Data Transport Protocol) output.This two paths of data is by ZYNQ (chip series that match company of Sentos releases) chip
PL (Programmable Logic programmable logic) partially uses hardware language VHDL (a kind of hardware program language) or verilog
(a kind of hardware program language) carries out PAL system coding to it respectively and encodes with cameralink (Data Transport Protocol).This method
It does not need additionally to reduce whole plate volume and weight using dedicated codec chip, be conducive to the miniaturization low-power consumption of product
Design.
Realize technical solution of the invention are as follows: one kind is based on ZYNQ (chip series that match company of Sentos releases) platform
The cameralink (Data Transport Protocol) of realization turns PAL (PAL system Phase Alteration Line swings to system line by line) system
Display methods, including following module: cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module, is
System reseting module, PLL (Phase-Locked Loop phase-locked loop) module, memory write data control module, PAL (PAL system
Phase Alteration Line swings to system line by line) memory read data control module, in cameralink (Data Transport Protocol)
Deposit read data control module, PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module,
(PAL system Phase Alteration Line is line by line by cameralink (Data Transport Protocol) output data cache module, PAL
The system of swinging to) output timing generation module, cameralink (Data Transport Protocol) output timing generation module, implement step
It is as follows:
Step 1, cameralink (Data Transport Protocol) data flow of front-end image acquisition equipment output is with fixed frequency
F1 (generally 30,000,000) write-in cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module, and system is multiple
Position module is that remaining module in addition to cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module mentions
For reset signal；
Step 2, cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module for fixed frequency f1
AXI4-Stream (bus protocol) data flow that the stream compression of (generally 30,000,000) changes 100,000,000 into is read, and memory is written and writes
In the memory of data control block；
Step 3, the data in memory read time-division two paths of data stream, are used for PAL (PAL system Phase all the way
Alteration Line swings to system line by line) system display, it is shown all the way for cameralink (Data Transport Protocol), wherein
PAL (PAL system Phase Alteration Line swings to system line by line) memory read data control module is with 100,000,000 speed from interior
Middle reading data are deposited, and are transferred to PAL (PAL system Phase Alteration Line swings to system line by line) output data caching mould
Block；Cameralink (Data Transport Protocol) memory read data control module reads data with 100,000,000 speed from memory, and
Output data to cameralink (Data Transport Protocol) data cache module；
Step 4, PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module is with admittedly
Determining frequency f2 (generally 13.5 million), to write data into PAL (PAL system Phase Alteration Line swings to system line by line) defeated
Timing generation module out；Cameralink (Data Transport Protocol) output data cache module is write data into fixed frequency f1
Cameralink (Data Transport Protocol) output timing generation module, wherein the clock of fixed frequency f2 is by PLL (Phase-
Locked Loop phase-locked loop) module offer；
Step 5, PAL (PAL system Phase Alteration Line swings to system line by line) output timing control module according to
The timing requirements of PAL (PAL system Phase Alteration Line swings to system line by line) system display, generate row field signal and blanking
Signal；According to the timing of the row field signal of generation and blanking signal adjustment front end data stream, the PAL (PAL system of standard is formed
Phase Alteration Line swings to system line by line) data flow processed.
The cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module and calls vivado
(developing instrument that xilinx company provides) included IP (Intellectual Property core IP core) core will
Cameralink (Data Transport Protocol) stream compression changes AXI4-Stream (bus protocol) data flow into, wherein FIFO
(First input First Output First Input First Output) depth is set as 1024, and input data 8, output data 8.
Described memory write data control module module is called in vivado (developing instrument that xilinx company provides)
VDMA (the direct accessor of Video Direct Memory Access video) core writes data into memory, wherein data buffer storage
It is set as caching n frame (generally 3 frames).
(Video Direct Memory Access video directly accesses VDMA in the memory write data control module
Device) rate-determining steps of core include: that partially (high speed storing component, can by register by PS (Process System processing system)
For keep in instruction, data, address) configuration mode, informing VDMA (Video Direct Memory Access video is direct
Accessor) each frame data of core storage first address and data location mode.
VDMA (the direct accessor of Video Direct Memory Access video) core in memory write data control module
Register configuration method include: that each frame is configured by register S2MM_START_ADDRESS (high speed storing unit number)
The first address of data storage, caching n frame need to configure n first address；It (is deposited at a high speed by register S2MM_FRMDLY_STRIDE
Storage unit number) configuration data are written line by line in the memory of memory write data control module.
PAL (PAL system Phase Alteration Line swings to system line by line) the memory read data control module is called
VDMA in vivado (developing instrument that xilinx company provides) (directly visit by Video Direct Memory Access video
Ask device) data now read in memory are verified, wherein data buffer storage is set as 2n.
In PAL (PAL system Phase Alteration Line swings to system line by line) the memory read data control module
VDMA (the direct accessor of Video Direct Memory Access video) the nuclear control method of reading includes: PS (Process
System processing system) partially by way of register configuration, inform VDMA (Video Direct Memory Access view
Frequently direct accessor) each frame data first address and data reading mode that read.
The PS (Process System processing system) of VDMA core in the PAL memory read data control module is partially posted
Storage control method includes: to configure each frame data by register MM2S_START_ADDRESS (high speed storing unit number)
The first address of reading, caching 2n frame need to configure 2n first address；Pass through register MM2S_FRMDLY_STRIDE (high speed storing
Unit number) configuration is that a kind of data in DDR3 (computer storage specification) are read line by line.
Cameralink (Data Transport Protocol) the memory read data control module calls vivado, and (xilinx company mentions
The developing instrument of confession) in VDMA (the direct accessor of Video Direct Memory Access video) verify it is existing with 100,000,000
Speed data are read from memory, and output data to cameralink (Data Transport Protocol) data cache module, wherein
Data buffer storage is set as n frame.
Reading VDMA (Video Direct in cameralink (Data Transport Protocol) the memory read data control module
The direct accessor of Memory Access video) nuclear control method includes: that PS (Process System processing system) partially passes through
The mode of register configuration informs VDMA (the direct accessor of Video Direct Memory Access video) each frame data
The first address and data reading mode of reading；
PS (Process System processing system) component register control method of VDMA core includes: to pass through register
MM2S_START_ADDRESS (high speed storing unit number) configures the first address that each frame data are read, and caching n frame needs are matched
Set n first address；It is a kind of DDR3 (calculating by register MM2S_FRMDLY_STRIDE (high speed storing unit number) configuration
Machine store specification) in data read line by line；
PAL (PAL system Phase Alteration Line swings to system line by line) the output data cache module includes the
One FIFO (First input First Output First Input First Output) module and the first FIFO (First input
First Output First Input First Output) time-sequence control module, (First input First Output is first by the first FIFO
Enter first dequeue) the module IP (Intellectual that calls vivado (xilinx company provide developing instrument) included
Property core IP core) core, the first FIFO time-sequence control module, which generates, to be controlled the reset signal of FIFO, reads
Write enable signal, read-write clock, when FIFO (First input First Output First Input First Output) write enable signal is
High level, PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module with 100,000,000 when
FIFO (First input First Output First Input First Output) is written in front end data by clock；As FIFO (First input
First Output First Input First Output) read enable signal be high level when, PAL (PAL system Phase Alteration Line
Swing to system line by line) output data cache module with 13.5 million clock by data from FIFO (First input First
Output First Input First Output) in read；FIFO (First input First Output First Input First Output) reset signal
It is provided by system reset module, when reset signal is effective, empties FIFO (First input First Output first in, first out
Queue)；
The cameralink output data cache module includes that (First input First Output is first by the 2nd FIFO
Enter first dequeue) module and the 2nd FIFO time-sequence control module, the IP that second fifo module calls vivado included
(Intellectual Property core IP core) core, the 2nd FIFO (the First input First
Output First Input First Output) time-sequence control module generation control FIFO (First input First Output first in, first out
Queue) reset signal, read-write enable signal, read-write clock；When FIFO (First input First Output first in, first out
Queue) write enable signal be high level, cameralink (Data Transport Protocol) output data cache module is with 100,000,000 clock
FIFO is written into front end data；It is height when FIFO (First input First Output First Input First Output) reads enable signal
When level, cameralink (Data Transport Protocol) output data cache module is with 30,000,000 clock by data from FIFO (First
Input First Output First Input First Output)；When FIFO (First input First Output First Input First Output)
Middle reading；FIFO (First input First Output First Input First Output)；As FIFO (First input First
Output First Input First Output) reset signal provides by system reset module, when reset signal is effective, empty FIFO (First
Input First Output First Input First Output)；When FIFO (First input First Output First Input First Output)；
The IP that the system reset module calls vivado (developing instrument that xilinx company provides) included
(Intellectual Property core IP core) core gives PLL (Phase-Locked Loop phase-locked loop) mould
Block, cameralink (Data Transport Protocol) turn AXI4_Stream (bus protocol) module, memory write data control module, PAL
(PAL system Phase Alteration Line swings to system line by line) memory read data control module, cameralink (data transmission
Agreement) memory read data control module, PAL (PAL system Phase Alteration Line swings to system line by line) output data be slow
Storing module, cameralink (Data Transport Protocol) output data cache module provide reset signal；
PLL (the Phase-Locked Loop phase-locked loop) Module implementations are to call vivado (xilinx company
The developing instrument of offer) included IP (Intellectual Property core IP core) core, PLL (Phase-
Locked Loop phase-locked loop) module with PS (Process System processing system) part provide 100,000,000 system clocks make
For benchmark clock, 13.5 million, 30,000,000 clock is generated, (PAL system Phase Alteration Line falls line by line to PAL respectively
To system) output timing generation module and cameralink (Data Transport Protocol) output timing generation module use.
Detailed description of the invention
The present invention is done with reference to the accompanying drawings and detailed description and is further illustrated, it is of the invention above-mentioned or
Otherwise advantage will become apparent.
Fig. 1 is overall data flow diagram.
Fig. 2 is integral frame structure figure.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and embodiments.
Realize technical solution of the invention are as follows: one kind is based on ZYNQ (chip series that match company of Sentos releases) platform
The cameralink (Data Transport Protocol) of realization turns PAL (PAL system Phase Alteration Line swings to system line by line) system
Display methods, as shown in Figures 1 and 2, comprising the following steps:
Step 1, cameralink (Data Transport Protocol) data flow in front end is with 30,000,000 clock write-in cameralink (number
According to transport protocol) turn AXI4-Stream (bus protocol) module.
Step 2, cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module for 30,000,000 data
Circulation changes the reading of 100,000,000 data flows into, and a kind of DDR3 (computer storage specification) memory write data control module, DDR3 is written
A kind of (computer storage specification) memory write data control module writes data into DDR3 (a kind of computer storage specification).
Step 3, the data in DDR3 (a kind of computer storage specification) read time-division two paths of data stream, are used for PAL all the way
(PAL system Phase Alteration Line swings to system line by line) system display, all the way for cameralink (data transmission association
View) display, wherein PAL (PAL system Phase Alteration Line swings to system line by line) memory read data control module with
100000000 speed reads data from DDR3 (a kind of computer storage specification), and is transferred to PAL (PAL system Phase
Alteration Line swings to system line by line) output data cache module；Cameralink (Data Transport Protocol) memory reads data
Control module reads data with 100,000,000 speed from DDR3 (a kind of computer storage specification), and outputs data to
Cameralink (Data Transport Protocol) data cache module.
Step 4, PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module is used
13.5 million clocks write data into PAL (PAL system Phase Alteration Line swings to system line by line) output timing and generate mould
Block；Cameralink (Data Transport Protocol) output data cache module writes data into cameralink (number with 30,000,000 clocks
According to transport protocol) output timing generation module.
Step 5, PAL (PAL system Phase Alteration Line swings to system line by line) output timing generation module will before
It holds the data flow sent to be packaged into meet PAL (PAL system Phase Alteration Line swings to system line by line) display timing and want
The data flow asked, and according to PAL (PAL system Phase Alteration Line swings to system line by line) display control signal when
Sequence requirement generates the control signal such as corresponding row field signal and blanking signal.
Wherein PAL (PAL system Phase Alteration Line swings to system line by line) timing specific requirement is as follows:
Lines per picture is 625 rows, and scanning mode is interlacing scan；Pixel clock is 13.5 million；The row period is 64us, and row disappears
Hidden pulse width is 12us；Along time interval 10.5us behind the synchronous forward position to horizontal blanking of row；Horizontal blanking impulse front porch width is
1.5us+/-0.3us；Horizontal synchronizing pulse width 4.7us+/- 0.2us；Horizontal blanking impulse edge time 0.3us+/- 0.1us；Row
Lock-out pulse edge settling time 0.3us+/- 0.1us；2.5 row of leading Eq pulse sequence time duration；Field synchronization dyke rushes sequence
Arrange 2.5 row of duration, 2.5 row of post-equalizing pulse sequence time duration；Equalizing pulse width 2.35+/- 0.1us；Field synchronization tooth
Pulse width 27.3us；Serrated pulse width 4.7us+/- 0.2us between the punching of field synchronization dyke；The punching of field synchronization dyke and equalizing pulse
Edge settling time 0.2us+/- 0.1us.
Cameralink described in step 1 of the present invention (Data Transport Protocol) turns AXI4-Stream (bus protocol) mould
Block implementation method includes: that the module calls vivado (developing instrument that xilinx company provides) included IP (Intellectual
Property core IP core) verify existing, wherein FIFO (First input First Output First Input First Output)
Depth is set as 1024, and input data 8, output data 8, video format selects mono/sensor, and (xilinx company makes by oneself
The video format of justice).
A kind of DDR3 described in step 2 of the present invention (computer storage specification) memory write data control module implementation
It include: VDMA (the Video Direct Memory in module calling vivado (developing instrument that xilinx company provides)
The direct accessor of Access video) it verifies now, wherein data buffer storage is set as 3 frames of caching.
VDMA (the direct accessor of Video Direct Memory Access video) control method includes: PS (Process
System processing system) partially by way of register configuration, inform VDMA (Video Direct Memory Access view
Frequently direct accessor) each frame data storage first address and data location mode.PS (Process System processing system
System) control section register configuration method includes: by register S2MM_START_ADDRESS (high speed storing unit number)
The first address of each frame data storage is configured, 3 frames of caching need to configure three first address；Pass through register S2MM_FRMDLY_
STRIDE (high speed storing unit number) configuration makes data that DDR3 (a kind of computer storage specification) be written line by line.
(PAL system Phase Alteration Line the swings to system line by line) memory of PAL described in step 3 of the present invention reading
According to the VDMA that control module implementation includes: in module calling vivado (developing instrument that xilinx company provides)
(the direct accessor of Video Direct Memory Access video) is verified now, and wherein data buffer storage is set as 6 frames.
VDMA (the direct accessor of Video Direct Memory Access video) control method includes: PS (Process
System processing system) partially by way of register configuration, inform VDMA (Video Direct Memory Access view
Frequently direct accessor) each frame data first address and data reading mode that read.PS (Process System processing system
System) component register control method include: by register MM2S_START_ADDRESS (high speed storing unit number) configure
The first address that each frame data are read, 6 frames of caching need to configure 6 first address；Pass through register MM2S_FRMDLY_STRIDE
(high speed storing unit number) configuration is that the data interlacing in DDR3 (a kind of computer storage specification) is read.
Cameralink described in step 3 of the present invention (Data Transport Protocol) memory read data control module implementation
It include: VDMA (the Video Direct Memory in module calling vivado (developing instrument that xilinx company provides)
The direct accessor of Access video) it verifies now, wherein data buffer storage is set as 3 frames.
VDMA (the direct accessor of Video Direct Memory Access video) control method includes: PS (Process
System processing system) partially by way of register configuration, inform VDMA (Video Direct Memory Access view
Frequently direct accessor) each frame data first address and data reading mode that read.PS (Process System processing system
System) component register control method include: by register MM2S_START_ADDRESS (high speed storing unit number) configure
The first address that each frame data are read, 3 frames of caching need to configure 3 first address；Pass through register MM2S_FRMDLY_STRIDE
(high speed storing unit number) configuration is that the data in DDR3 (a kind of computer storage specification) are read line by line.
Cameralink described in step 4 of the present invention (Data Transport Protocol) output data cache module implementation method packet
It includes: FIFO (First input First Output First Input First Output) module and FIFO (First input First
Output First Input First Output) time-sequence control module.FIFO (First input First Output First Input First Output) mould
IP (the Intellectual Property core knowledge that block calls vivado (developing instrument that xilinx company provides) included
Property right core) core, FIFO (First input First Output First Input First Output) time-sequence control module, which generates, controls FIFO
Reset signal, read-write enable signal, the read-write clock of (First input First Output First Input First Output).Work as FIFO
(First input First Output First Input First Output) write enable signal is high level, cameralink (data transmission
Agreement) output data cache module with 100,000,000 clock by front end data be written FIFO (First input First Output
First Input First Output)；When FIFO (First input First Output First Input First Output) reading enable signal is high level
When, cameralink (Data Transport Protocol) output data cache module is with 30,000,000 clock by data from FIFO (First
Input First Output First Input First Output) in read；FIFO (First input First Output first in, first out team
Column) reset signal provides by system reset module, when reset signal is effective, empty FIFO (First input First
Output First Input First Output).
The IP that system reset module of the present invention calls vivado (developing instrument that xilinx company provides) included
(Intellectual Property core IP core) is verified now, is given PLL (Phase-Locked Loop phase-locked loop)
Module, cameralink (Data Transport Protocol) turn AXI4_Stream (bus protocol) module, a kind of DDR3 (computer storage
Specification) memory write data control module, PAL (PAL system Phase Alteration Line swings to system line by line) memory reading data
Control module, cameralink (Data Transport Protocol) memory read data control module, PAL (PAL system Phase
Alteration Line swings to system line by line) output data cache module, cameralink (Data Transport Protocol) output data be slow
Storing module provides reset signal.
PLL (Phase-Locked Loop phase-locked loop) module of the present invention calls vivado, and (xilinx company mentions
The developing instrument of confession) included IP (Intellectual Property core IP core) verifies existing, IP
(Intellectual Property core IP core) core is set as MMCM mode (customized one kind of xilinx company
Mode), 100,000,000 system clocks which is provided using the part PS (Process System processing system) as reference clock,
13.5 million, 30,000,000 clock is generated, when exporting respectively to PAL (PAL system Phase Alteration Line swings to system line by line)
Sequence generation module and cameralink (Data Transport Protocol) output timing generation module use.
Embodiment
(1) a kind of cameralink realized based on ZYNQ (chip series that match company of Sentos releases) platform of the present invention
(Data Transport Protocol) turns PAL (PAL system Phase Alteration Line swings to system line by line) display methods processed, and inputting is 30
Million cameralink (Data Transport Protocol) data flow exports PAL (the PAL system Phase Alteration for 13.5 million
Line swings to system line by line) data flow processed with 30,000,000 cameralink (Data Transport Protocol) data flow, realization approach as scheme
1: 30,000,000 camerlink (Data Transport Protocol) stream compression is changed to 100,000,000 AXI4-Stream (bus protocol) data
Stream is stored in a kind of DDR3 (computer storage by VDMA (the direct accessor of Video Direct Memory Access video)
Specification) it is cached, then divide two-way by data by VDMA (the direct accessor of Video Direct Memory Access video)
It is read from DDR3 (a kind of computer storage specification), the two paths of data difference read in DDR3 (a kind of computer storage specification)
Carry out data buffer storage, make 100,000,000 stream compression be changed to 13.5 million and 30,000,000 data flow, finally respectively progress PAL (PAL system
Phase Alteration Line swings to system line by line) system encodes and cameralink (Data Transport Protocol) encodes.
(2) the method for the present invention is described first:
The present invention is a kind of cameralink (number realized based on ZYNQ (chip series that match company of Sentos releases) platform
According to transport protocol) turn PAL (PAL system Phase Alteration Line swings to system line by line) display methods processed, implementing procedure is such as
Shown in Fig. 1,30,000,000 camerlink (Data Transport Protocol) stream compression is changed to 100,000,000 AXI4-Stream (bus association
View) data flow, a kind of DDR3 (calculating is stored in by VDMA (the direct accessor of Video Direct Memory Access video)
Machine stores specification) it is cached, then divide two-way by VDMA (the direct accessor of Video Direct Memory Access video)
Data are read from DDR3 (a kind of computer storage specification), two numbers read in DDR3 (a kind of computer storage specification)
According to data buffer storage is carried out respectively, make 100,000,000 stream compression be changed to 13.5 million and 30,000,000 data flow, finally carry out PAL respectively
(PAL system Phase Alteration Line swings to system line by line) system coding is encoded with cameralink (Data Transport Protocol).
(3) Fig. 2 is combined, the present invention is that one kind is realized based on ZYNQ (chip series that match company of Sentos releases) platform
Cameralink (Data Transport Protocol) turns PAL (PAL system Phase Alteration Line swings to system line by line) system display side
Method, specific implementation step are as follows:
Step 1, front-end image acquisition equipment output cameralink (Data Transport Protocol) data flow with 30,000,000 when
Clock write-in cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module.The module calls vivado
(developing instrument that xilinx company provides) included IP (Intellectual Property core IP core) is verified now,
The entitled Video In to AXI4-Stream (IP kernel of IP (Intellectual Property core IP core) core
Title).
Step 2, cameralink (Data Transport Protocol) turns AXI4-Stream (bus protocol) module for 30,000,000 data
Circulation changes the reading of 100,000,000 data flows into, and a kind of DDR3 (computer storage specification) memory write data control module, DDR3 is written
A kind of (computer storage specification) memory write data control module writes data into DDR3 (a kind of computer storage specification).DDR3
A kind of (computer storage specification) memory write data control module calls VDMA (Video Direct Memory Access video
Direct accessor) it verifies now, frame buffer is set as 3 frames of caching, and data are written to DDR3 (a kind of computer storage specification) line by line.
By PS (Process System processing system), partially by register S2MM_START_ADDRESS, (high speed storing component is compiled
Number) first address that each frame data are stored is configured, 3 frames of caching need to configure three first address；Pass through register S2MM_
FRMDLY_STRIDE (high speed storing unit number) configuration makes data that DDR3 (a kind of computer storage specification) be written line by line.
Step 3, the data in DDR3 (a kind of computer storage specification) read time-division two paths of data stream, are used for PAL all the way
(PAL system Phase Alteration Line swings to system line by line) system display, all the way for cameralink (data transmission association
View) display, wherein PAL (PAL system Phase Alteration Line swings to system line by line) memory read data control module with
100000000 speed reads data from DDR3 (a kind of computer storage specification), and is transferred to PAL (PAL system Phase
Alteration Line swings to system line by line) output data cache module；Cameralink (Data Transport Protocol) memory reads data
Control module reads data with 100,000,000 speed from DDR3 (a kind of computer storage specification), and outputs data to
Cameralink (Data Transport Protocol) data cache module.
PAL (PAL system Phase Alteration Line swings to system line by line) memory read data control module calls VDMA
(the direct accessor of Video Direct Memory Access video) is verified existing, and frame buffer is set as 6 frames, by data interlacing from
It is read in DDR3 (a kind of computer storage specification).
Register MM2S_START_ADDRESS (high speed storing unit number) is passed through by the part PS and configures each frame data
The first address of reading, 6 frames of caching need to configure 6 first address；Pass through (the high speed storing portion register MM2S_FRMDLY_STRIDE
Part number) configuration is that a kind of data interlacing in DDR3 (computer storage specification) is read.
Cameralink (Data Transport Protocol) memory read data control module calls VDMA (Video Direct
The direct accessor of Memory Access video) it verifies now, frame buffer is set as 3 frames, by data line by line from a kind of DDR3 (calculating
Machine store specification) in read.
Register MM2S_START_ADDRESS (high speed storing is partially passed through by PS (Process System processing system)
Unit number) first address that each frame data are read is configured, 3 frames of caching need to configure 3 first address；Pass through register MM2S_
FRMDLY_STRIDE (high speed storing unit number) configuration is that the data in DDR3 (a kind of computer storage specification) are read line by line
Out.
Step 4, PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module is used
13.5 million clocks write data into PAL (PAL system Phase Alteration Line swings to system line by line) output timing and generate mould
Block；Cameralink (Data Transport Protocol) output data cache module writes data into cameralink (number with 30,000,000 clocks
According to transport protocol) output timing generation module.
PAL (PAL system Phase Alteration Line swings to system line by line) output data cache module implementation method packet
It includes: FIFO (First input First Output First Input First Output) module and FIFO (First input First
Output First Input First Output) time-sequence control module.FIFO (First input First Output First Input First Output) mould
IP (the Intellectual Property core knowledge that block calls vivado (developing instrument that xilinx company provides) included
Property right core) core, FIFO (First input First Output First Input First Output) time-sequence control module, which generates, controls FIFO
Reset signal, read-write enable signal, the read-write clock of (First input First Output First Input First Output).Work as FIFO
(First input First Output First Input First Output) write enable signal is high level, PAL (PAL system Phase
Alteration Line swings to system line by line) with 100,000,000 clock FIFO is written in front end data by output data cache module
(First input First Output First Input First Output)；When (First input First Output first enters elder generation to FIFO
Dequeue) read enable signal be high level when, PAL (PAL system Phase Alteration Line swings to system line by line) output number
According to cache module with 13.5 million clock by data from FIFO (First input First Output First Input First Output)
It reads；FIFO (First input First Output First Input First Output) reset signal is provided by system reset module, when
When reset signal is effective, FIFO (First input First Output First Input First Output) is emptied.
Step 5, PAL (PAL system Phase Alteration Line swings to system line by line) output timing generation module will before
It holds the data flow sent to be packaged into meet PAL (PAL system Phase Alteration Line swings to system line by line) display timing and want
The data flow asked, and according to PAL (PAL system Phase Alteration Line swings to system line by line) display control signal when
Sequence requirement generates the control signal such as corresponding row field signal and blanking signal.
The present invention provides cameralink (the data transmission associations based on ZYNQ (chip series that match company of Sentos releases)
View) method that turns PAL system, there are many method and the approach for implementing the technical solution, and the above is only of the invention preferred
Embodiment, it is noted that for those skilled in the art, in the premise for not departing from the principle of the invention
Under, several improvements and modifications can also be made, these modifications and embellishments should also be considered as the scope of protection of the present invention.In the present embodiment
The available prior art of each component part not yet explicitly is realized.
Claims (10)
1. the method that the cameralink based on ZYNQ turns PAL system, which is characterized in that including following module: cameralink turns
AXI4-Stream module, system reset module, PLL module, memory write data control module, PAL memory read data and control mould
Block, cameralink memory read data control module, PAL output data cache module, cameralink output data cache mould
Block, PAL output timing generation module, cameralink output timing generation module, the specific implementation steps are as follows:
Step 1, the cameralink data flow of front-end image acquisition equipment output is turned with fixed frequency f1 write-in cameralink
AXI4-Stream module, system reset module provide for remaining module in addition to cameralink turns AXI4-Stream module
Reset signal；
Step 2, cameralink turns the AXI4- that the stream compression of fixed frequency f1 is changed into 100MHZ by AXI4-Stream module
Stream data flow is read, and is written in the memory of memory write data control module；
Step 3, the data in memory read time-division two paths of data stream, show all the way for PAL system, are used for cameralink all the way
Display, wherein PAL memory read data control module reads data with the speed of 100MHZ from memory, and is transferred to PAL output
Data cache module；Cameralink memory read data control module reads data with the speed of 100MHZ from memory, and defeated
Data give cameralink data cache module out；
Step 4, PAL output data cache module writes data into PAL output timing generation module with fixed frequency f2；
Cameralink output data cache module writes data into cameralink output timing generation module with fixed frequency f1,
The clock of middle fixed frequency f2 is provided by PLL module；
Step 5, the timing requirements that PAL output timing control module is shown according to PAL system generate row field signal and blanking signal；
According to the timing of the row field signal of generation and blanking signal adjustment front end data stream, the PAL system data flow of standard is formed.
2. the method according to claim 1, wherein the cameralink turns AXI4-Stream module calling
Vivado carries IP kernel and changes cameralink stream compression into AXI4-Stream data flow, and wherein FIFO depth is set as
1024, input data 8, output data 8.
3. according to the method described in claim 2, it is characterized in that, described memory write data control module module is called
VDMA core in vivado writes data into memory, and wherein data buffer storage is set as caching n frame.
4. according to the method described in claim 3, it is characterized in that, in the memory write data control module VDMA core control
Step includes: PS processing system part by way of register configuration, informs the first ground of the storage of each frame data of VDMA core
Location and data location mode.
5. according to the method described in claim 4, it is characterized in that, in the memory write data control module VDMA core deposit
Device configuration method includes: the first address that each frame data storage is configured by register S2MM_START_ADDRESS, caches n frame
Need to configure n first address；Make data that memory be written line by line by register S2MM_FRMDLY_STRIDE configuration and writes data control
In the memory of molding block.
6. according to the method described in claim 5, it is characterized in that, the PAL memory read data control module calls vivado
In VDMA verify now read memory in data, wherein data buffer storage is set as 2n.
7. according to the method described in claim 6, it is characterized in that, reading VDMA in the PAL memory read data control module
Nuclear control method includes: the part PS by way of register configuration, inform first address that each frame data of VDMA are read and
Data reading mode.
8. the method according to the description of claim 7 is characterized in that VDMA core in the PAL memory read data control module
PS component register control method includes: to configure the first ground that each frame data are read by register MM2S_START_ADDRESS
Location, caching 2n frame need to configure 2n first address；Pass through the data that register MM2S_FRMDLY_STRIDE configuration is in DDR3
It reads line by line.
9. according to the method described in claim 8, it is characterized in that, the cameralink memory read data control module is called
VDMA in vivado is verified now reads data with the speed of 100MHZ from memory, and outputs data to cameralink data
Cache module, wherein data buffer storage is set as n frame.
10. according to the method described in claim 9, it is characterized in that, in the cameralink memory read data control module
Reading nuclear control method include: the part PS by way of register configuration, inform the first address that each frame data of VDMA are read
And data reading mode；
The PS component register control method of VDMA core includes: to configure each frame number by register MM2S_START_ADDRESS
According to the first address of reading, caches n frame and need to configure n first address；It is by register MM2S_FRMDLY_STRIDE configuration
Data in DDR3 are read line by line；
The PAL output data cache module include the first fifo module and the first FIFO time-sequence control module, described first
The IP kernel that fifo module calls vivado included, the reset signal of the first FIFO time-sequence control module generation control FIFO,
Enable signal, read-write clock are read and write, when FIFO write enable signal is high level, PAL output data cache module is with 100MHZ's
FIFO is written in front end data by clock；When FIFO read enable signal be high level when, PAL output data cache module with
The clock of 13.5MHZ reads data from FIFO；FIFO reset signal is provided by system reset module, when reset signal is effective
When, empty FIFO；
The cameralink output data cache module includes the second fifo module and the 2nd FIFO time-sequence control module, institute
The IP kernel that the second fifo module calls vivado included is stated, the 2nd FIFO time-sequence control module generates the clearing of control FIFO
Signal, read-write enable signal, read-write clock；When FIFO write enable signal is high level, cameralink output data caches mould
With the clock of 100MHZ FIFO is written in front end data by block；When it is high level that FIFO, which reads enable signal, cameralink output
Data cache module is read data with the clock of 30MHZ from FIFO；FIFO reset signal is provided by system reset module, when
When reset signal is effective, FIFO is emptied；
The IP kernel that the system reset module calls vivado included, turns AXI4_Stream mould to PLL module, cameralink
Block, memory write data control module, PAL memory read data control module, cameralink memory read data control module, PAL
Output data cache module, cameralink output data cache module provide reset signal；
The PLL Module implementations are the IP kernel for calling vivado included, the 100MHZ system that PLL module is provided with the part PS
Clock generates the clock of 13.5MHZ, 30MHZ as reference clock, respectively to PAL output timing generation module with
Cameralink output timing generation module uses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811050894.XA CN109299030B (en) | 2018-09-10 | 2018-09-10 | The method that cameralink based on ZYNQ turns PAL system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811050894.XA CN109299030B (en) | 2018-09-10 | 2018-09-10 | The method that cameralink based on ZYNQ turns PAL system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109299030A true CN109299030A (en) | 2019-02-01 |
| CN109299030B CN109299030B (en) | 2019-06-11 |
Family
ID=65166714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811050894.XA Active CN109299030B (en) | 2018-09-10 | 2018-09-10 | The method that cameralink based on ZYNQ turns PAL system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109299030B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110824218A (en) * | 2019-11-18 | 2020-02-21 | 重庆邮电大学 | Digital storage oscilloscope system based on ZYNQ |
| CN110971856A (en) * | 2019-10-30 | 2020-04-07 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN112732603A (en) * | 2019-10-14 | 2021-04-30 | 广州飒特红外股份有限公司 | Multi-channel VDMA control method and application thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030056039A1 (en) * | 2000-10-17 | 2003-03-20 | Digital Interfaces Limited | Data buffer |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
| CN101902608A (en) * | 2009-06-30 | 2010-12-01 | 长春理工大学 | Adaptive conversion and display device of non-standard digital videos |
| CN204258949U (en) * | 2014-11-26 | 2015-04-08 | 成都盛军电子设备有限公司 | A kind of IMAQ playback board |
| CN104580895A (en) * | 2014-12-26 | 2015-04-29 | 北京航天控制仪器研究所 | Airborne imaging system with synchronous camera shooting and photographing capacity |
| CN105681783A (en) * | 2016-01-14 | 2016-06-15 | 西安电子科技大学 | Design method for audio and video data acquisition interface circuit |
| CN108200372A (en) * | 2017-12-06 | 2018-06-22 | 西南技术物理研究所 | Multi-standard video data stores and playing device |
-
2018
- 2018-09-10 CN CN201811050894.XA patent/CN109299030B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030056039A1 (en) * | 2000-10-17 | 2003-03-20 | Digital Interfaces Limited | Data buffer |
| CN101902608A (en) * | 2009-06-30 | 2010-12-01 | 长春理工大学 | Adaptive conversion and display device of non-standard digital videos |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
| CN204258949U (en) * | 2014-11-26 | 2015-04-08 | 成都盛军电子设备有限公司 | A kind of IMAQ playback board |
| CN104580895A (en) * | 2014-12-26 | 2015-04-29 | 北京航天控制仪器研究所 | Airborne imaging system with synchronous camera shooting and photographing capacity |
| CN105681783A (en) * | 2016-01-14 | 2016-06-15 | 西安电子科技大学 | Design method for audio and video data acquisition interface circuit |
| CN108200372A (en) * | 2017-12-06 | 2018-06-22 | 西南技术物理研究所 | Multi-standard video data stores and playing device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112732603A (en) * | 2019-10-14 | 2021-04-30 | 广州飒特红外股份有限公司 | Multi-channel VDMA control method and application thereof |
| CN110971856A (en) * | 2019-10-30 | 2020-04-07 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN110971856B (en) * | 2019-10-30 | 2022-01-04 | 中国航空工业集团公司洛阳电光设备研究所 | Device and method for generating HD-SDI video and analog video based on low-speed SRAM |
| CN110824218A (en) * | 2019-11-18 | 2020-02-21 | 重庆邮电大学 | Digital storage oscilloscope system based on ZYNQ |
| CN110824218B (en) * | 2019-11-18 | 2022-03-22 | 重庆邮电大学 | Digital storage oscilloscope system based on ZYNQ |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109299030B (en) | 2019-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109299030B (en) | The method that cameralink based on ZYNQ turns PAL system | |
| CN105915780B (en) | Image signal processor and apparatus including the same | |
| CN107249101A (en) | A kind of sample of high-resolution image and processing unit | |
| CN103647918B (en) | Video synchronization method and device | |
| CN101256763B (en) | Image display controlling device | |
| JP6062512B2 (en) | Imaging apparatus, information processing system, and image data transmission method | |
| US20210160418A1 (en) | Image data processing for digital overlap wide dynamic range sensors | |
| CN103595924B (en) | A kind of image fusion system based on Cameralink and method thereof | |
| JP2017069718A (en) | Imaging device, information processing device, display device, information processing system, image data transmission method, and image display method | |
| JPH0191576A (en) | Time expanded video signal generator | |
| CN104469241B (en) | A kind of device for realizing video frame rate conversion | |
| WO2024051674A1 (en) | Image processing circuit and electronic device | |
| CN108540689B (en) | Image signal processor, application processor and mobile device | |
| CN109587421A (en) | A kind of HD-SDI/3G-SDI transmitting-receiving and real-time picture-in-picture switch output processing method | |
| CN111428560B (en) | Video image processing method, device, electronic equipment and storage medium | |
| JP2012028997A (en) | Image processing device and camera | |
| CN102497514B (en) | Three-channel video forwarding equipment and forwarding method | |
| CN101257588A (en) | Image processing system and method for processing television divided pictures | |
| CN102881273B (en) | Embedded type image processing method aiming at asynchronous video | |
| CN109873954B (en) | Method for realizing color recovery of Bayer array based on FPGA | |
| CN115002304A (en) | Video image resolution self-adaptive conversion device | |
| CN107544124A (en) | Picture pick-up device and its control method and storage medium | |
| CN118018665A (en) | Multichannel image acquisition and processing system based on ZYNQ | |
| CN107959815A (en) | A kind of pal video encodes IP kernel | |
| Davutoglu et al. | Real-time Frame Buffer Implementation based on External Memory using FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |