CN109217880B - Linear type polar code decoder and design method thereof - Google Patents

Abstract

The invention discloses a linear polar code decoder and a design method thereof, which realize decoding by adopting fewer operation nodes and registers and have low hardware complexity. The invention not only can establish the quantitative relation between the hardware resource consumption and the time delay of the polar code decoder, but also provides the mapping relation from each step of calculation to the time axis, and provides guidance for the design of a control circuit and the hardware framework of the linear polar code decoder.

Description

Linear type polar code decoder and design method thereof

Technical Field

The invention relates to a decoding technology, in particular to a linear type polarization code decoder and a design method thereof.

Background

In 2009, e.arika first realized a coding scheme of capacity of a symmetric binary input discrete memoryless channel and a binary erasure channel. This new type of polarization Code encoding is called a polarization Code (Polar Code). The polar code is one of the 5G coding schemes because it can reach shannon limit and has the coding and decoding capability of practical linear complexity. Therefore, the research of the polar code decoder is regarded by the researchers.

For the decoding algorithm of the polar code, from the initial continuous elimination decoding algorithm to the list continuous elimination decoding algorithm to the adaptive list continuous elimination decoding algorithm, with the research, the error rate of the polar code decoding under the condition of short code is lower and lower, but the complexity of hardware is higher and higher, so how to reduce the hardware complexity of the polar code decoder is an urgent problem to be solved.

Disclosure of Invention

The purpose of the invention is as follows: the invention provides a linear polar code decoder and a design method thereof, aiming at the problems in the prior art.

The technical scheme is as follows: the decoder of the invention comprises 2ⁿA computing node PE and

one register P, m ═ log₂M, M is the length of the receiving sequence, and n is a non-negative integer; wherein:

register P_λ(a₁a₂...a_m-λ) For storing

The value of (a) is,

b-th representing a lambda-th layer₁b₂...b_λA of a channel₁a₂...a_m-λChannel transition probability of a branch, b₁b₂...b_λ、a₁a₂...a_m-λAre all binary numbers, b₁，...，b_λ∈{0，1}，a₁，a₂，...，a_m-λ∈{0，1}，λ＝1，...，m；

Operation node PE [ a ]₁a₂...a_n]For performing the following computational operations:

O[a₁a₂...a_n]

＝z(I[a₁a₂...a_n0]，I[a₁a₂...a_n1]，C[a₁a₂...a_n]，b_λ)

＝(1-b_λ)f(I[a₁a₂...a_n0]，I[a₁a₂...a_n1])

+b_λ·g(I[a₁a₂...a_n0]，I[a₁a₂...a_n1]，C[a₁a₂...a_n])

in the formula, a₁，a₂，...，a_n∈{0，1}，O[a₁a₂...a_n]Representing an operational node PE [ a ]₁a₂...a_n]Is output of (I a)₁a₂...a_n0]、I[a₁a₂...a_n1]Representing an operational node PE [ a ]₁a₂...a_n]Z () represents the operation function performed by the operation node PE, f (), g () represent b, respectively₁b₂...b_λThe function is calculated for the channel transition probabilities for even and odd numbers,

in order to be a feedback value, the feedback value,

denotes the a₁...a_m-λb₁...b_λ-1Estimate of 0 codewords, a₁...a_m-λb₁...b _λ-10 is a binary number;

the connection relationship between the register and the operation node is as follows:

when λ ∈ {1, 2., m-n-1}, there are:

and if n is m-1, then

When λ is m-n, there are:

when λ ∈ { m-n + 1., m-1, m }, there is:

wherein the number of 0 is n + λ -m-1, and if n is 0, then

In the formula, t₁，...，t_m-n-λValues of 0 and 1, t₁...t_m-n-λa₁...a_nIs a binary number and is used as a reference,

when a plurality of registers are connected to one input or one output of the operation node at the same time, a time control switch is added on the connecting line to control the input and the output of the operation node. .

Wherein, the time updating set of the time control switch is as follows:

when λ ∈ {1, 2., m-n-1}, there are:

B_λ，o(t₁...t_m-n-λa₁...a_n)＝{a+R_λ|a∈B_λ}，R_λ＝t₁...t_m-n-λ

and if n is m-1, then

When λ ∈ { m-n., m }, there are:

B_λ，o(a₁...a_m-λ)＝B_λ

B_λ-1，i(a₁a₂...a_m-λ0)＝B_λ-1，i(a₁a₂...a_m-λ1)＝B_λ，o(a₁...a_m-λ)

in the formula, the shape is as B_λ，o(. indicates) register P_λ(x) a time set connected to the output of the corresponding operational node and updated by the operational output, shaped as B_λ，i(. indicates) register P_λ(x) is connected with the input of the corresponding operation node and is used as a time set of the input of the operation node;

wherein:

d(λ)＝w(λ)+T_λ+1

w (λ) represents 2ⁿLinear type polar code decoder of node decodes length 2^m-λ-1The required delay.

The design method of the linear polarization code decoder comprises the following steps:

(1) calculating the number of the required minimum operation nodes according to the tolerable delay length;

(2) the decoder structure is designed according to the decoder of claim 1 based on the number of operational nodes and the known length of the received sequence.

Further, the step (1) specifically comprises:

obtaining the tolerable delay length T_hAnd calculating the number N of minimum operation nodes which satisfy the following inequality:

2^m+1+(m-n-2)·2^m-n≤T_h

wherein m is log₂M, M is the length of the receiving sequence, and n is log₂N。

Further, calculating

The time spent was:

in the formula, b₁′b₂′...b_λ′＝b₁b₂...b_λ-1，T(b₁b₂...b_λ) To be calculated from

To

The time that is consumed is the time required for,

b-th representing a lambda-th layer₁b₂...b_λThe channel transition probability of a channel is,

has the advantages that: compared with the prior art, the invention has the following remarkable advantages: the invention achieves the purpose of reducing the complexity of hardware within the expected delay allowable range, not only can establish the quantitative relation between the hardware resource consumption and the delay of the polar code decoder, but also provides the mapping relation of each step of calculation to a time axis, and provides guidance for the design of a control circuit and the hardware framework of the linear polar code decoder.

Drawings

FIG. 1 is a block diagram of a decoder architecture for an 8-bit-2 compute node using the present invention;

fig. 2 is a block diagram of a decoder for 8-bit-1 computational nodes using the present invention.

Detailed Description

First, analysis of technical problem

The essence of the conventional successive erasure decoding algorithm is that for a length of M-2^mReceive sequence of

To calculate the M-pair probabilities, i.e. to calculate the M-pairs

Wherein the content of the first and second substances,

for a decoded sequence that has been previously estimated,

indicating to the receiving sequence

The estimated value of each of the code words,

representing the channel transition probability when the input is 0,

representing the channel transition probability when the input is 1. The continuous elimination polar code decoding algorithm adopts a recursion mode to calculate the M pairs of probabilities, and the condition of recursion ending is that

By abbreviations

Denotes the second of the lambda layer

Channel transition probability of each channel. The continuous elimination polar code decoding algorithm calculates the M pairs of probabilities in a recursive mode, thereby further defining

As an intermediate state in the computation of M pairs of probabilities. The recurrence relation is shown as the following equation

When in use

When the number is even:

when in use

When the number is odd:

wherein β represents a branch. If it will be

Beta is represented by a binary number, i.e.

Then

Will be provided with

Is shown as

Second, the technical problem is solved

For the above analysis, the decoder may be constructed using registers and operation nodes in binary representation. The decoder comprises 2ⁿA computing node PE and

one register P, m ═ log₂M, M is the length of the receiving sequence, and n is a non-negative integer; wherein:

register P_λ(a₁a₂...a_m-λ) For storing

The value of (a) is,

b-th representing a lambda-th layer₁b₂...b_λA of a channel₁a₂...a_m-λChannel transition probability of a branch, b₁b₂...b_λ、a₁a₂...a_m-λAre all binary numbers, b₁，...，b_λ∈{0，1}，a₁，a₂，...，a_m-λ∈{0，1}，λ＝1，...，m；

Operation node PE [ a ]₁a₂...a_n]For performing the following computational operations:

O[a₁a₂...a_n]

＝z(I[a₁a₂...a_n0]，I[a₁a₂...a_n1]，C[a₁a₂...a_n]，b_λ)

＝(1-b_λ)f(I[a₁a₂...a_n0]，I[a₁a₂...a_n1])

+b_λ·g(I[a₁a₂...a_n0]，I[a₁a₂...a_n1]，C[a₁a₂...a_n])

in the formula, a₁，a₂，...，a_n∈{0，1}，O[a₁a₂...a_n]Representing an operational node PE [ a ]₁a₂...a_n]Is output of (I a)₁a₂...a_n0]、I[a₁a₂...a_n1]Representing an operational node PE [ a ]₁a₂...a_n]Z () represents the operation function performed by the operation node PE, f (), g () represent b, respectively₁b₂...b_λThe function is calculated for the channel transition probabilities for even and odd numbers,

in order to be a feedback value, the feedback value,

denotes the a₁...a_m-λb₁...b_λ-1Estimate of 0 codewords, a₁...a_m-λb₁...b _λ-10 is a binary number;

the connection relationship between the register and the operation node is as follows:

when λ ∈ {1, 2,. m-n-1}, there is:

and if n is m-1, then

When λ is m-n, there are:

when λ ∈ { m-n + 1., m-1, m }, there is:

wherein the number of 0 s, whose description is omitted, is n + λ -m-1, and if n is 0, then

In the formula, t₁，...，t_m-n-λValues of 0 and 1, t₁...t_m-n-λa₁...a_nIs a binary number and is used as a reference,

when a plurality of registers are connected to one input or one output of the operation node at the same time, a time control switch is added on the connecting line to control the input and the output of the operation node.

Wherein, the time updating set of the time control switch is as follows:

when λ ∈ {1, 2., m-n-1}, there are:

B_λ，o(t₁...t_m-n-λa₁...a_n)＝{a+R_λ|a∈B_λ}，R_λ＝t₁...t_m-n-λ

and if n is m-1, then

When λ ∈ { m-n., m }, there are:

B_λ，o(a₁...a_m-λ)＝B_λ

B_λ-1，i(a₁a₂...a_m-λ0)＝B_λ-1，i(a₁a₂...a_m-λ1)＝B_λ，o(a₁...a_m-λ)

in the formula, the shape is as B_λ，o(. indicates) register P_λ(x) a time set connected to the output of the corresponding operational node and updated by the operational output, shaped as B_λ，i(. indicates) register P_λ(x) is connected with the input of the corresponding operation node and is used as a time set of the input of the operation node;

wherein:

d(λ)＝w(λ)+T_λ+1

w (λ) represents 2ⁿLinear type polar code decoder of node decodes length 2^m-λ-1The required delay.

In designing a linear polar code decoder, the adopted design method comprises the following steps:

(1) calculating the number of the required minimum operation nodes according to the tolerable delay length; the method specifically comprises the following steps: obtaining the tolerable delay length T_hAnd calculating the minimum number N of operation nodes which satisfies the following inequality as 2ⁿ：

2^m+1+(m-n-2)·2^m-n≤T_h

(2) And designing a decoder structure according to the decoder according to the number of the operation nodes and the known receiving sequence length.

The following description will be given by taking the number of operation nodes as 2 and the length M of the received sequence as 8. In this case, n is 1 and m is 3, and the constructed decoder is as shown in fig. 1. Includes 2 operation nodes PE 0 and PE 1 and 15 registers P.

The connection relationship between the register and the operation node is as follows:

when λ is 1, there are:

when c is going to₁、a₁When the values are 0 and 1, respectively, the following are provided

When λ -m-n-2, there are:

when a is₁When the values are 0 and 1, respectively, the following are provided

When λ is 3, there are:

when a plurality of registers are simultaneously connected to one input or one output of the operation node, a time control switch is added on the connecting line to control the input and the output of the operation node.

The time update set of the time controlled switch is calculated as follows, when m is 3 and n is 1:

d(0)＝8，d(1)＝3，d(2)＝1，T₁＝2，T₂＝1，T₃＝1

then it can be calculated according to the formula:

B₁＝{1，1+d(0)}＝{1，9}

B₂＝{a+T₁，a+T₁+d(1)|a∈B₁}＝{3，6，11，14，}

B₃＝{a+T₂，a+T₂+d(2)|a∈B₂}＝{4，5，7，8，12，13，15，16}

then the set of strobe times for each register can be calculated:

B_1，o(00)＝B_1，o(01)＝{1，9}

B_1，o(10)＝B_1，o(11)＝{2，10}

B_2，o(0)＝B_2，o(1)＝{3，6，11，14}

B_3，o＝{4，5，7，8，12，13，15，16}

B_0，i(000)＝B_0，i(001)＝B_0，i(010)＝B_0，i(011)＝{1，9}

B_0，i(100)＝B_0，i(101)＝B_0，i(110)＝B_0，i(111)＝{2，10}

B_1，i(00)＝B_1，i(01)＝B_1，i(10)＝B_1，i(11)＝{3，6，11，14}

B_0，i(0)＝B_2，i(1)＝{4，5，7，8，12，13，15，16}

for example, B_0，i(000) The register P is represented by {1, 9}₀(000) And operation node PE [0] when t is 1 and t is 9]Is turned on as the operational node PE [0]]The input of (2) is operated.

In addition, when the operation node is 1, the decoder architecture is as shown in fig. 2, and the connection manner and the switching time set are as described above and are not described again.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (5)

1. A linear polar code decoder, comprising: comprises 2ⁿA computing node PE and

one register P, m ═ log₂M, M is the length of the receiving sequence, and n is a non-negative integer; wherein:

register P_λ(a₁a₂...a_m-λ) For storing

The value of (a) is,

b-th representing a lambda-th layer₁b₂...b_λA of a channel₁a₂...a_m-λChannel transition probability of a branch, b₁b₂...b_λ、a₁a₂...a_m-λAre all binary numbers, b₁，...，b_λ∈{0，1}，a₁，a₂，...，a_m-λ∈{0，1}，λ＝1，...，m；

Operation node PE [ a ]₁a₂...a_n]For performing the following computational operations:

in the formula, a₁，a₂，...，a_n∈{0，1}，O[a₁a₂...a_n]Representing an operational node PE [ a ]₁a₂...a_n]Is output of (I a)₁a₂...a_n0]、I[a₁a₂...a_n1]Representing an operational node PE [ a ]₁a₂...a_n]Z () represents the operation function performed by the operation node PE, f (), g () represent b, respectively₁b₂...b_λThe function is calculated for the channel transition probabilities for even and odd numbers,

in order to be a feedback value, the feedback value,

denotes the a₁...a_m-λb₁...b_λ-1Estimate of 0 codewords, a₁...a_m-λb₁...b_λ-10 is a binary number;

the connection relationship between the register and the operation node is as follows:

when λ ∈ {1, 2., m-n-1}, there are:

and if n is m-1, then

When λ is m-n, there are:

when λ ∈ { m-n + 1., m-1, m }, there is:

wherein the number of 0 is n + λ -m-1, and if n is 0, then

In the formula, t₁，...，t_m-n-λValues of 0 and 1, t₁...t_m-n-λa₁...a_nIs a binary number and is used as a reference,

when a plurality of registers are connected to one input or one output of the operation node at the same time, a time control switch is added on the connecting line to control the input and the output of the operation node.

2. The linear polar code decoder according to claim 1, wherein:

wherein, the time updating set of the time control switch is as follows:

when λ ∈ {1, 2., m-n-1}, there are:

B_λ，o(t₁...t_m-n-λa₁...a_n)＝{a+R_λ|a∈B_λ}，R_λ＝t₁...t_m-n-λ

and if n is m-1, then

When λ ∈ { m-n., m }, there are:

B_λ，o(a₁...a_m-λ)＝B_λ

B_λ-1，i(a₁a₂...a_m-λ0)＝B_λ-1，i(a₁a₂...a_m-λ1)＝B_λ，o(a₁...a_m-λ)

in the formula, the shape is as B_λ，o(. indicates) register P_λ(x) a time set connected to the output of the corresponding operational node and updated by the operational output, shaped as B_λ，i(. indicates) register P_λ(x) is connected with the input of the corresponding operation node and is used as a time set of the input of the operation node;

wherein:

d(λ)＝w(λ)+T_λ+1

w (λ) represents 2ⁿLinear type polar code decoder of node decodes length 2^m-λ-1The required delay.

3. A method for designing a linear polar code decoder, the method comprising:

(1) calculating the number of the required minimum operation nodes according to the tolerable delay length;

(2) the decoder structure is designed according to the decoder of claim 1 based on the number of operational nodes and the known length of the received sequence.

4. The linear polar code decoder design method according to claim 3, wherein: the step (1) specifically comprises the following steps:

obtaining the tolerable delay length T_hAnd calculating the number N of minimum operation nodes which satisfy the following inequality:

2^m+1+(m-n-2)·2^m-n≤T_h

wherein m is log₂M, M is the length of the receiving sequence, and n is log₂N。

5. The linear polar code decoder design method according to claim 3, wherein: computing

The time spent was:

in the formula, b₁′b₂′...b_λ′＝b₁b₂...b_λ-1，T(b₁b₂...b_λ) To be calculated from

To

The time that is consumed is the time required for,

b-th representing a lambda-th layer₁b₂...b_λThe channel transition probability of a channel is,

Images