CN109213424A - Concurrent I/O command without lock processing method - Google Patents
Concurrent I/O command without lock processing method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/522—Barrier synchronisation
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Abstract
Present applicant proposes concurrent I/O commands without lock processing method.The concurrent I/O command of the application includes: to receive the first I/O command without lock processing method；Judge whether the first I/O command conflicts with any I/O command in ordered set；Do not conflict in response to the first I/O command with any I/O command in ordered set, the first I/O command is inserted into ordered set, handles the first I/O command；It is had been processed into response to the first I/O command, the first I/O command is taken out from ordered set.
Description
Technical field
This application involves solid storage devices, and in particular to accesses in storage equipment the concurrent resource of multiple I/O commands
Use of the middle elimination to lock.
Background technique
Fig. 1 is the block diagram of the solid storage device of the prior art, as shown in Figure 1, storage equipment 102 is coupled with host,
For providing storage capacity for host.Host can be coupled in several ways between storage equipment 102, and coupled modes include
But it is not limited by such as SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, Ethernet, optical-fibre channel, wireless
Communication network etc. connects host and storage equipment 102.Host, which can be, same through the above way to store what equipment communicate
Information processing equipment, for example, personal computer, tablet computer, server, portable computer, the network switch, router,
Cellular phone, personal digital assistant etc..It is (non-easy including interface 103, control unit 104, one or more NVM to store equipment 102
Lose memory, Non-Volatile Memory) chip 105 and optionally firmware memory 110.Interface 103 can adapt to lead to
Cross the mode such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel and host exchanging data.Control unit
104, for controlling the transmission of the data between interface 103, NVM chip 105 and firmware memory 110, are also used to storage tube
Reason, host logical address to flash memory physical address map, erasure balance, bad block management etc..Can by software, hardware, firmware or
The various ways of a combination thereof realize control unit 104.Control unit 104 can be FPGA (Field-programmable gate
Array, field programmable gate array), ASIC (Application Specific Integrated Circuit, application specific
Integrated circuit) or a combination thereof form.Control unit 104 also may include processor or controller.Control unit 104 exists
From 110 loading firmware of firmware memory when operation.Firmware memory 110 can be NOR flash memory, ROM, EEPROM, be also possible to
The part of NVM chip 105.Nand flash memory, phase transition storage, FeRAM, MRAM etc. are common NVM.
Memory target (Target) is that the shared chip in nand flash memory encapsulation enables (CE, Chip Enable) signal
One or more logic units (LUN, Logic UNit).It may include one or more tube cores (Die) in nand flash memory encapsulation.
Typically, logic unit corresponds to single tube core.Logic unit may include multiple planes (Plane).It is more in logic unit
A plane can be with parallel access, and multiple logic units in nand flash memory chip can execute order and report independently of one another
State.Can be from http://www.micron.com/~/media/Documents/Products/Other%20Docume
" the Open NAND Flash Interface Specification (Revision that nts/ONFI3_0Gold.ashx is obtained
3.0) in ", provide about target (target), logic unit, LUN, plane (Plane) meaning, be the prior art
A part.
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block includes multiple pages.Block packet
Containing multiple pages.Page (referred to as Physical Page) on storage medium has fixed size, such as 17664 bytes.Physical Page can also be with
With other sizes.It may include multiple data segments in Physical Page, data segment has specified size, such as 4096 or 4416
Byte.
In solid storage device, safeguarded using FTL (Flash Translation Layer, flash translation layer (FTL)) from
Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address for accessing the physical memory cell of solid storage device.In existing skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL table.FTL table is that solid-state is deposited
Store up the important metadata in equipment.The data item of usual FTL table has recorded the ground in solid storage device as unit of data page
Location mapping relations.
FTL table includes multiple FTL table clauses (or list item).In one embodiment, it is had recorded in each FTL table clause
The corresponding relationship of one logical page address and a Physical Page.In another example, it is had recorded in each FTL table clause continuous
Multiple logical page addresses and continuous multiple Physical Page corresponding relationship.In yet another embodiment, in each FTL table clause
Have recorded the corresponding relationship of logical block address and physical block address.In still another embodiment, logical block is recorded in FTL table
The mapping relations and/or logical page address of address and physical block address and the mapping relations of physical page address.
I/O command from host includes such as read command and write order.When handling the read command from host, solid-state
The logical address carried in storage equipment utilization read command obtains corresponding physical address from FTL table, and according to physical address
Read request is issued to NVM chip, and receives the data that NVM chip is exported in response to read request.Life is write from host in processing
When enabling, solid storage device is write order allocated physical address, and the logical address of write order and the object of distribution are recorded in FTL table
The corresponding relationship of address is managed, and issues write request to NVM chip according to the physical address of distribution.
In NVMe specification (http://nvmexpress.org/wp-content/uploads/NVM_Express_1_2_
1_Gold_20160603.pdf) in define atomic operation (Atomic Operation).Atomic operation includes atomic write life
It enables.To execute atom write order, solid storage device ensures to refer to the data shown in atom write order or all be written to solid-state
It in storage equipment or is all not written in solid storage device, without having other Proper Motions.When existing simultaneously to identical
Or two or more atom write orders of the identical address in part write-in data are when existing simultaneously, the execution of these atom write orders
The result is that as these atomic write orders serially execute.
For example, referring to table 1, data are written to logical address (LBA) 0-3 in atom write order A, and atom write order B is to logic
Address (LBA) 1-4 write-in data (indicate the data being written by atom write order A with " A " in table 1, and are indicated by " B " by atom
The data of write order B write-in).2nd row of table 1 and the 3rd row show order A and order the correct implementing result of B.Referring to table 1,
It is the data that write order A is written that a kind of possible result (as shown in the 2nd row of table 1), which is LBA 0-LBA 3, and LBA 4 is to write
The data that order B is written, in other words, write order B first comes into force, and has updated to atomicity LBA 1-LBA 4, next writes life
Enable A come into force, but atomicity have updated LBA 0-LBA 3.Alternatively possible result (as shown in the 3rd row of table 1) is that LBA 0 is
The data that write order A is written, and LBA 1-LBA 4 is the data that write order B is written, in other words, write order Mr. A
Effect, have updated to atomicity LBA 0-LBA 3, following write order B comes into force, but atomicity have updated LBA 1-LBA 4.It removes
Two kinds above-mentioned standardize requirement to atom write order as a result, other any results do not comply with NVMe.
Table 1
| LBA0 | LBA1 | LBA 2 | LBA 3 | LBA 4 | LBA 5 | LBA 6 | |
| Effective result | A | A | A | A | B | ||
| Effective result | A | B | B | B | B | ||
| Null result | A | A | B | B | B |
Summary of the invention
In solid storage device, while multiple I/O commands are handled, almost each I/O command requires access FTL table.Make
Elimination access conflict can satisfy the atomicity requirement to I/O command when being made as the FTL list item of I/O command access with lock machine.However,
Access lock increases the occupancy to bandwidth of memory and CPU computing capability, and is unfavorable for promoting the processing energy of solid storage device
Power and performance-power dissipation ratio.
According to an embodiment of the present application, the concurrent processing that can be realized multiple I/O commands meets atomicity requirement, eliminates
The use of lock improves the process performance of solid storage device.
According to a first aspect of the present application, it provides according to the first concurrent I/O command of the application first aspect at without lock
Reason method, comprising: receive the first I/O command；Judge whether the first I/O command conflicts with any I/O command in ordered set；It rings
It should not conflict in the first I/O command with any I/O command in ordered set, the first I/O command is inserted into ordered set,
Handle the first I/O command；It is had been processed into response to the first I/O command, the first I/O command is taken out from ordered set.
The concurrent I/O command of first according to a first aspect of the present application without lock processing method, provide according to the application the
The concurrent I/O command of the second of one side without lock processing method, further includes: in response to the first I/O command in ordered set appoint
First I/O command is placed in waiting set by what I/O command conflict.
The concurrent I/O command of second according to a first aspect of the present application without lock processing method, provide according to the application the
The concurrent I/O command of the third of one side without lock processing method, further includes: from wait set in obtain the first I/O command, in response to
First I/O command disappears with any I/O command conflict in ordered set, and the first I/O command is inserted into ordered set, and
Handle the first I/O command.
First according to a first aspect of the present application, without one of lock processing method, provides root to the concurrent I/O command of third
According to the application first aspect the 4th concurrent I/O command without lock processing method, the element in ordered set is I/O command.
The concurrent I/O command of first to fourth according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 5th concurrent I/O command without lock processing method, the I/O command in ordered set is the IO in processing
Order.
The first to the 5th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 6th concurrent I/O command without lock processing method, the I/O command in ordered set is visited according to I/O command
The logical address sequence asked.
The first to the 6th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 7th concurrent I/O command without lock processing method, ordered set according to I/O command access logically
The initial address of location or end address sequence.
The first to the 7th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 8th concurrent I/O command without lock processing method, the I/O command access in ordered set is logically
The range size of location is same or different.
The first to the 8th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 9th concurrent I/O command without lock processing method, ordered set be queue, chained list, skip list, two
One of fork tree is a variety of.
The first to the 9th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the tenth concurrent I/O command without lock processing method, ordered set is stored in the on-chip memory of SoC
In.
The first to the tenth concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide root
According to the application first aspect the 11st concurrent I/O command without lock processing method, each I/O command of ordered set is logically
There is no overlapping for location range.
The first to the 11st concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 12nd concurrent I/O command of the application first aspect without lock processing method, if the first I/O command is the same as in ordered set
The ranges of logical addresses of any I/O command, which exists, to be overlapped, then the first I/O command has conflict with the I/O command in ordered set.
The first to the 12nd concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 13rd concurrent I/O command of the application first aspect without lock processing method, in response to the same ordered set of the first I/O command
In the second I/O command conflict, the first I/O command is placed in in the associated waiting subset of the second I/O command.
The 13rd concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to the application
14th concurrent I/O command of first aspect without lock processing method, the second I/O command has been processed into and moves from ordered set
It removes, third I/O command is obtained from the same associated waiting subset of second I/O command, and attempt for third I/O command to be added and sort
Set.
The 14th concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to the application
15th concurrent I/O command of first aspect without lock processing method, if third I/O command is the same as any I/O command in ordered set
Do not conflict, by third I/O command insertion sort set.
The 14th concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to the application
16th concurrent I/O command of first aspect without lock processing method, if third I/O command is the same as the 4th I/O command in ordered set
Third I/O command is put into in the associated waiting subset of the 4th I/O command by conflict.
The first to the 16th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 17th concurrent I/O command of the application first aspect without lock processing method, if the first I/O command is read command, directly
First I/O command is handled, without the first I/O command is added to ordered set.
The first to the 17th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 18th concurrent I/O command of the application first aspect without lock processing method, if the first I/O command is write order, if the
One I/O command does not conflict with any I/O command in ordered set, the first I/O command is just added to ordered set, and to
One I/O command is handled.
The first to the 18th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 19th concurrent I/O command of the application first aspect without lock processing method, if the first I/O command is write order, if the
First I/O command is placed in waiting set by one I/O command with the third I/O command conflict in ordered set.
The 19th concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to the application
20th concurrent I/O command of first aspect without lock processing method, it is associated that the first I/O command is placed in same third I/O command
It waits in subset.
The first to the 20th concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 21st concurrent I/O command of the application first aspect without processing method is locked, the I/O command in ordered set is concurrent
Processing.
The first to the 21st concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 22nd concurrent I/O command of the application first aspect without lock processing method, received I/O command is to be deposited by access
The order of storage equipment splits obtained subcommand.
The first to the 22nd concurrent I/O command according to a first aspect of the present application without lock one of processing method, provide
According to the 23rd concurrent I/O command of the application first aspect without lock processing method, the first I/O command of processing includes foundation
The logical address access FTL table of first I/O command access obtains corresponding physical address, accesses the physical address to respond the
One I/O command.
The 23rd concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to this Shen
Please first aspect the 24th concurrent I/O command without lock processing method, when accessing FTL table, without to FTL table or FTL table
List item locks.
The the 23rd or the 24th concurrent I/O command according to a first aspect of the present application without lock processing method, provide
According to the 25th concurrent I/O command of the application first aspect without lock processing method, further includes: if presently written position
The first physical address is lagged behind, suspends the processing to the first read request, until presently written position is ahead of the first physical address.
The the 23rd or the 24th concurrent I/O command according to a first aspect of the present application without lock processing method, provide
According to the method without lock processing of the 26th concurrent I/O command of the application first aspect, further includes: if include the object
Manage address physical block or bulk be in has been written into state, and if presently written position be ahead of the physical address, from institute
It states physical address and reads data to respond first I/O command.
The 26th concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to this Shen
Please first aspect the 27th concurrent I/O command without lock processing method, further includes: if presently written position lags behind first
Physical address suspends the processing to the first I/O command, until presently written position is ahead of the first physical address.
The the 23rd or the 24th concurrent I/O command according to a first aspect of the present application without lock processing method, provide
According to the 28th concurrent I/O command of the application first aspect without lock processing method, further includes: if from it is described physically
Physical Page where the result that data are read in location indicates the physical address is in erase status, and includes the physical address
Physical block or bulk be in and have been written into state, if presently written position lags behind the physical address, suspend to described first
The processing of I/O command, until presently written position is ahead of the physical address.
The 28th concurrent I/O command according to a first aspect of the present application without lock processing method, provide according to this Shen
Please first aspect the 29th concurrent I/O command without lock processing method, further includes: if from the physical address read data
Result indicate the physical address where Physical Page be in erase status, and the physical block comprising the physical address or
Bulk is in erased state, and the logical address access FTL table according to the access of the first I/O command is to obtain the second physical address；With
And data are read from the second physical address.
According to a second aspect of the present application, the first concurrent I/O command according to the application second aspect is provided without lock processing
System, comprising: receiving module, for receiving the first I/O command；Judgment module, for judging the first I/O command in ordered set
Any I/O command whether conflict；Processing module, in response to the first I/O command with any I/O command in ordered set all
Do not conflict, the first I/O command is inserted into ordered set, handles the first I/O command；Module is taken out, in response to the first IO
Order has been processed into, and the first I/O command is taken out from ordered set.
According to the third aspect of the application, the first solid storage device according to the application third aspect is provided, including
Control unit, NVM chip and memory, control unit are respectively coupled to NVM chip and memory, and the control unit executes root
According to one of the method without lock processing of the first to the 29th concurrent I/O command of the first aspect of the application.
According to the fourth aspect of the application, the storage for storing program according to the first of the fourth aspect of the application is provided
Medium is loaded into processor operation in response to described program, and described program executes the processor according to the first of the application
One of the method without lock processing of first to the 29th concurrent I/O command of aspect.
According to the 5th of the application aspect, provide according to the first concurrent I/O command of the 5th aspect of the application at without lock
Reason method, comprising: in response to receiving the first write order, judge whether the first write order rushes with any write order in ordered set
It is prominent；Do not conflict in response to the first write order with any write order in ordered set, the first write order is inserted into sequence collection
In conjunction, the first write order is handled；If logical address block belonging to the logical address of the first write order access is the same as in processing
Logical address block belonging to the logical address of read command access is identical or overlaps mutually, and makes the update meter in the read command metadata
Number is incremented by；It is had been processed into response to the first write order, the first write order is taken out from ordered set.
According to the first concurrent I/O command of the 5th of the application aspect without lock processing method, provide according to the application the
Five aspect the second concurrent I/O command without lock processing method, further includes: in response to the first write order in ordered set appoint
First write order is placed in waiting set by one write order conflict.
According to the concurrent I/O command of the first or second of the 5th of the application the aspect without lock processing method, provide according to this
Apply the 5th aspect the concurrent I/O command of third without lock processing method, further includes: in response to receiving the first read command, if first
Read command does not conflict with any write order in ordered set, handles the first read command.
According to the first of the 5th of the application the aspect to the concurrent I/O command of third without one of lock processing method, root is provided
According to the 4th concurrent I/O command in terms of the application the 5th without lock processing method, further includes: if the same ordered set of the first read command
In any write order conflict, by the first read command be placed in waiting set in.
According to the second of the 5th of the application aspect or the 4th concurrent I/O command without lock processing method, provide according to this
Apply the 5th concurrent I/O command of the 5th aspect without lock processing method, the waiting set associative writes in second to lead to a conflict
Order.
According to the first to the 5th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, root is provided
According to the 6th concurrent I/O command in terms of the application the 5th without lock processing method, further includes: in response to waiting first in set
I/O command disappears with any write order conflict in ordered set, handles the first I/O command, until the processing of the first I/O command is completed.
According to the 5th concurrent I/O command of the 5th of the application aspect without lock processing method, provide according to the application the
Five aspect the 7th concurrent I/O command without lock processing method, further includes: had been processed into response to second write order, will
Second write order takes out from ordered set, handles the I/O command waited in set, until the IO waited in set
Command process is completed.
According to the first to the 7th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, root is provided
According to the 8th concurrent I/O command in terms of the application the 5th without lock processing method, further includes: in response to obtaining institute from NVM chip
The data that the second read command in the read command in processing is accessed are stated, if the institute recorded in the metadata of second read command
The more New count for stating logical address block belonging to the logical address of the second read command access is greater than threshold value, handles described second again
Read command.
According to the 8th concurrent I/O command of the 5th of the application aspect without lock processing method, provide according to the application the
Five aspect the 9th concurrent I/O command without lock processing method, in response to handling second read command again, if described second
There is conflict with any write order in ordered set in read command, second read command is placed in the second waiting set, institute
The second waiting set associative is stated in the third write order to lead to a conflict.
According to the 8th or the 9th concurrent I/O command of the 5th of the application the aspect without lock processing method, provide according to this
Apply the 5th aspect the tenth concurrent I/O command without lock processing method, if second read command is the same as any in ordered set
Conflict is all not present in write order, and the second physical address for corresponding to the logical address of second read command is obtained from FTL table,
NVM chip is accessed according to the second physical address.
According to the 8th or the 9th concurrent I/O command of the 5th of the application the aspect without lock processing method, provide according to this
Apply the 5th aspect the 11st concurrent I/O command without lock processing method, in response to handling second read command again, if
Conflict is all not present with any write order in ordered set in second read command, obtains from FTL table and corresponds to described the
Second physical address of the logical address of two read commands, if being recorded in metadata of second physical address with second read command
Physical address it is different, access NVM chip according to the second physical address.
According to the 11st concurrent I/O command of the 5th of the application the aspect without lock processing method, provide according to the application
5th aspect the 12nd concurrent I/O command without lock processing method, if the second physical address is the same as first number of second read command
Physical address according to middle record is identical, and the data that the second read command obtained from NVM chip is accessed are supplied to host.
According to the 11st concurrent I/O command of the 5th of the application the aspect without lock processing method, provide according to the application
5th aspect the 13rd concurrent I/O command without lock processing method, further includes: remember in the metadata of second read command
Record second physical address.
According to the 8th to the 13rd concurrent I/O command of the 5th of the application the aspect without one of lock processing method, provide
According to the 14th concurrent I/O command of the 5th aspect of the application without lock processing method, further includes: if second read command
The more New count of logical address block belonging to the logical address of second read command access recorded in metadata is no more than threshold
The data that the second read command obtained from NVM chip is accessed are supplied to host by value.
According to the first to the 14th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, provide
According to the 15th concurrent I/O command of the aspect of the application the 5th without lock processing method, write order in ordered set is according to writing life
Enable the logical address sequence of access.
According to the first to the 15th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, provide
According to the 16th concurrent I/O command of the 5th aspect of the application without lock processing method, the logic of each write order of ordered set
There is no overlapping for address range.
According to the first to the 16th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, provide
According to the 17th concurrent I/O command of the 5th aspect of the application without lock processing method, if I/O command is the same as any in ordered set
The ranges of logical addresses of write order, which exists, to be overlapped, then I/O command has conflict with the write order in ordered set.
According to the first to the 17th concurrent I/O command of the 5th of the application the aspect without one of lock processing method, provide
According to the 18th concurrent I/O command of the aspect of the application the 5th without lock processing method, when accessing FTL table, without to FTL table or
The list item of FTL table locks.
According to the 6th of the application the aspect, the first concurrent I/O command according to the 6th aspect of the application is provided without lock processing
System, comprising: conflict set recognition module, for judging the first write order in ordered set in response to receiving the first write order
Whether any write order conflicts；Ordered set is inserted into module, for writing in response to the first write order with any in ordered set
Order does not conflict, and the first write order is inserted into ordered set, handles the first write order；Counting module is updated, if for
Logical address institute of the logical address block belonging to the logical address of the first write order access with the read command access in processing
The logical address block of category is identical or overlaps mutually, and is incremented by the more New count in the read command metadata；Ordered set deletes mould
Block takes out the first write order for having been processed into response to the first write order from ordered set.
According to the 7th of the application the aspect, the first solid storage device according to the 7th aspect of the application is provided, including
Control unit, NVM chip and memory, control unit are respectively coupled to NVM chip and memory, and the control unit executes root
According to the application the 5th aspect first to one of 18th concurrent I/O command without lock processing method.
According to the eighth aspect of the application, the storage for storing program according to the first of the eighth aspect of the application is provided
Medium is loaded into processor operation in response to described program, and described program executes the processor according to the 5th of the application
First to one of 18th concurrent I/O command of aspect without lock processing method.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application can also be obtained according to these attached drawings other attached for those skilled in the art
Figure.
Fig. 1 is the block diagram of the solid storage device of the prior art；
Fig. 2 is the block diagram formed according to the inside of the control unit of Fig. 1 of the embodiment of the present application；
Fig. 3 is the flow chart after the completion of the I/O command processing in the ordered set according to the embodiment of the present application；
Fig. 4 is the flow chart according to the processing I/O command of the embodiment of the present application；
Fig. 5 is the schematic diagram according to the concurrent processing I/O command of the embodiment of the present application；
Fig. 6 is the physical block state table according to the embodiment of the present application；
Fig. 7 is the schematic diagram according to the bulk of the embodiment of the present application；
Fig. 8 is the writing position table according to the embodiment of the present application；And
Fig. 9 is according to the extension flow chart for handling read command in the application still another embodiment.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, those skilled in the art's every other embodiment obtained without making creative work, all
Belong to the scope of protection of the invention.
Embodiment one
Fig. 2 is the block diagram formed according to the inside of the control unit of Fig. 1 of the embodiment of the present application.As shown in Fig. 2, control unit
Part 104 includes host interface 210, distributor 230, multiple CPU for handling I/O command (for example, CPU 240 and CPU
250), for accessing the Media Interface Connector 220 of NVM chip 105.
Host interface 210 is used for host exchange command and data.In one example, host passes through with storage equipment
NVMe/PCIe protocol communication, host interface 210 handle PCIe protocol data packet, extract NVMe protocol command, and return to host
Return the processing result of NVMe protocol command.
Distributor 230 is coupled to host interface 210, and receiving host is sent to the I/O command of storage equipment, and by I/O command
Distribute to one of multiple CPU for handling I/O command.Distributor 230 can be realized by CPU or specialized hardware.Control unit 104
It is additionally coupled to external memory (for example, DRAM) 110.The segment space of memory 110 be used to store FTL table (for example, FTL
Table 260 and FTL table 270).Optionally, the complete logical address space that solid storage device provides is divided into multiple portions, each
Part is managed by one of FTL table (FTL table 260 or FTL table 270).
Optionally, the CPU of FTL table and processing I/O command is corresponded.For example, FTL table 260 is only accessed by CPU 40, and
FTL table 270 is only accessed by CPU 250.I/O command is sent to management by the logical address that distributor 230 is accessed according to I/O command
The CPU of the FTL table of the logical address accessed comprising I/O command.
Still optionally, the either of which of CPU 240 and CPU 250 may have access to complete FTL table.
It should be understood that can provide the CPU processing I/O command of one or more quantity.
For write order, under the instruction of CPU, the data to be written are transferred to NVM from host by host interface 210
Chip 105.CPU is the physical address that write order distribution is used for NVM chip 105, by the object of the logical address of write order and distribution
Reason address constitutes FTL list item and is recorded in FTL table.
For read command, under the instruction of CPU, the logical address access FTL table according to read command obtains same logical address
Corresponding physical address, and data are read from NVM chip 105 according to physical address, and data are transmitted by host interface 210
To host.
CPU to the processing of each I/O command need to occupy certain time and using solid storage device part resource (for example,
Storing data and/or the caching for recording I/O command context).To the portion link of the processing of I/O command (for example, access FTL table,
NVM chip is accessed, with host transmission data etc.) it is executed using asynchronous system.During asynchronous process I/O command, CPU handles it
His I/O command, to also concomitantly handle multiple I/O commands even if single CPU.
The I/O command for handling and not yet handling completion will be had begun in solid storage device, the IO life referred to as in processing
It enables.And need to avoid the I/O command in multiple processing to access conflict caused by identical logical address.
According to an embodiment of the present application, the lock for FTL list item is eliminated, and it is more to manage to be to provide ordered set
A concurrent I/O command.Table 2 illustrates the example of ordered set.Element in ordered set is I/O command, in table 2, in " IO
Order " column, represent I/O command with the identifier (C0, C5, C9 or C2) of I/O command.Element (I/O command) in ordered set is pressed
The logical address sequence of I/O command access.In the example of table 2, by the initial address or end of the logical address of I/O command access
Address sort.The range size of the logical address of each I/O command access may be the same or different.
The I/O command recorded in ordered set is the I/O command in processing.
In response to receiving I/O command from distributor, I/O command is added in ordered set by CPU.It can be by queue, chained list, jump
The plurality of data structures such as jump table (Skip List), binary tree realize that ordered set, ordered set size are smaller (for example, set member
Plain maximum quantity is the I/O command number that solid storage device is performed simultaneously), the local for being stored in CPU 240 or CPU 250 is deposited
In reservoir.CPU 240 and CPU 250 safeguard respective ordered set.
Appropriate position to be found in ordered set for I/O command, to guarantee to sort for I/O command insertion sort set
Element in set is sequence.The logical address of each I/O command of ordered set cannot overlap (in other words, any two
The part of any overlapping is not present in the ranges of logical addresses of I/O command access).If being inserted into I/O command with the IO in ordered set
The ranges of logical addresses of order occurs overlapping, it is believed that conflicts.When conflicting, the I/O command being inserted into cannot be added
Into ordered set.But the I/O command that conflict will be present is placed in and waits in I/O command subset.
For example, accessing ranges of logical addresses 100-200 by the I/O command of C0 instruction referring to table 2, and ordered by the IO of C1 instruction
Enable access ranges of logical addresses 120-130.Since I/O command C1 has conflict with the I/O command C0 in ordered set, by I/O command
C1 is placed in the associated waiting I/O command subset of same I/O command C0.As another example, I/O command C3 accesses logical address
Range 180-183 conflicts with I/O command C0 phase, and I/O command C3 is also placed in the associated waiting I/O command subset of same I/O command C0
In.
According to an embodiment of the present application, only the I/O command in ordered set is handled, it is sub to I/O command is waited
The I/O command of concentration is without processing.It is thus processing I/O command, needs that first I/O command is added in ordered set.Due to sequence
The ranges of logical addresses of each I/O command access in set does not overlap each other, ensure that the I/O command in handling ordered set
When, the FTL list item of access is all different FTL list item, so that FTL list item will not become facing for multiple I/O commands of concurrent processing
Boundary's resource, to eliminate conflict.And the I/O command of conflict can be caused all to be added because the ranges of logical addresses of access is overlapping
Into waiting I/O command subset.It is handled again after conflict resolving.
Table 2
Fig. 3 is the flow chart after the completion of the I/O command processing in the ordered set according to the embodiment of the present application.Such as Fig. 3 institute
Show, have been processed into (310) in response to I/O command, the I/O command having been processed is taken out (320) by CPU from ordered set.
And optionally, adjust ordered set, make wherein element still keep sorting.Further, CPU judges with by from ordered set
The associated waiting I/O command subset of the I/O command of middle deletion whether non-empty (330).If it does not exist with being taken from ordered set
The associated waiting I/O command subset of I/O command out, the new I/O command (340) to be received such as CPU.
If it exists with the associated waiting I/O command subset of I/O command (such as { C1, C3 }) taken out from ordered set,
In one example, each I/O command in I/O command subset will be waited, attempts that ordered set (350) are added.For example, if waiting
I/O command C1 in I/O command subset does not conflict with any I/O command in ordered set, by I/O command C1 insertion sort collection
It closes, and guarantees that all elements in ordered set are orderly.If waiting the I/O command C3 in I/O command subset in ordered set
I/O command C3, is placed again into the associated waiting of I/O command for causing conflict in same ordered set by the conflict of one of any I/O command
In I/O command subset.In another example, as the substitution to step 350, if I/O command subset non-empty is waited, by I/O command
Into waiting the sequencing processing of I/O command subset to wait each I/O command in I/O command subset, until waiting I/O command
All orders concentrated all have been processed into.During this period, if distributor is assigned with new I/O command, and I/O command access is patrolled
Collect address with the logical address conflict for waiting the I/O command in I/O command subset handled, also in order by new I/O command
It is added to and waits in I/O command subclass, and is not added to ordered set.Alternatively, waiting all orders in I/O command subset
Period is all had been processed into, does not receive the new I/O command of distributor distribution temporarily.
Fig. 4 is according to the flow chart of the processing I/O command of the embodiment of the present application, as shown in figure 4, distributor receives I/O command
I/O command is distributed to and is used to handle one of multiple CPU (CPU 240 or CPU 250) of I/O command (referring also to figure by (410) afterwards
2).CPU judges the I/O command received as read command or write order (420).For read command (being denoted as read command R1), CPU sentences
Whether disconnected read command conflicts (430) with the element in ordered set.If read command R1 with any I/O command in ordered set all
Do not conflict (ranges of logical addresses does not overlap), read command R1 is handled (including access FTL table obtains physical address, from object
Address reading data is managed, and the data of reading are supplied to host etc.) (440), without read command R1 is added to ordered set.
Further, if read command R1 is placed in same write order C9 with write order (such as C9) conflict in ordered set by read command R1
In associated waiting I/O command subset (450), and read command R1 is not handled temporarily.In the fig. 4 embodiment, ordered set
In read command is not present, thus read command R1 will not be the same as the read command conflict in ordered set.
In alternative embodiments, even if there are read commands in ordered set, in step 430, if read command R1 is the same as row
Read command (such as C2) conflict in ordered sets, read command R1 is handled, without read command R1 is added to ordered set.
The write order (being denoted as write order W1) identified for step 420, CPU judge the member in write order and ordered set
Whether element conflicts (460).If write order W1 does not conflict with any I/O command in ordered set, write order W1 is added to row
Ordered sets (470), and (480) are handled to write order W1.If write order W1 in ordered set any write order (such as
Write order C9) conflict, then write order W1 is placed in the associated waiting I/O command subset of same write order C9 (490).It can manage
Xie Di, waiting in I/O command subset may include one or more etc. pending (identical or different type (read and/or write))
I/O command.
According to an embodiment of the present application, by using ordered set, barrier is provided with for I/O command.It is all to enter row
The I/O command of ordered sets, is equivalent to and has passed through barrier, can need not cause resource contention by concurrent processing.And it is placed into
I/O command to I/O command subset is equivalent to by barrier, will not by with other handle in I/O command concurrent processing, thus
Avoid resource contention.Also, it ensure that the atomicity of I/O command processing.It meets in NVMe specification to power down atomicity
(AWUPF, Atomic Write Unit Power Fail) and general atomicity (AWUN, Atomic Write Unit
Normal requirement).
And the operation in relation to ordered set is all the low latency operation of CPU operation local storage, will not be quoted long etc.
To the time, the external memory access of high latency is needed to operate caused by the lock of access FTL list item to eliminate.
In embodiment as shown in Figure 4, write order is only recorded in ordered set, without recording read command.Reduce row
Number of elements in ordered sets reduces demand of the ordered set to memory space, also reduces and searches member from ordered set
The calculation amount of element, has also speeded up the processing speed of read command, reduces read command processing delay.
Also read command is added in ordered set in step 440 as another embodiment.And correspondingly, exist
Step 460, if write order W1 is with the read command C2 conflict in ordered set, write order W1, which is placed in same read command C2, to be associated
Waiting I/O command subset in.
In the fig. 4 embodiment, in step 410, logical address of the distributor according to I/O command access, selection, which manages, includes
The CPU (for example, CPU 240, referring to Fig. 2) of the FTL exterior portion of the logical address point, is sent to CPU 240 for I/O command.CPU
240 safeguard ordered set for FTL table 260.And CPU 250 is that FTL table 270 safeguards another ordered set.
In an alternate embodiment of the invention, single complete FTL table is stored in DRAM 110, CPU 240 and CPU 250 are respective
Safeguard one's own ordered set (for example, ordered set S1 and ordered set S2).For example, the element in ordered set S1 is visited
The logical address for the odd number asked, and the logical address of the element access even number in ordered set S2.Optionally, it otherwise draws
It is divided to two ordered sets, for example, the logical address of the element in ordered set S1 is greater than the logic of the element in ordered set S2
Address.In step 410, logical address of the distributor according to I/O command access, selecting CPU management includes the sequence of the logical address
The CPU of set.
Fig. 5 is the schematic diagram according to the concurrent processing I/O command of the embodiment of the present application.As shown in figure 5, in response to I/O command
C0, C5, C9 and C2 (referring also to table 2) are added to ordered set, also start the processing to these I/O commands.I/O command is added
Time to I/O command can be different, and the time for handling beginning is also different.In Fig. 5, side that time shaft indicated by arrow is extended
To for the time pass direction, and logical address space axis direction indicated by arrow be logical address be incremented by direction.In Fig. 5, IO
Order the logical address of C0, C5, C9 and C2 non-overlapping, thus these I/O commands are by concurrent processing.And it is deposited with these I/O commands
It is placed in and is waited in I/O command subset in the I/O command C1 and C3 of conflict, and it is not processed.
According to an embodiment of the present application identification can concurrent processing I/O command, improve I/O command processing concurrency, increase
The strong performance of solid storage device, and need not use lock, and reduce the access times to external memory, reduces pair
The occupancy of external memory bandwidth.
Embodiment two
In the another embodiment according to the application, I/O command is split as one or more subcommands by distributor 230.
Illustratively, in some cases, the ranges of logical addresses (for example, 0-127) of write order access is greater than single FTL
Write order is split as multiple subcommands, each subcommand is visited in the case by the ranges of logical addresses (for example, 4) of list item
The ranges of logical addresses asked is no more than the ranges of logical addresses of a FTL list item.For example, write order access 0-7KB is logically
Location range is split as two sub- write orders for write order, and first sub- write order accesses 0-3KB ranges of logical addresses, and second
Sub- write order accesses 4-7KB ranges of logical addresses.As another example, the ranges of logical addresses of write order access 2-9KB, will
Write order is split as three sub- write orders, and first sub- write order is for accessing 2-3KB ranges of logical addresses, and second son is write
Order is for accessing 4-7KB ranges of logical addresses, and the sub- write order of third is for accessing 8-9KB ranges of logical addresses.Similarly,
Also read command is split as sub- read command.Sub- write order and sub- read command are referred to as subcommand.
Logical address of the distributor by subcommand according to its access is sent to one of CPU.CPU attempts received subcommand
It is added to ordered set, and the subcommand for being added to ordered set is handled.The element of ordered set is subcommand.Sequence
The ranges of logical addresses of any two element access in set is non-intersecting folded.If to be added to the same row of subcommand of ordered set
The ranges of logical addresses of any element in ordered sets, which exists, to be overlapped, which is placed in waiting
Subset of commands.Wait subset of commands associated with the subcommand in the ordered set for causing conflict.
CPU handles the subcommand for being added to ordered set, including access FTL table, accesses NVM chip, same to host
Transmit data etc..
It is had been processed into response to subcommand, the subcommand having been processed is taken out from ordered set.And it is optional
Ground, adjust ordered set, make wherein element still keep sorting.Further, if it exists with being taken out from ordered set
The associated waiting subset of commands of subcommand will wait each subcommand in subset of commands, attempt that ordered set is added.It can manage
Xie Di, for example, by subcommand insertion sort set, and being protected if subcommand does not conflict with any subcommand in ordered set
The all elements demonstrate,proved in ordered set are orderly.If subcommand is with any subcommand conflict in ordered set, again by subcommand
It is put into the associated waiting subset of commands of subcommand for causing conflict in same ordered set.
In the further embodiment according to the application, for sub- read command (being denoted as sub- read command SR1), if son reads life
SR1 is enabled not conflict (ranges of logical addresses does not overlap) with any subcommand in ordered set, at sub- read command SR1
Reason, without sub- read command SR1 is added to ordered set.Further, if sub- read command SR1 writes life with the son in ordered set
It enables (such as SW9) to conflict, sub- read command SR1 is placed in in the associated waiting subset of commands of sub- write order SW9.Implement herein
In mode, read command or sub- read command are not present in ordered set.
Further, for sub- write order (being denoted as sub- write order SW1), if sub- write order SW1 is the same as appointing in ordered set
What subcommand does not conflict, and sub- write order SW1 is added to ordered set, and handle sub- write order SW1.If son writes life
It enables SW1 with the sub- write order SW9 conflict in ordered set, is then placed in sub- write order SW1 associated etc. with sub- write order SW9
In Wait Order subset.
Optionally, it is handled according to the process of the processing I/O command of the embodiment of the present application by multiple CPU, controller collaboration.
In solid storage device, the multiple I/O commands of concurrent processing.In some cases, from read command or sub- read command from
In FTL table obtain physical address after, which is written over because of the processing to other write orders or erasing order, cause from
The physical address obtains the data of mistake.In the Chinese patent application application No. is 201610509669.2, provides and locating
Inspection is wiped free of block when managing read command and whether read physical address is written into the scheme of data.By its full text by drawing
With incorporated herein.
According to the another embodiment of the application, the control unit of solid storage device also safeguards physical block state table.Fig. 6 is
According to the physical block state table of the embodiment of the present application.Referring to Fig. 6, physical block state table 610, physical block state table 610 includes more
A entry (for example, 612 and 614), each entry corresponds to a physical block in solid storage device, and records with table clause pair
The physical block answered is to be in the state (referred to as " having been written into " state) for having been written to data in erase status.?
In one example, when physical block is wiped free of, more new physical block state table 610 is in erased state to identify physical block.And
When physical block is written for the first time, more new physical block state table 610, with identify physical block be in have been written into state.
Before issuing read command to NVM chip by Media Interface Connector 220 (referring also to Fig. 2), with from FTL list item 260 or FTL table
270 physical address obtained obtain the physical block where the physical address, and the physical block is inquired in physical block state table 610
State.If the physical block is in and has been written into state, read command is issued to NVM chip by flash interface；If the physical block
In erased state, then indicate to reset read command.
As an example, the meaning for resetting read command is, which is regarded as to the read command newly received, and locate again
Reason.For example, redistributing CPU by distributor 230 for the read command, or by one of CPU 240 or CPU 250 again to the reading
Order is handled.
The time is needed due to resetting read command, when reacquiring FTL list item, content has been updated with very maximum probability,
The FTL list item newly obtained will provide updated physical address, and store valid data in updated physical address.Few
In number situation, as an example, when reacquiring FTL list item, the update of FTL list item is not completed still, the FTL list item of reacquisition
It is still the old physical address in erased state.In the case, read command is reset, again to reacquire FTL table
?.
Fig. 7 is the schematic diagram according to the bulk of the embodiment of the present application.That is Fig. 7 shows the schematic diagram of bulk.Bulk includes
Physical block from each of multiple logic units (referred to as logic unit group).Optionally, each logic unit provides for bulk
One physical block.As an example, bulk is constructed on every 16 logic units (LUN).Each bulk includes 16 physical blocks, is come
From each of 16 logic units (LUN).In the example of fig. 7, bulk 0 includes every from 16 logic units (LUN)
A physical block 0, bulk 1 include the physical block 1 from each logic unit (LUN).It can also carry out structure there are many other modes
Make bulk.
As a kind of optional mode, page band, each interior same physical address of logic unit (LUN) are constructed in bulk
Physical Page constitute " page band ".In Fig. 7, Physical Page 0-0, Physical Page 0-1 ... and Physical Page 0-x constitute page band 0,
Wherein Physical Page 0-0, Physical Page 0-1 ... Physical Page 0-14 are for storing user data, and Physical Page 0-15 is for storing root
The verification data being calculated according to all customer data in band.Similarly, in Fig. 7, Physical Page 2-0, Physical Page 2-1 ...
Page band 2 is constituted with Physical Page 2-x.Optionally, appointing in page band can be located at for storing the Physical Page of verification data
Meaning position.
In the another embodiment according to the application, bulk state table is also safeguarded.Each of bulk state table program recording
Bulk is to be in the state (referred to as " having been written into " state) for having been written to data in erase status.In an example
In, when bulk is wiped free of, the entry of block bulk state table is updated, is in erased state to identify bulk.And work as bulk quilt
For the first time write-in data when, update bulk state table, with identify bulk be in have been written into state.
Before issuing read command to NVM chip by Media Interface Connector 220 (referring also to Fig. 2), with from FTL list item 260 or FTL table
270 physical address obtained obtain the bulk where the physical address, and the state of the bulk is inquired in bulk state table.If
The bulk is in and has been written into state, then issues read command to NVM chip by flash interface；If the bulk is in and is wiped free of shape
State then indicates to reset read command.
According to the still another embodiment of the application, is issued and read to NVM chip by Media Interface Connector 220 (referring also to Fig. 2)
Before order, do not check whether the physical address that read command is accessed is in erased state.But check the execution knot of read command
Fruit, to know whether the physical address of read command access is in erased state.In one example, NVM chip is reading number
According to result in such instruction is provided, to identify whether read Physical Page is in erased state.In another example
In, whether the flash interface of the control unit data read-out according to the data judgement read from NVM chip, which come to be in, is wiped
Except the Physical Page of state.
If the corresponding Physical Page of physical address for reading data result instruction read command is in erased state, the reading is reset
Order.If the corresponding Physical Page of physical address for reading data result instruction read command is non-to be in erased state, read
Data it is effective, using the data of reading as the response to read command.As the physics where the corresponding physical address of read command
The probability that block or block band are in erased state is very low, in most cases, checks whether physical address is in and is wiped free of
The operation of state will introduce additional delay.In the present embodiment, it after obtaining the read command physical address to be accessed, does not check
Whether physical block or block band where physical address are in erased state, and directly from physical address reading data, and according to
Lai Yu reads the instruction that data result provides to judge whether read Physical Page is in erased state.To only read
When the Physical Page taken is in erased state, additional processing is carried out, reduces the average treatment delay of read command.
Fig. 8 is the writing position table according to the embodiment of the present application.It is had recorded in writing position table 820 and is currently written into block or bulk
In current location to be written.The position to be currently written can be the page (being indicated by page address or page number) in physical block,
It is also possible to location to be written in the page band in bulk.In an embodiment according to the present invention, when responding write order,
Control unit is sequentially the write order distribution physical address to be written.For example, current write location is the 100th piece of NVM chip
Page 100, when for write order allocated physical address, by the 100th piece of the physical address assignments of page 100 to write order,
And the physical address of distribution is recorded in the list item of FTL table, and make current write location is incremental (to become the 101st of the 100th piece
Page).And when responding write order again, new current write location (page 101 of the 100th piece) is distributed physically for write order
Location.Optionally, data only are written to one or a small amount of physical block or bulk in synchronization in control unit, thus, writing position
It only needs to provide one or a small amount of list item in table 820, without occupying a large amount of memory spaces.In another example, current write bit
Set the logic unit to be currently written into (LUN) in instruction page band, such as the 3rd of the band of page 100 of the 100th piece of band
Logic unit.When for write order allocated physical address, by the 3rd logic unit institute of the band of page 100 of the 100th piece of band
The physical address assignments of corresponding page are recorded in the list item of FTL table to write order, and by the physical address of distribution, and make to work as
Preceding writing position is incremented by (the 4th logic unit for becoming the band of page 100 of the 100th piece of band).And when responding write order again,
New current write location (the 4th logic unit of the band of page 100 of the 100th piece of band) is distributed physically for write order
Location.
Control unit also safeguards that physical block or bulk are in the state for being wiped free of or having been written into (referring also to Fig. 6).Control unit
Before part issues read command to NVM chip by flash interface, the physical address institute is obtained with the physical address obtained from FTL list item
Physical block or bulk.Inquire the state of the physical block or bulk.If the physical block is in erased state, reading life is reset
It enables.If the physical block or bulk, which are in, has been written into state, whether the further relatively presently written position of physical block or bulk
It is ahead of the physical address obtained from FTL list item.The presently written of physical block or bulk is obtained from the writing position table (referring to Fig. 8)
Position, and be compared with the physical address obtained from FTL list item.If presently written position is ahead of physical address, show
The physical address has been written to data, to issue read command to the physical address and read data.If presently written position
It is not advanced or lag behind the physical address, show that the physical address is not yet written into data, can not be read at this time from the physical address
Correct data out, thus the read command is reset, or suspend the processing to the read command, wait presently written position to be ahead of
The physical address.Data are read after presently written position is ahead of the physical address, then from the physical address.
It is not first checked for after obtaining the corresponding physical address of read command from FTL table according to the another embodiment of the application
Whether physical block or block band where the physical address are in erase status.Because of physical block or block where the physical address
The probability that band is in erase status is very low, in most cases, checks whether that the operation in erase status will introduce volume
Outer delay.But data directly are read from the physical address, and the instruction dependent on reading data result offer is to judge
Whether the Physical Page of reading is in erase status.To only when read Physical Page is in erase status, carry out additional
Processing reduces the average treatment delay of read command.If reading data result indicates that the corresponding Physical Page of the physical address is in
Erase status obtains corresponding physical block or bulk according to the physical address, obtains the state of corresponding physical block or bulk.If
Physical block or bulk where the physical address, which are in, has been written into state, then further judges whether presently written position surpasses
It is preceding in the physical address.If presently written position is ahead of the physical address, show that the physical address has been written to data, from
And read command is issued to the physical address and reads data.If presently written position is not advanced or lags behind the physical address, table
The bright physical address is not yet written into data, can not read correct data from the physical address at this time, thus suspends to the reading
The processing of order waits presently written position to be ahead of the physical address.After presently written position is ahead of the physical address,
Data are read from the physical address again.If the physical block or bulk where the physical address are in erased state, visit again
It asks FTL table and obtains updated physical address.And next, it is judged that updated physical address and presently written position
Relationship simultaneously carries out subsequent processing.
In above embodiment, based on the inspection of the physical address accessed read command, the feelings for being wiped free of page are read in processing
Condition.In the still another embodiment according to the application, the case where reading of logic-based address process is wiped free of page.
Referring to the step 440 of Fig. 4, in response to handling read command, for example, CPU 240 or CPU 250 be it is each in processes
Read command safeguard metadata.Metadata includes the more New count of the logical address block where read command.As an example, meter is updated
Several initial values is 0.With read command, corresponding logical address block is continuously patrolling for the logical address accessed comprising read command
Collect address range.As an example, each logical address block includes logical address indicated by the entry of hundreds of-thousands of FTL tables.
As another example, the range of physical addresses phase of ranges of logical addresses size that each logical address block includes with physical block
Together or each logical address block ranges of logical addresses size for including be physical block range of physical addresses multiple.Each
Logical address block can ranges of logical addresses having the same, and be adjacent to arrangement by logical address.
With continued reference to Fig. 4, write order visit is also checked in response to handling write order in step 470 or step 480
The corresponding logical address block of the logical address asked, if identical with the corresponding logical address block of read command in processing.If writing life
The logical address block for enabling the logical address of access, it is identical with the corresponding logical address block of read command (being denoted as R1) in processing, it will
The more New count of logical address block in the metadata of read command R1 is incremented by, to indicate indicated by the logical address block logically
There is the write order handled in the range of location.If the logical address block of the logical address of write order access, with multiple in processing
The corresponding logical address block of read command (being denoted as R2, R3) is identical, by the metadata of read command R2 and read command R3 logically
The more New count of location block is incremented by respectively, to indicate with logic indicated by read command R2 logical address block corresponding with read command R3
There is the write order handled in address range.
The write order handled may cause and indicate with logical address block the FTL table clause of corresponding logical address
Physical address is updated.And then cause the read command for accessing identical FTL table clause that the physical address before updating is accessed.Further
Ground, the physical address before update have certain probability to be wiped free of, and cause read command that the physical address being wiped free of is accessed.
As another example, logic that the metadata record read command of the read command in step 440, processing is accessed
The more New count of address.And in step 470 or step 480, it is ordered in response to the logical address of write order access with the reading in processing
It enables accessed logical address identical or overlaps mutually, the more New count of read command is incremented by.Optionally, in step 470 or step
Rapid 480, in response to the corresponding logical address block of write order with the logical address of the corresponding logical address block of read command in processing
Range is identical or overlaps mutually, and the more New count of read command is incremented by.
Fig. 9 is according to the extension flow chart for handling read command in the application still another embodiment.In response to from NVM chip
The data (910) that read command is accessed are obtained, identify whether logical address block corresponding to read command is updated (920).Make
To illustrate, if having the corresponding FTL of any logical address in ranges of logical addresses indicated by the corresponding logical address block of read command
Table clause is updated, then it is assumed that the corresponding logical address block of the read command is updated.As another example, according to read command
The more New count of metadata is greater than initial value (such as 0), it is believed that the corresponding FTL table clause of the logical address of read command is updated.
If the corresponding logical address block of step 920 identification read command is not updated, the number that the read command obtained is accessed
According to effective, read data (930) are provided to host.If step 920 identifies that the corresponding logical address block of read command is being read to order
Order handle during be updated, then the data that read command is accessed may be it is invalid, read command is handled again.
To handle read command again, checks that read command whether there is with the element in ordered set and conflict (940).If reading life
It enables with the element in ordered set there is no conflicting, read command is handled again, access FTL table again and obtain physically
Location reads again data from physical address, and the data of reading is supplied to host.
As an example, in step 440, also record obtains physically from FTL table also in the metadata of read command
Location, and in step 960, also identification from the physical address obtained again in FTL table with the physical address recorded in metadata whether
Unanimously.If different with the physical address recorded in metadata from the physical address obtained again in FTL table, again from physically
Data are read in location, and the data of reading are supplied to host.If from the physical address obtained again in FTL table with remembering in metadata
The physical address of record is identical, then need not read data by physical address again, and the data obtained in step 910 are supplied to master
Machine.
As another example, in step 440, without the physics that record is obtained from FTL table in the metadata of read command
Address.And in step 960, physical address is obtained from FTL table, but need not identify that physical address is in read command period processed
It is no to be updated.And data are read from physical address again, and the data of reading are supplied to host.
Conflict if read command exists with the element in ordered set, read command is added to, I/O command subset is waited (also to join
See the step 450) of Fig. 4.
It is handled in response to read command and completes (930), also discharge the metadata of read command.To one of read command (such as R2)
The release of metadata does not influence the metadata of other read commands (such as R3).It is patrolled even if read command R2 is corresponding with read command R3
Volume address block is identical or overlaps mutually.
Although the preferred embodiment of the application has been described, but those skilled in the art once know basic creativeness generally
It reads, then additional changes and modifications may be made to these embodiments.So it includes preferred real that the following claims are intended to be interpreted as
It applies example and falls into all change and modification of the application range.Obviously, those skilled in the art can carry out the application each
Kind modification and variation is without departing from spirit and scope.In this way, if these modifications and variations of the application belong to this
Within the scope of applying for claim and its equivalent technologies, then the application is also intended to include these modifications and variations.
Claims (10)
1. a kind of concurrent I/O command without lock processing method characterized by comprising
Receive the first I/O command；
Judge whether the first I/O command conflicts with any I/O command in ordered set；
Do not conflict in response to the first I/O command with any I/O command in ordered set, the first I/O command is inserted into sequence collection
In conjunction, the first I/O command is handled；
It is had been processed into response to the first I/O command, the first I/O command is taken out from ordered set.
2. the method as described in claim 1, which is characterized in that further include:
In response to the first I/O command with any I/O command conflict in ordered set, the first I/O command is placed in waiting set.
3. method according to claim 2, which is characterized in that further include:
The first I/O command is obtained from waiting in set, is disappeared in response to the first I/O command with any I/O command conflict in ordered set
It loses, the first I/O command is inserted into ordered set, and the first I/O command of processing.
4. method as described in any one of claims 1 to 3, which is characterized in that in response to the first I/O command in ordered set
The second I/O command conflict, the first I/O command is placed in in the associated waiting subset of the second I/O command.
5. method as claimed in claim 4, which is characterized in that the second I/O command has been processed into and moves from ordered set
It removes, third I/O command is obtained from the same associated waiting subset of second I/O command, and attempt for third I/O command to be added and sort
Set.
6. such as method described in any one of claim 1 to 5, which is characterized in that if the first I/O command is read command, directly to the
One I/O command is handled, without the first I/O command is added to ordered set.
7. such as method as claimed in any one of claims 1 to 6, which is characterized in that the first I/O command of processing includes according to the first IO
The logical address access FTL table of command access obtains corresponding physical address, accesses the physical address to respond the first IO life
It enables.
8. according to the method described in claim 7, further include:
If presently written position lags behind the first physical address, suspend the processing to the first read request, until presently written position
It is ahead of the first physical address.
9. a kind of concurrent I/O command without lock processing system characterized by comprising
Receiving module, for receiving the first I/O command；
Judgment module, for judging whether the first I/O command conflicts with any I/O command in ordered set；
Processing module orders the first IO for not conflicting in response to the first I/O command with any I/O command in ordered set
Order is inserted into ordered set, handles the first I/O command；
Module is taken out to take out the first I/O command from ordered set for having been processed into response to the first I/O command.
10. a kind of solid storage device, which is characterized in that including control unit, NVM chip and memory, control unit difference
It is coupled to NVM chip and memory, the control unit executes method described in one of -8 according to claim 1.
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