CN109144907B - Method for realizing quick reading and medium interface controller - Google Patents
Method for realizing quick reading and medium interface controller Download PDFInfo
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- CN109144907B CN109144907B CN201710499881.XA CN201710499881A CN109144907B CN 109144907 B CN109144907 B CN 109144907B CN 201710499881 A CN201710499881 A CN 201710499881A CN 109144907 B CN109144907 B CN 109144907B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
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Abstract
The application provides a method for realizing quick reading and a medium interface controller. The method for realizing the quick reading comprises the following steps: acquiring a first message for accessing a logic unit; if the first message indicates to read the logic unit, generating and sending a read command to the logic unit; acquiring a second message for accessing the same logic unit; if the second message indicates to read the logic unit, generating and sending a 'fast reading' command to the logic unit; the receive logic unit responds to read data provided by the read command.
Description
Technical Field
The present application relates to the field of memory controller technology, and more particularly to generating fast read commands.
Background
The "Read Cache" series of commands, including "Read Cache Sequential" and "Read Cache Random", are defined in the ONFI interface standard (available in http:// www.onfi.org// media/ONFI/specs/ONFI _4_0-gold. pdfla ═ en). Similar "Sequential Cache Read" and "Random Cache Read" commands are defined in the Toggle interface standard.
In the present application, "Cache Read" series commands, "Read Cache" series commands, and the like are collectively referred to as "Cache Read (fast Read)" commands. The memory controller issues a "Cache Read" command to the NAND flash memory chip instructing the NAND chip to Read one page of data from the page register and simultaneously Read another page of data from the flash memory cell array on the same LUN (logical UNit).
The mainstream NAND flash memory chip supports the command of "Cache Read".
The memory Target (Target) is one or more Logical Units (LUNs) of a shared Chip Enable (CE) signal within the flash Chip package. One or more dies (Die) may be included within the NAND flash memory chip package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other. In the ONFI/Toggle interface standard, the meaning for target (target), logical unit, LUN, Plane (Plane) is also provided, and the commands to operate the NVM chip are also provided.
NVM (Non-Volatile Memory) is used to implement Memory function and has Non-Volatile feature. Fig. 1 is a block diagram of a solid-state storage device of the prior art, and a solid-state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.
NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.
The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof; the control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands; the control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110; FTL tables and/or cached IO command data may be stored in the DRAM.
The control unit 104 of the solid-state storage device includes, for example, a host interface, a front-end processing module, a flash management module, and one or more media interface controllers (or flash interface controllers, flash channel controllers). The host interface is used for exchanging commands and data with the host. The flash memory management module provides functions of mapping from a logical address to a physical address, wear leveling, garbage recovery and the like, generates a message for accessing the NVM chip and sends the message to the media interface controller. The media interface controller is coupled to NVM chip 105. There are one or more media interface controllers, each coupled to a respective NVM chip 105. The media interface controller receives the message to access the NVM chip and issues a command (e.g., a read, program, erase, pause, read feature (feature) and/or set feature command) to the NVM chip 105 in accordance with the message to access the NVM chip and in a manner that conforms to an interface protocol (e.g., ONFI, Toggle interface standard) of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. The media interface controller receives messages from, for example, queues, bus interfaces, and/or memory to access the NVM chip.
The media interface controller is typically coupled to a plurality of NVM chips that include multiple LUNs (logical units) or dies that can respond to commands in parallel.
Chinese patent applications CN201610009789.6 and CN201510253428.1 provide a method and apparatus for executing micro instructions for a media interface controller, while chinese patent application CN201610861793.5 provides a method and apparatus for scheduling micro instruction sequences, and chinese patent application 201710204980.0 provides a control-intensive control system and method, the entire contents of which are incorporated herein. Alternatively, the media interface controller may include one or more CPUs that receive and process messages to access the NVM chip, issue commands to the NVM chip, and receive responses by running a program.
Disclosure of Invention
The method for realizing the rapid reading and the media interface controller solve the problem of automatic generation of the Cache Read command. And generating a Cache Read command according to the existence of a plurality of messages for accessing the LUN in a specified mode so as to reduce the delay of reading data from the NVM chip and improve the performance of the solid-state storage device.
According to the embodiment of the application, the reading performance of the solid state disk product can be improved, the intervention of upper software is not needed, and whether the fast reading is carried out or not can be completely and automatically judged.
According to a first aspect of the present application, there is provided a method for implementing fast reading according to the first aspect of the present application, including: acquiring a first message for accessing a logic unit; if the first message indicates to read the logic unit, generating and sending a read command to the logic unit; acquiring a second message for accessing the same logic unit; if the second message indicates to read the logic unit, generating and sending a 'fast reading' command to the logic unit; the receive logic unit responds to read data provided by the read command.
According to a first method for implementing fast read of the first aspect of the present application, a second method for implementing fast read of the first aspect of the present application is provided, wherein a message for accessing a logical unit is obtained from a message queue and/or a memory.
According to the first or second method for implementing fast reading of the first aspect of the present application, there is provided a third method for implementing fast reading of the first aspect of the present application, wherein the read command is a read command conforming to the ONFI standard or the TOGGLE standard.
According to one of the methods of implementing fast read of the first to third aspects of the present application, there is provided a fourth method of fast read according to the first aspect of the present application, wherein the "fast read" command is a "fast read" command conforming to the ONFI standard or a "fast read" command conforming to the TOGGLE standard.
According to one of the first to fourth methods for implementing fast reading in the first aspect of the present application, there is provided a fifth method for implementing fast reading in the first aspect of the present application, wherein if the type of the first message accessing the logic unit indicates a non-read logic unit, a command corresponding to the first message accessing the logic unit is generated and sent to the logic unit.
According to one of the first to fifth fast reading methods of the first aspect of the present application, there is provided the sixth fast reading method of the first aspect of the present application, wherein if the type of the second message accessing the same logical unit indicates a non-read logical unit, a command corresponding to the second message accessing the logical unit is generated and sent to the logical unit.
According to one of the methods of implementing fast read of the first to sixth aspects of the present application, there is provided the seventh fast read method according to the first aspect of the present application, wherein a second message for accessing the same logical unit is acquired during a time period from when the read command is sent to the logical unit to when the logical unit outputs data corresponding to the read command.
According to a seventh implementation fast read method of the first aspect of the present application, there is provided a method of implementing fast read according to the eighth aspect of the present application, wherein a second message accessing the same logical unit is obtained towards the end of the time period.
According to one of the methods for implementing fast reading in the first to eighth aspects of the present application, there is provided a method for implementing fast reading in the ninth aspect of the present application, wherein after receiving read data of a first message provided by a logic unit, a third message for accessing the same logic unit is obtained.
According to a ninth implementation fast reading method of the first aspect of the present application, there is provided the tenth implementation fast reading method of the first aspect of the present application, wherein if the type of the third message accessing the logical unit indicates to read the logical unit, a "fast read" command is sent to the logical unit, and data corresponding to the second message read from the logical unit is received.
According to a tenth implementation fast reading method of the first aspect of the present application, there is provided the eleventh implementation fast reading method of the first aspect of the present application, wherein if the type of the message accessing the logical unit indicates a non-read logical unit, an end command corresponding to the "fast read" command is generated and sent to the logical unit, and data corresponding to the second message read from the logical unit is received.
According to a second aspect of the present application, there is provided a method for implementing fast reading according to the first aspect of the present application, comprising: running a first thread to acquire a first message for accessing the logic unit; if the first message indicates to read the logic unit, generating and sending a read command to the logic unit, and recording the state of the first thread to enable the first thread to be dormant; restoring the state of the first thread in response to the occurrence of the second message to access the logical unit to retrieve the second message to access the logical unit; if the second message indicates to read the logic unit, generating and sending a 'fast reading' command to the logic unit; receiving read data of the first message provided by the logic unit.
According to a first method of implementing fast read according to the second aspect of the present application, there is provided a method of implementing fast read according to the second aspect of the present application, the thread corresponding to one or more logical units.
A method of implementing fast read according to a third aspect of the present application is provided, the scheduler selecting the other thread to be executed by the processor in response to the first thread sleeping.
According to one of the methods of implementing fast read of the second aspect of the present application, there is provided the method of implementing fast read of the fourth aspect of the present application, wherein the scheduler schedules the first thread to execute on the processor near completion of the processing in the read command.
According to a third aspect of the present application, there is provided a method for implementing fast read according to the first aspect of the present application, obtaining a message for accessing a logical unit; if the message indicates to read the logic unit and the logic unit is processing the read command or the fast read command, generating the fast read command and sending the fast read command to the logic unit; and receiving read data provided by the logic unit in response to the read command.
According to the first method for realizing fast reading of the third aspect of the present application, there is provided a method for realizing fast reading according to the second aspect of the present application, further comprising: if the message indicates a read logical unit and there is no pending read command or "fast read" command on the logical unit, a read command is generated and sent to the logical unit.
According to the second method for implementing fast reading of the third aspect of the present application, there is provided the method for implementing fast reading of the third aspect of the present application, recording the read command or "fast read" command being processed on the logic unit.
According to one of the methods of implementing fast reading of the third aspect of the present application, there is provided a method of implementing fast reading according to the fourth aspect of the present application, further comprising: if the message indicates a non-read logical unit and a 'fast read' command is being processed on the logical unit, generating and sending an end command corresponding to the 'fast read' command to the logical unit; receiving read data provided by the logic unit in response to the fast read command; and generating a command corresponding to the message for accessing the logic unit and sending the command to the logic unit.
According to one of the methods of implementing fast read of the third aspect of the present application, there is provided the method of implementing fast read of the fifth aspect of the present application, wherein a message for accessing the same logical unit is acquired during a period from a time when a read command or a "fast read" command is sent to the logical unit to a time when the logical unit outputs data corresponding to the read command or the "fast read" command.
According to a fifth implementation fast reading method of the third aspect of the present application, there is provided a sixth implementation fast reading method of the third aspect of the present application, wherein a message accessing the same logical unit is obtained towards the end of the time period.
According to one of the methods for implementing fast reading in the first to sixth aspects of the present application, there is provided a method for implementing fast reading in the seventh aspect of the present application, wherein after sending a read command to a logic unit, a message for accessing the same logic unit is obtained again.
According to one of the methods for implementing fast reading in the first to seventh aspects of the present application, there is provided a method for implementing fast reading in the eighth aspect of the present application, wherein if it is recognized that the type of the message accessing the logical unit indicates a non-read command and there is a read command being processed on the logical unit, data read by the read command is received after the read command processing is completed.
According to one of the methods for realizing fast reading in the sixth aspect to the eighth aspect of the present application, there is provided the method for realizing fast reading in the ninth aspect of the present application, in response to the read data being acquired from the logic unit, generating a corresponding command according to the message for accessing the logic unit and sending the command to the logic unit.
According to a ninth implementation fast reading method of the third aspect of the present application, there is provided a tenth implementation fast reading method of the third aspect of the present application, where after sending a corresponding command to a logic unit, a message for accessing the logic unit is obtained again.
According to one of the methods of implementing fast read in the first to tenth aspects of the present application, there is provided the method of implementing fast read in the eleventh aspect of the present application, wherein when the read command processing is completed, or in response to an end command being issued and the corresponding "fast read" command processing is completed, the read command or the "fast read" command that is not currently being processed on the logical unit is also recorded.
According to a fourth aspect of the present application, there is provided a first media interface controller according to the fourth aspect of the present application, comprising a scheduler, a processor, a status register, a media interface, a message queue, and one or more threads capable of being scheduled by the scheduler and executed by the processor; the processor is respectively coupled to the status register, the medium interface and the message queue; the message queue provides messages for accessing the logical unit; the state register saves the state of the thread; wherein the processor runs a thread to perform one of the methods of implementing fast read according to the first, second, third aspect of the present application.
According to a fifth aspect of the present application, there is provided a system for implementing fast reading according to the first aspect of the present application, comprising: the first acquisition module is used for acquiring a first message for accessing the logic unit; the first judgment module is used for generating and sending a read command to the logic unit if the first message indicates to read the logic unit; the second acquisition module is used for acquiring a second message for accessing the same logic unit; the second judgment module is used for generating and sending a 'quick reading' command to the logic unit if the second message indicates to read the logic unit; and the receiving module is used for receiving the read data provided by the logic unit in response to the read command.
According to a sixth aspect of the present application, there is provided a system for implementing fast reading according to the first aspect of the present application, comprising: the acquisition module is used for acquiring the information of the access logic unit; the first judging module is used for generating a fast reading command and sending the fast reading command to the logic unit if the message indicates to read the logic unit and the logic unit is processing a reading command or a fast reading command; and the receiving module is used for receiving the read data provided by the logic unit in response to the read command.
According to a seventh aspect of the present application, there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to perform one of the methods of implementing fast read according to the first, second or third aspect of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a block diagram of a solid-state storage device of the prior art;
FIG. 2 is a flow diagram of generating a "fast read" command according to an embodiment of the present application;
FIG. 3 is a block diagram of a media interface controller according to an embodiment of the present application; and
FIG. 4 is a flow diagram of generating a "fast read" command according to yet another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the present application, if there are consecutive read commands accessing the same logical unit, the subsequent read command is replaced by a "fast read" command. And issues a "fast read" command to the same logical unit before the previous read command execution is complete (e.g., before the data is read).
Further, for multiple consecutive read commands accessing the same logical unit, the read commands are replaced by a "fast read" command, except for the oldest read command. Since the "fast read" command is issued to the logic unit before the read command execution is complete, the read command is executed in parallel with the "fast read" command on the logic unit, thereby reducing the overall latency of the read data process.
Example one
FIG. 2 is a flow diagram of generating a "fast read" command according to an embodiment of the present application. As shown in fig. 2, the control section of the solid-state storage device (see also fig. 1, control section 104) converts a command from the host to access the storage device into a message to access a Logical Unit (LUN). Control component 104 or the media interface controller obtains a message to access a LUN (210). By way of example, a message accessing a LUN is retrieved from a message queue and/or memory.
Next, the control section 104 or the media interface controller receives read-out data provided by the LUN (270), the read-out data being data read based on the read command in step 230.
Optionally, in step 220, if the type of the message accessing the same LUN indicates a non-read LUN (e.g., write data to the LUN, erase a physical block on the LUN, etc.), a command corresponding to the message accessing the LUN is generated and sent to the LUN.
Still alternatively, in step 250, if the type of the message accessing the same LUN indicates a non-read LUN (e.g., write data to the LUN, erase a physical block on the LUN, etc.), a command corresponding to the message accessing the LUN is generated and sent to the LUN.
Still alternatively, in step 230, there is a specified time period from sending the read command to the LUN until the LUN outputs the data corresponding to the read command. During a specified time period, steps 240 through 260 are performed to generate and send a "fast read" command to the LUN. Preferably, steps 240 through 260 are performed towards the end of the specified time period to promote the chance of recognizing a continuous read LUN type message. For example, steps 240 through 260 are performed about 5us before the expiration of the specified time period.
Still alternatively, after step 270, the message accessing the same LUN is acquired again. If it is recognized that the type of the message accessing the LUN still indicates to read the LUN, a "fast read" command is sent to the LUN again, and data read from the LUN is received. The data read out from the LUN at this time is read out data corresponding to the "fast read" command sent in step 260. And after step 270, obtaining the information for accessing the LUN, and if the type of the information for accessing the LUN is identified to indicate a non-read LUN, the condition for generating the "fast read" command is no longer met. Accordingly, an "end" command corresponding to the "fast read" command is generated and sent to the LUN, and data read out from the LUN is received. The data read out from the LUN at this time is read out data corresponding to the "fast read" command sent in step 260.
Fig. 3 is a block diagram of a media interface controller according to an embodiment of the present application. As shown in fig. 3, the media interface controller includes a scheduler 330, a processor 340, status registers 350, a media interface 360, a message queue 370, and one or more threads (e.g., thread 300, thread 310, and thread 320) that may be scheduled by scheduler 330 and executed by processor 340.
The message queue 370 provides messages that access the LUN. The thread, when executed by the processor 340, retrieves a message from the message queue 370 to access a LUN and operates the media interface 360 to generate a command to operate the LUN. The running state of the thread and/or the execution state of the command to operate the LUN is recorded in the state register 350. Thus, while waiting for the LUN to execute the command, the state of the thread is saved in the state register 350 and the scheduler 330 schedules other threads to execute on the processor 340. Processor 340 may execute instructions and/or microinstructions that make up a thread.
The threads correspond to the specified LUN or LUNs. For example, messages accessing LUN 0 are all processed by thread 300, while messages accessing LUN 1 and/or LUN 2 are all processed by thread 310.
According to the embodiment of the present application, taking thread 300 as an example, processor 340 runs thread 300, obtains a message for accessing LUN 0 from message queue 370 (see also fig. 2, step 210), recognizes that the message for accessing LUN 0 indicates reading LUN (220), and issues a read command (denoted as R0) to LUN 0 (see also fig. 2, step 230). Next, the state of thread 300 (including the state of read command R0) is recorded in state register 350, and scheduler 330 selects other threads to be executed by processor 340, such as thread 310 and thread 320.
After a period of time, for example, in anticipation of the completion of processing by read command R0 issued by thread 300 to LUN 0, scheduler 330 schedules thread 300 for execution on processor 340. Thread 300 uses the status recorded in status register 350 and again retrieves the message from message queue 370 that accessed LUN 0 (240) and recognizes that the new message that accessed LUN 0 still indicates read LUN (250), thread 300 generates a "fast read" command from the new message that accessed LUN 0 and sends to LUN 0(260) based on that LUN 0 has read command R0 on it and a message indicating read LUN 0 again appears, and receives read data from LUN 0 (270), which corresponds to read command R0 of step 230.
Example two
FIG. 4 is a flow diagram of generating a "fast read" command according to yet another embodiment of the present application. As shown in FIG. 4, the media interface controller obtains a message (400) accessing a LUN, identifies the type of message (410) accessing the LUN, and if a read LUN is indicated, further identifies whether there is a pending read command or "fast read" command on the LUN to be read (420). For example, a read command or "fast read" command that is being processed on the LUN to be read is identified by accessing the status register 350 or status flag.
If there is a read command or a fast read command being processed on the LUN to be read, the media interface controller generates a fast read command according to a message for accessing the LUN and sends the fast read command to the LUN (430) in response before the read command or the fast read command being processed on the LUN is processed. Next, data corresponding to the access result of the read command or "fast read" command being processed on the LUN identified in step 420 is received from the LUN (440). And returns to step 400 to obtain further information for accessing the LUN.
Alternatively, after generating and sending a "fast read" command to the LUN, the state of the current thread (e.g., thread 300) is backed up and the scheduler 330 (see also FIG. 3) selects another thread (e.g., thread 310 or thread 320) to execute on the processor 340. After receiving the read data from the LUN, the state of the current thread (e.g., thread 300) is also backed up and other threads (e.g., thread 310 or thread 320) are selected to execute on processor 340.
If it is identified that there is no pending read command or "fast read" command on the LUN to be read, at step 420, a read command is sent to the LUN according to the obtained message to access the LUN (450). And returns to step 400 to obtain further information for accessing the LUN. Optionally, after sending the read command to the LUN, the processing state of the current read command is backed up (e.g., the current thread is put to sleep), and other messages are processed or other threads are selected to execute on the processor 340.
If, at step 410, it is identified that the type of message accessing the LUN indicates a non-read command, it is further identified whether there is a read command or "fast read" command being processed on the LUN to be accessed (460). If there is a "fast read" command being processed on the LUN to be accessed, an end command is sent to the LUN (470) and the data read by the "fast read" command is received (480). If there is a read command being processed on the LUN to be accessed, the data read by the read command is received after the read command processing is completed (480). Optionally, prior to receiving the read data, the state of the current thread is also backed up and other threads are selected for execution on processor 340. And restores the backed up state and continues to receive data read by the read command in response to the LUN being able to provide the read data. In response to the read data being obtained from the LUN, a corresponding command is generated from a message to access the LUN and sent to the LUN (490). Then return to step 400 to obtain further information for accessing LUN.
After sending a read command or "fast read" command to a LUN, it is also recorded that there is a read command or "fast read" command being processed on the LUN. Read commands or "fast read" commands that are not currently being processed on the LUN are also recorded after read command processing is complete, or in response to an end command being issued and a corresponding "fast read" command processing being complete.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method for implementing fast read, comprising:
acquiring a first message for accessing a logic unit;
if the first message indicates to read the logic unit, generating and sending a read command to the logic unit;
acquiring a second message for accessing the same logic unit;
if the second message indicates to read the logic unit, generating and sending a 'fast reading' command to the logic unit;
receiving read data provided by the logic unit in response to the read command;
the command of fast reading is one of the commands of 'Read Cache' series conforming to ONFI standard or one of the commands of 'Cache Read' series conforming to TOGGLE standard; a "fast read" command is sent to the logical unit as a response to the second message obtained to access the same logical unit.
2. The method of implementing a fast read as recited in claim 1, wherein the second message accessing the same logical unit is obtained during a time period from when the read command is sent to the logical unit to when the logical unit outputs data corresponding to the read command.
3. The method of implementing a fast read as in claim 2 wherein a second message accessing the same logical unit is obtained near the end of the time period.
4. A method for performing a fast read as claimed in any one of claims 1 to 3, wherein if the type of message accessing the logical unit indicates a non-read logical unit, an end command corresponding to the "fast read" command is generated and sent to the logical unit, and data corresponding to the second message read from the logical unit is received.
5. A method for implementing fast read, comprising:
running a first thread to acquire a first message for accessing the logic unit;
if the first message indicates to read the logic unit, generating and sending a read command to the logic unit, and recording the state of the first thread to enable the first thread to be dormant;
restoring the state of the first thread in response to the occurrence of the second message to access the logical unit to retrieve the second message to access the logical unit;
if the second message indicates to read the logic unit, generating and sending a 'fast reading' command to the logic unit;
receiving read data of a first message provided by the logic unit;
the command of fast reading is one of the commands of 'Read Cache' series conforming to ONFI standard or one of the commands of 'Cache Read' series conforming to TOGGLE standard; a "fast read" command is sent to the logical unit as a response to the second message obtained to access the same logical unit.
6. A method for implementing fast read, comprising:
acquiring a message for accessing the logic unit;
if the message indicates to read the logic unit and the logic unit is processing the read command or the fast read command, generating the fast read command and sending the fast read command to the logic unit; and
receiving read data provided by the logic unit in response to the read command;
the command of fast reading is one of the commands of 'Read Cache' series conforming to ONFI standard or one of the commands of 'Cache Read' series conforming to TOGGLE standard; a "fast read" command is sent to the logical unit as a response to the second message obtained to access the same logical unit.
7. The method of implementing fast reading as claimed in claim 6, further comprising:
if the message indicates a non-read logical unit and a 'fast read' command is being processed on the logical unit, generating and sending an end command corresponding to the 'fast read' command to the logical unit;
receiving read data provided by the logic unit in response to the fast read command; and
and generating a command corresponding to the message for accessing the logic unit and sending the command to the logic unit.
8. The method for implementing fast read as claimed in claim 6 or 7, wherein if the type of the message accessing the logical unit is identified to indicate a non-read command and there is a read command being processed on the logical unit, the data read by the read command is received after the read command processing is completed.
9. A media interface controller comprising a scheduler, a processor, a status register, a media interface, a message queue, and one or more threads capable of being scheduled by the scheduler and executed by the processor; the processor is respectively coupled to the status register, the medium interface and the message queue; the message queue provides messages for accessing the logical unit; a state register to hold a state of a thread, wherein the processor runs the thread to perform the method according to one of claims 1 to 8.
10. A system for implementing fast reading, comprising:
the first acquisition module is used for acquiring a first message for accessing the logic unit;
the first judgment module is used for generating and sending a read command to the logic unit if the first message indicates to read the logic unit;
the second acquisition module is used for acquiring a second message for accessing the same logic unit;
the second judgment module is used for generating and sending a 'quick reading' command to the logic unit if the second message indicates to read the logic unit; and
the receiving module is used for receiving read data provided by the logic unit in response to the read command;
the command of fast reading is one of the commands of 'Read Cache' series conforming to ONFI standard or one of the commands of 'Cache Read' series conforming to TOGGLE standard; a "fast read" command is sent to the logical unit as a response to the second message obtained to access the same logical unit.
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